CN111246662A - Carrier plate structure and manufacturing method thereof - Google Patents
Carrier plate structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN111246662A CN111246662A CN201811440489.9A CN201811440489A CN111246662A CN 111246662 A CN111246662 A CN 111246662A CN 201811440489 A CN201811440489 A CN 201811440489A CN 111246662 A CN111246662 A CN 111246662A
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- layer
- glass substrate
- circuit layer
- dielectric layer
- inner circuit
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention provides a carrier plate structure and a manufacturing method thereof. The glass substrate is provided with a first surface, a second surface opposite to the first surface and at least one through hole penetrating through the glass substrate. The buffer layers are arranged on the first surface and the second surface of the glass substrate. The inner circuit layer is arranged on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a portion of the buffer layer.
Description
Technical Field
The present disclosure relates to carrier structures, and particularly to a carrier structure with a buffer layer and a method for fabricating the same.
Background
Currently, glass substrates are widely used as intermediate substrate materials for carrier (superstrate) or intermediate (interposer) substrates with high-level requirements due to their special surface flatness. However, due to its fragile characteristic, after a thick copper inner layer circuit is fabricated on the surface of a glass substrate by using a conventional carrier manufacturing method, such as a semi-additive process (SAP), a micro crack (micro crack) which is small and not easy to be found by naked eyes or a microscope is easily generated due to stress, so that the thick copper inner layer circuit is easily separated from the glass substrate, and the glass substrate cannot pass the verification of reliability (such as TCT, HAST, PCT, or the like).
Disclosure of Invention
The invention provides a carrier plate structure, wherein a circuit layer is arranged on the surface of a glass substrate and has better reliability.
The invention provides a manufacturing method of a carrier plate structure, which is used for manufacturing the carrier plate structure, can avoid the generation of micro cracks on a glass substrate and can improve the adhesion capability of a circuit layer on the surface of the glass substrate.
The carrier plate structure comprises a glass substrate, a buffer layer and an inner circuit layer. The glass substrate is provided with a first surface, a second surface opposite to the first surface and at least one through hole penetrating through the glass substrate. The buffer layers are arranged on the first surface and the second surface of the glass substrate. The inner circuit layer is arranged on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a portion of the buffer layer.
In an embodiment of the invention, the inner circuit layer and the glass substrate are respectively located at two opposite sides of the buffer layer.
In an embodiment of the invention, the buffer layer directly contacts the glass substrate. The buffer layer completely covers the first surface and the second surface of the glass substrate.
In an embodiment of the invention, the carrier structure further includes a first dielectric layer, a second dielectric layer, at least one first conductive via, a first circuit layer, at least one second conductive via, and a second circuit layer. The first dielectric layer and the second dielectric layer are arranged on the glass substrate and fill the through hole. The first dielectric layer covers the first surface and part of the inner circuit layer, and the second dielectric layer covers the second surface and part of the inner circuit layer. The first conductive via penetrates the first dielectric layer. The first circuit layer is configured on the first dielectric layer and is electrically connected with the inner circuit layer through the first conductive through hole. The second conductive via penetrates the second dielectric layer. The second circuit layer is configured on the second dielectric layer and is electrically connected with the inner circuit layer through the second conductive through hole.
In an embodiment of the invention, the carrier structure further includes a first solder mask layer and a second solder mask layer. The first solder mask layer is disposed on the first dielectric layer and covers the first dielectric layer and a portion of the first circuit layer. The second solder mask layer is disposed on the second dielectric layer and covers the second dielectric layer and a portion of the second circuit layer.
In an embodiment of the invention, the buffer layer is disposed in the through hole of the glass substrate and located between the inner circuit layer and the glass substrate.
In an embodiment of the invention, a material of the buffer layer includes an inorganic material or an organic polymer material.
In an embodiment of the invention, the thickness of the buffer layer is between 10 nanometers and 50 micrometers.
In an embodiment of the invention, a thickness of the inner circuit layer is between 1 micron and 30 microns.
The manufacturing method of the carrier plate structure comprises the following steps. First, a glass substrate is provided. The glass substrate is provided with a first surface, a second surface opposite to the first surface and at least one through hole penetrating through the glass substrate. Then, buffer layers are formed on the first surface and the second surface of the glass substrate. And then, forming an inner circuit layer on the buffer layer and in the through hole of the glass substrate. Wherein, the inner circuit layer exposes part of the buffer layer.
In an embodiment of the invention, the method for manufacturing the carrier structure further includes the following steps. First, press the first dielectric layer and the second dielectric layer on the glass substrate and fill the through hole. The first dielectric layer covers the first surface and part of the inner circuit layer, and the second dielectric layer covers the second surface and part of the inner circuit layer. Then, at least one first conductive through hole is formed, and the first conductive through hole penetrates through the first dielectric layer. Then, a first circuit layer is formed on the first dielectric layer and electrically connected with the inner circuit layer through the first conductive through hole. And then, forming at least one second conductive through hole which penetrates through the second dielectric layer. And then, forming a second circuit layer on the second dielectric layer, wherein the second circuit layer is electrically connected with the inner circuit layer through the second conductive through hole.
In an embodiment of the invention, the method for manufacturing the carrier structure further includes the following steps. First, a first solder mask layer is formed on the first dielectric layer, and the first solder mask layer covers the first dielectric layer and a portion of the first circuit layer. Then, a second solder mask layer is formed on the second dielectric layer, and the second solder mask layer covers the second dielectric layer and a portion of the second circuit layer.
In view of the above, in the carrier structure and the manufacturing method thereof of the present invention, the carrier structure includes a glass substrate, a buffer layer, and an inner circuit layer. The buffer layers are arranged on the first surface and the second surface of the glass substrate, the inner circuit layer is arranged on the buffer layers and in the through holes of the glass substrate, and part of the buffer layers are exposed out of the inner circuit layer. By means of the design, the surface of the glass substrate of the carrier plate structure of the invention is provided with the circuit layer, and the carrier plate structure has better reliability. In addition, the manufacturing method of the carrier plate structure of the invention can avoid the glass substrate from generating micro cracks and can improve the adhesion capability of the circuit layer on the surface of the glass substrate.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a method for manufacturing a carrier structure according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view illustrating a carrier structure according to another embodiment of the invention.
[ notation ] to show
100. 100 a: support plate structure
110: glass substrate
111: first surface
112: second surface
113: through hole
120: buffer layer
130: inner layer circuit layer
132: first inner layer circuit layer
134: second inner layer circuit layer
136: third inner layer circuit layer
140: a first dielectric layer
142: a second dielectric layer
150: a first conductive via
152: second conductive via
160: first circuit layer
162: second circuit layer
170: first solder mask layer
172: second solder mask
P1: first pad
P2: second pad
Detailed Description
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a method for manufacturing a carrier structure according to an embodiment of the invention.
First, referring to fig. 1A, in the present embodiment, a glass substrate 110 is provided. In detail, the glass substrate 110 has a first surface 111, a second surface 112 opposite to the first surface 111, and at least one through hole 113 (fig. 1A schematically shows 1 through hole, but not limited thereto) penetrating through the glass substrate 110. Wherein the through hole 113 connects the first surface 111 and the second surface 112. In the present embodiment, the through hole is formed by drilling the glass substrate 110 with a laser, for example, but the invention is not limited thereto.
Next, referring to fig. 1B, in the present embodiment, a buffer layer 120 is formed on the first surface 111, the second surface 112, and the through hole 113 of the glass substrate 110. The buffer layer 120 may directly contact the glass substrate 110, and the buffer layer 120 may completely cover the first surface 111 and the second surface 112 of the glass substrate 110. In detail, in the present embodiment, the buffer layer 120 is formed on the glass substrate 110 by, for example, sputtering or coating, but not limited thereto. The coating method may be, for example, a physical vapor deposition method, an immersion method, or the like, or coating using a slit coater, but is not limited thereto. In the present embodiment, the thickness of the buffer layer 120 can be between 10 nanometers and 50 micrometers. In the present embodiment, the material of the buffer layer 120 is, for example, an inorganic material or an organic polymer material. In some embodiments, the material of the buffer layer 120 may be, for example, a non-conductive oxide or an insulating material. For example, the material of the buffer layer 120 may be silicon dioxide or ABF resin, but is not limited thereto.
Then, referring to fig. 1C, in the present embodiment, an inner circuit layer 130 is formed on the buffer layer 120 and in the through hole 113 of the glass substrate 110, and a portion of the buffer layer 120 is exposed. In detail, in the present embodiment, the inner circuit layer 130 includes a first inner circuit layer 132, a second inner circuit layer 134, and a third inner circuit layer 136. The first inner circuit layer 132 is formed on the buffer layer 120 on the first surface 111 of the glass substrate 110, the second inner circuit layer 134 is formed on the buffer layer 120 on the second surface 112 of the glass substrate 110, and the third inner circuit layer 136 is formed in the through hole 113 of the glass substrate 110. Therefore, the first inner circuit layer 132 and the glass substrate 110 are respectively located at two opposite sides of the buffer layer 120, the second inner circuit layer 134 and the glass substrate 110 are respectively located at two opposite sides of the buffer layer 120, and the buffer layer 120 in the through hole 113 is located between the third inner circuit layer 136 and the glass substrate 110. In addition, the first inner circuit layer 132 exposes a portion of the buffer layer 120 on the first surface 111, and the second inner circuit layer 134 exposes a portion of the buffer layer 120 on the second surface 112. In the present embodiment, the inner circuit layer 130 is formed by electroplating, for example, and includes the following steps: a seed layer is formed on the first surface 111, the second surface 112 and the through hole 113 of the glass substrate 110, a patterned photoresist layer is formed, a conductive material is used for electroplating, and finally the patterned photoresist layer and the seed layer below the patterned photoresist layer are removed, so that the inner circuit layer 130 is manufactured. The conductive material may be copper, for example, and the thickness of the inner circuit layer 130 may be between 1 micron and 30 microns, for example. It should be noted that, although the inner circuit layer 130 is formed in the above manner and steps in the present embodiment, the invention is not limited thereto.
Referring to fig. 1D, in the present embodiment, one or more circuit layers may be further fabricated on the inner circuit layer 130. Here, for example, a circuit layer is formed on the first inner circuit layer 132 and the second inner circuit layer 134, and the method includes the following steps: first, the first dielectric layer 140 and the second dielectric layer 142 are laminated on the glass substrate 110 and the through hole 113 is filled, such that the first dielectric layer 140 covers the first surface 111 and the first inner circuit layer 132, and the second dielectric layer 142 covers the second surface 112 and the second inner circuit layer 134. Next, at least one first conductive via 150 (fig. 1D schematically shows 2, but not limited thereto) is formed, and the first conductive via 150 penetrates through the first dielectric layer 140. At least one second conductive via 152 (fig. 1D schematically shows 2, but not limited thereto) is formed, and the second conductive via 152 penetrates through the second dielectric layer 142. Then, a first circuit layer 160 is formed on the first dielectric layer 140, and the first circuit layer 160 is electrically connected to the first inner circuit layer 132 through the first conductive via 150. The second circuit layer 162 is formed on the second dielectric layer 142, and the second circuit layer 162 can be electrically connected to the second inner circuit layer 134 through the second conductive via 152. Here, the first circuit layer 160 and the second circuit layer 162 are formed by electroplating, for example, and the method and the steps are similar to those of the inner circuit layer 130, so that the detailed description is not repeated.
Finally, referring to fig. 1E, in the present embodiment, a first solder mask layer 170 is formed on the first dielectric layer 140, and a second solder mask layer 172 is formed on the second dielectric layer 142. The first solder mask layer 170 covers the first dielectric layer 140 and a portion of the first circuit layer 160 and exposes a portion of the first circuit layer 160. The second solder mask layer 172 covers the second dielectric layer 142 and a portion of the second circuit layer 162 and exposes a portion of the second circuit layer 162. Thus, a portion of the first circuit layer 160 exposed by the first solder mask layer 170 may be defined as a first pad P1, and a portion of the second circuit layer 162 exposed by the second solder mask layer 172 may be defined as a second pad P2. Therefore, the carrier structure 100 can be electrically connected to an external circuit through the first pads P1 and the second pads P2. At this time, the carrier structure 100 of the present embodiment is completed.
In short, in the carrier structure 100 of the present embodiment, the carrier structure 100 includes a glass substrate 110, a buffer layer 120, and an inner circuit layer 130. The glass substrate 110 has a first surface 111, a second surface 112 opposite to the first surface 111, and a through hole 113 penetrating through the glass substrate 110. The buffer layer 120 is disposed on the first surface 111 and the second surface 112 of the glass substrate 110. The inner circuit layer 130 is disposed on the buffer layer 120 and in the through hole 113 of the glass substrate 110. The inner wiring layer 130 exposes a portion of the buffer layer 120. By this design, the inner circuit layer 130 can be formed on the surface of the glass substrate 110 of the carrier structure 100 of the present embodiment, and the carrier structure has a better reliability. In addition, the manufacturing method of the carrier structure of the embodiment can also prevent the glass substrate 110 from generating micro cracks, and can improve the adhesion capability of the inner circuit layer 130 on the surface of the glass substrate 110.
Other examples will be listed below for illustration. It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
Fig. 2 is a schematic cross-sectional view illustrating a carrier structure according to another embodiment of the invention. Referring to fig. 1E and fig. 2, a carrier structure 100a of the present embodiment is similar to the carrier structure 100 of fig. 1E, but the main difference between the two is: in the carrier board structure 100a of the present embodiment, the buffer layer 120 is not formed in the through hole 113 of the glass substrate 110. That is, there is no buffer layer between the third inner wiring layer 136 within the via hole 113 and the glass substrate 110, so that the third inner wiring layer 136 within the via hole 113 may directly contact the glass substrate 110.
In summary, in the carrier structure and the manufacturing method thereof of the present invention, the carrier structure includes a glass substrate, a buffer layer and an inner circuit layer. The buffer layers are arranged on the first surface and the second surface of the glass substrate, the inner circuit layer is arranged on the buffer layers and in the through holes of the glass substrate, and part of the buffer layers are exposed out of the inner circuit layer. By means of the design, the surface of the glass substrate of the carrier plate structure of the invention is provided with the circuit layer, and the carrier plate structure has better reliability. In addition, the manufacturing method of the carrier plate structure of the invention can avoid the glass substrate from generating micro cracks and can improve the adhesion capability of the circuit layer on the surface of the glass substrate.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (18)
1. A carrier structure, comprising:
the glass substrate is provided with a first surface, a second surface opposite to the first surface and at least one through hole penetrating through the glass substrate;
the buffer layers are configured on the first surface and the second surface of the glass substrate; and
the inner circuit layer is configured on the buffer layer and in the through hole of the glass substrate, and part of the buffer layer is exposed out of the inner circuit layer.
2. The carrier board structure of claim 1, wherein the inner circuit layer and the glass substrate are respectively located on two opposite sides of the buffer layer.
3. The carrier plate structure of claim 1, wherein the buffer layer directly contacts the glass substrate and the buffer layer completely covers the first and second surfaces of the glass substrate.
4. The carrier plate structure of claim 1, further comprising:
a first dielectric layer and a second dielectric layer disposed on the glass substrate and filling the through hole, wherein the first dielectric layer covers the first surface and a portion of the inner circuit layer, and the second dielectric layer covers the second surface and a portion of the inner circuit layer;
at least one first conductive via through the first dielectric layer;
the first circuit layer is configured on the first dielectric layer and is electrically connected with the inner circuit layer through the first conductive through hole;
at least one second conductive via through the second dielectric layer; and
and the second circuit layer is configured on the second dielectric layer and is electrically connected with the inner circuit layer through the second conductive through hole.
5. The carrier plate structure of claim 4, further comprising:
a first solder mask layer disposed on the first dielectric layer and covering the first dielectric layer and a portion of the first circuit layer; and
and the second solder mask layer is configured on the second dielectric layer and covers the second dielectric layer and part of the second circuit layer.
6. The carrier structure of claim 1, wherein the buffer layer is disposed in the through hole of the glass substrate and between the inner circuit layer and the glass substrate.
7. The carrier plate structure of claim 1, wherein the material of the buffer layer comprises an inorganic material or an organic polymer material.
8. The carrier plate structure of claim 1, wherein the buffer layer has a thickness between 10 nanometers and 50 micrometers.
9. The carrier board structure of claim 1, wherein the thickness of the inner circuit layer is between 1 micron and 30 microns.
10. A manufacturing method of a carrier plate structure comprises the following steps:
providing a glass substrate, wherein the glass substrate is provided with a first surface, a second surface opposite to the first surface and at least one through hole penetrating through the glass substrate;
forming buffer layers on the first surface and the second surface of the glass substrate; and
and forming an inner circuit layer on the buffer layer and in the through hole of the glass substrate, wherein part of the buffer layer is exposed out of the inner circuit layer.
11. The method of claim 10, wherein the inner circuit layer and the glass substrate are respectively disposed on two opposite sides of the buffer layer.
12. The method of claim 10, wherein the buffer layer directly contacts the glass substrate and completely covers the first surface and the second surface of the glass substrate.
13. The method of manufacturing a carrier plate structure of claim 10, further comprising:
laminating a first dielectric layer and a second dielectric layer on the glass substrate and filling the through hole, wherein the first dielectric layer covers the first surface and part of the inner circuit layer, and the second dielectric layer covers the second surface and part of the inner circuit layer;
forming at least one first conductive via, wherein the first conductive via penetrates through the first dielectric layer;
forming a first circuit layer on the first dielectric layer, wherein the first circuit layer is electrically connected with the inner circuit layer through the first conductive through hole;
forming at least one second conductive through hole, wherein the second conductive through hole penetrates through the second dielectric layer; and
and forming a second circuit layer on the second dielectric layer, wherein the second circuit layer is electrically connected with the inner circuit layer through the second conductive through hole.
14. The method of manufacturing a carrier plate structure of claim 13, further comprising:
forming a first solder mask layer on the first dielectric layer, wherein the first solder mask layer covers the first dielectric layer and a part of the first circuit layer; and
and forming a second solder mask layer on the second dielectric layer, wherein the second solder mask layer covers the second dielectric layer and part of the second circuit layer.
15. The method of claim 10, wherein the buffer layer is disposed in the through hole of the glass substrate and between the inner circuit layer and the glass substrate.
16. The method of claim 10, wherein the buffer layer comprises an inorganic material or an organic polymer material.
17. The method of claim 10, wherein the thickness of the buffer layer is between 10 nm and 50 μm.
18. The method of claim 10, wherein the thickness of the inner circuit layer is between 1 micron and 30 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811440489.9A CN111246662A (en) | 2018-11-29 | 2018-11-29 | Carrier plate structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811440489.9A CN111246662A (en) | 2018-11-29 | 2018-11-29 | Carrier plate structure and manufacturing method thereof |
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| CN111246662A true CN111246662A (en) | 2020-06-05 |
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| CN201811440489.9A Pending CN111246662A (en) | 2018-11-29 | 2018-11-29 | Carrier plate structure and manufacturing method thereof |
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Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1116943A (en) * | 1997-06-27 | 1999-01-22 | Sony Corp | Semiconductor device and its manufacture |
| JPH11274372A (en) * | 1998-03-19 | 1999-10-08 | Toshiba Corp | Semiconductor device and its semiconductor package |
| JP2000188309A (en) * | 1998-12-22 | 2000-07-04 | Hitachi Cable Ltd | Stiffener and tab tape with the stiffener |
| US20040079643A1 (en) * | 2002-10-29 | 2004-04-29 | Noritaka Ban | Method for manufacturing wiring substrates |
| CN102187472A (en) * | 2008-10-20 | 2011-09-14 | 出光兴产株式会社 | Photovoltaic element and method for manufacturing the same |
| CN103458629A (en) * | 2012-05-30 | 2013-12-18 | 富葵精密组件(深圳)有限公司 | Multi-layer circuit board and manufacturing method thereof |
| CN103531594A (en) * | 2013-10-30 | 2014-01-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN103596373A (en) * | 2013-11-07 | 2014-02-19 | 南京邮电大学 | Integrated circuit plate manufacturing method based on copper nitride film |
| CN103613289A (en) * | 2013-11-22 | 2014-03-05 | 华进半导体封装先导技术研发中心有限公司 | Method for electroless copper plating on glass substrate |
| CN103985810A (en) * | 2014-05-28 | 2014-08-13 | 深圳力合光电传感股份有限公司 | LED glass and manufacturing technology thereof |
| CN203912323U (en) * | 2014-06-11 | 2014-10-29 | 深圳华麟电路技术有限公司 | Location hole structure of flexible/hard multilayer circuit board |
| CN205124121U (en) * | 2015-11-30 | 2016-03-30 | 胜华电子（惠阳）有限公司 | PCB circuit board |
| CN105578710A (en) * | 2014-11-05 | 2016-05-11 | 三星电机株式会社 | Printed circuit board and method of manufacturing the same |
| US20160374198A1 (en) * | 2015-06-18 | 2016-12-22 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board |
| CN108699673A (en) * | 2016-02-29 | 2018-10-23 | 三井金属矿业株式会社 | The manufacturing method of copper foil with carrier and centreless supporter and printed circuit board with wiring layer |
-
2018
- 2018-11-29 CN CN201811440489.9A patent/CN111246662A/en active Pending
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1116943A (en) * | 1997-06-27 | 1999-01-22 | Sony Corp | Semiconductor device and its manufacture |
| JPH11274372A (en) * | 1998-03-19 | 1999-10-08 | Toshiba Corp | Semiconductor device and its semiconductor package |
| JP2000188309A (en) * | 1998-12-22 | 2000-07-04 | Hitachi Cable Ltd | Stiffener and tab tape with the stiffener |
| US20040079643A1 (en) * | 2002-10-29 | 2004-04-29 | Noritaka Ban | Method for manufacturing wiring substrates |
| CN102187472A (en) * | 2008-10-20 | 2011-09-14 | 出光兴产株式会社 | Photovoltaic element and method for manufacturing the same |
| CN103458629A (en) * | 2012-05-30 | 2013-12-18 | 富葵精密组件(深圳)有限公司 | Multi-layer circuit board and manufacturing method thereof |
| CN103531594A (en) * | 2013-10-30 | 2014-01-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN103596373A (en) * | 2013-11-07 | 2014-02-19 | 南京邮电大学 | Integrated circuit plate manufacturing method based on copper nitride film |
| CN103613289A (en) * | 2013-11-22 | 2014-03-05 | 华进半导体封装先导技术研发中心有限公司 | Method for electroless copper plating on glass substrate |
| CN103985810A (en) * | 2014-05-28 | 2014-08-13 | 深圳力合光电传感股份有限公司 | LED glass and manufacturing technology thereof |
| CN203912323U (en) * | 2014-06-11 | 2014-10-29 | 深圳华麟电路技术有限公司 | Location hole structure of flexible/hard multilayer circuit board |
| CN105578710A (en) * | 2014-11-05 | 2016-05-11 | 三星电机株式会社 | Printed circuit board and method of manufacturing the same |
| US20160374198A1 (en) * | 2015-06-18 | 2016-12-22 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board |
| CN205124121U (en) * | 2015-11-30 | 2016-03-30 | 胜华电子（惠阳）有限公司 | PCB circuit board |
| CN108699673A (en) * | 2016-02-29 | 2018-10-23 | 三井金属矿业株式会社 | The manufacturing method of copper foil with carrier and centreless supporter and printed circuit board with wiring layer |
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Application publication date: 20200605 |