CN111221378B - Clock domain conversion method and device of periodic signal and readable storage medium - Google Patents
Clock domain conversion method and device of periodic signal and readable storage medium Download PDFInfo
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Abstract
The invention provides a clock domain conversion method, a device and a readable storage medium of periodic signals, which adopt the periodic signals of a receiving source clock domain, wherein the periodic signals of the source clock domain are obtained by sampling the clock signals of the source clock domain; sampling a periodic signal of a source clock domain by using a current clock domain to obtain a synchronous signal; creating a cycle clock counter; extracting the rising edge of the synchronous signal, and synchronizing the counting starting point of the cycle clock counter to the first rising edge of the synchronous signal; determining whether the cycle clock counter is synchronous with the synchronous signal or not according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal; when the cycle clock counter keeps synchronous with the synchronous signal, the technical scheme of generating the periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter effectively avoids signal jitter and signal loss caused by the sampling process of clock domain conversion, and further provides a stable and reliable periodic signal for the clock domain conversion.
Description
Technical Field
The present invention relates to computer technologies, and in particular, to a clock domain conversion method and apparatus for a periodic signal, and a readable storage medium.
Background
During the signal transmission of digital circuit systems, it is often necessary to switch a periodic signal from one clock domain to another clock domain, so that processing units or computation units in different clock domains can process the signal depending on the periodic signal.
The clock domain conversion of the existing periodic signal can adopt the following two ways:
the first method is to directly sample the periodic signal output by the source clock domain by using the clock signal of the current clock domain to obtain the sampled periodic signal of the current clock domain. However, when the periodic signal output by the source clock domain is sampled, the sampled periodic signal of the current clock domain may generate clock jitter, so that the sampled periodic signal may not be the periodic signal any more, but may have one clock cycle less or one clock cycle more, and a jitter phenomenon exists.
The second method is to use a memory such as a RAM or a FIFO to perform asynchronous clock domain isolation on signals, to write the periodic signals output by the source clock domain into the memory, and to read the periodic signals from the memory in the current clock domain, wherein the read signals are the periodic signals of the current clock domain. However, the periodic signal of the current clock domain obtained by such a conversion method has strong dependency on the periodic signal output by the source clock domain, and once the periodic signal output by the source clock domain is lost, the periodic signal of the current clock domain is also lost.
Therefore, none of the existing clock domain conversion methods can provide a stable sampled periodic signal for the current clock domain.
Disclosure of Invention
In view of the above-mentioned problem that the sampled periodic signal provided by the conventional clock domain conversion method is not stable enough and cannot meet the actual use requirement, the present invention provides a clock domain conversion method and apparatus for a periodic signal, and a readable storage medium.
In one aspect, the present invention provides a clock domain conversion method for a periodic signal, including:
receiving a periodic signal of a source clock domain, wherein the periodic signal of the source clock domain is obtained by sampling a clock signal of the source clock domain;
sampling the periodic signal of the source clock domain by using the current clock domain to obtain a synchronous signal;
creating a cycle clock counter;
extracting a rising edge of the synchronous signal, and synchronizing a counting starting point of the cycle clock counter to a first rising edge of the synchronous signal;
determining whether the cycle clock counter is synchronous with the synchronous signal according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal;
and when the cycle clock counter keeps synchronous with the synchronous signal, generating a periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter.
In an alternative embodiment, the determining whether the cycle clock counter is synchronized with the synchronization signal according to the synchronization of the cycle clock counter with the next rising edge of the synchronization signal includes:
judging whether the next rising edge of the synchronous signal is aligned with a preset counting interval of the cycle clock counter or not;
if yes, the cycle clock counter keeps synchronous with the synchronous signal;
if not, the cycle clock counter is not synchronous with the synchronous signal.
In an alternative embodiment, when the cycle clock counter is not synchronized with the synchronization signal, the method further comprises:
and re-extracting the rising edge of the synchronous signal, resetting the counting period of the cycle clock counter, and re-returning to the step of synchronizing the counting starting point of the cycle clock counter to the first rising edge of the synchronous signal.
In an optional implementation manner, the determining whether the cycle clock counter is synchronized with the synchronization signal according to the synchronicity of the cycle clock counter and the next rising edge of the synchronization signal further includes:
and if the synchronous signal has no next rising edge, directly generating a periodic signal of the current clock domain according to the counting starting point and the counting period of the current cycle clock counter, and generating a prompt message of the loss of the periodic signal of the source clock domain.
In an alternative embodiment, the count period of the cycle clock counter is from 0 to N, where N is a positive integer;
the preset counting interval comprises N-M, 0 and M; wherein M is a positive integer less than N.
In another aspect, the present invention provides a clock domain converting apparatus for a periodic signal, including:
the clock signal sampling circuit comprises a signal input end, a signal output end and a clock signal output end, wherein the signal input end is used for receiving a periodic signal of a source clock domain, and the periodic signal of the source clock domain is obtained by sampling a clock signal of the source clock domain;
the sampling circuit is used for sampling the periodic signal of the source clock domain by utilizing the current clock domain to obtain a synchronous signal;
the cycle clock counter is used for synchronizing the counting starting point of the created cycle clock counter to the first rising edge of the synchronous signal according to the rising edge of the extracted synchronous signal; the clock synchronization device is also used for determining whether the cycle clock counter is synchronous with the synchronous signal or not according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal;
and the periodic signal generator is used for generating a periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter when the cycle clock counter keeps synchronous with the synchronous signal.
In an optional implementation manner, the cycle clock counter is specifically configured to determine whether a next rising edge of the synchronization signal is aligned with a preset counting interval of the cycle clock counter; if yes, the cycle clock counter keeps synchronous with the synchronous signal; if not, re-extracting the rising edge of the synchronous signal, resetting the counting period of the cycle clock counter, and re-returning to the step of synchronizing the counting starting point of the cycle clock counter to the first rising edge of the synchronous signal.
In an optional implementation manner, the periodic signal generator is further configured to, when the cycle clock counter determines that the synchronization signal does not have the next rising edge, generate a periodic signal of the current clock domain according to a count start point and a count period of the current cycle clock counter, and generate a notification message that the periodic signal of the source clock domain is lost.
In another aspect, the present invention provides a clock domain converting apparatus for a periodic signal, including:
a processor;
a memory for storing executable instructions of the processor;
the processor, when executing the executable instructions, may perform the method of any of claims 1-5 above.
In a final aspect, the invention provides a readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the method of any of claims 1 to 5.
The invention provides a clock domain conversion method, a clock domain conversion device and a readable storage medium of a periodic signal, which adopt the receiving of the periodic signal of a source clock domain, wherein the periodic signal of the source clock domain is obtained by sampling the clock signal of the source clock domain; sampling the periodic signal of the source clock domain by using the current clock domain to obtain a synchronous signal; creating a cycle clock counter; extracting a rising edge of the synchronous signal, and synchronizing a counting starting point of the cycle clock counter to a first rising edge of the synchronous signal; determining whether the cycle clock counter is synchronous with the synchronous signal according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal; when the cycle clock counter keeps synchronous with the synchronous signal, the technical scheme of generating the periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter effectively avoids signal jitter and signal loss caused by the sampling process of clock domain conversion, and further provides a stable and reliable periodic signal for the clock domain conversion.
Drawings
With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific embodiments.
FIG. 1 is a schematic diagram of a network architecture on which the present invention is based;
fig. 2 is a flowchart illustrating a clock domain conversion method of a periodic signal according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating relationships among signals in a clock domain conversion method of a periodic signal according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a clock domain conversion method of a periodic signal according to a second embodiment of the present invention;
fig. 5 is a schematic diagram illustrating relationships among signals in a clock domain conversion method of a periodic signal according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of a clock domain conversion apparatus for periodic signals according to a third embodiment of the present invention;
fig. 7 is a schematic diagram of a hardware structure of a clock domain conversion apparatus for periodic signals according to a fourth embodiment of the present invention.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
During the signal transmission of digital circuit systems, it is often necessary to switch a periodic signal from one clock domain to another clock domain, so that processing units or computation units in different clock domains can process the signal depending on the periodic signal.
The clock domain conversion of the existing periodic signal can adopt the following two ways:
the first method is to directly sample the periodic signal output by the source clock domain by using the clock signal of the current clock domain to obtain the sampled periodic signal of the current clock domain. However, when the periodic signal output by the source clock domain is sampled, the sampled periodic signal of the current clock domain may generate clock jitter, so that the sampled periodic signal may not be the periodic signal any more, but may have one clock cycle less or one clock cycle more, and a jitter phenomenon exists.
The second method is to use a memory such as a RAM or a FIFO to perform asynchronous clock domain isolation on signals, to write the periodic signals output by the source clock domain into the memory, and to read the periodic signals from the memory in the current clock domain, wherein the read signals are the periodic signals of the current clock domain. However, the periodic signal of the current clock domain obtained by such a conversion method has strong dependency on the periodic signal output by the source clock domain, and once the periodic signal output by the source clock domain is lost, the periodic signal of the current clock domain is also lost.
The invention provides a clock domain conversion method and device of a periodic signal and a readable storage medium. The clock domain conversion method, the clock domain conversion device and the readable storage medium of the periodic signal can be applied to various scenes needing to perform cross-clock domain signal processing, and the scenes include but are not limited to: data processing based on a multi-base station system, terminal data processing based on multiple chips and the like. Similarly, a clock domain exists in each execution main body for processing data in each application scenario, and the signal frequencies of the clock domains of different execution main bodies may be the same or different, but each execution main body needs to perform data processing on a synchronous periodic signal in its corresponding clock domain to realize the cooperative operation of each execution main body.
Therefore, in order to solve the above-mentioned problem that the periodic signal provided by the conventional clock domain conversion method is not stable enough and cannot meet the actual use requirement, fig. 1 is a schematic diagram of a network architecture based on the present invention, as shown in fig. 1, the network architecture based on the present invention at least includes: a plurality of execution units 1, and a clock domain conversion device 2 of periodic signals which are arranged in each execution unit 1 or are electrically connected with the execution units 1 one by one. Based on different scenes of the execution unit, the execution unit has different hardware forms, such as a chip, a base station, a terminal and the like; meanwhile, based on the difference of the hardware form of the execution unit, the clock domain conversion device 2 of the periodic signal may be a hardware structure installed in the execution unit 1, or may be a hardware structure electrically connected to the execution unit 1.
For example, based on the foregoing data processing scenario based on a multi-base-station system, the clock domain conversion device for periodic signals may be installed inside each base station and electrically connected to the processing system of the base station; for another example, in the scenario of multi-chip-based terminal data processing, the clock domain conversion device for periodic signals may be a hardware circuit connected between chips.
Fig. 2 is a flowchart illustrating a clock domain conversion method of a periodic signal according to an embodiment of the present invention.
As shown in fig. 2, the clock domain conversion method of the periodic signal includes:
And 102, sampling the periodic signal of the source clock domain by using the current clock domain to obtain a synchronous signal.
And 104, extracting the rising edge of the synchronous signal, and synchronizing the counting start point of the cycle clock counter to the first rising edge of the synchronous signal.
And 105, determining whether the cycle clock counter keeps synchronous with the synchronous signal according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal.
And 106, when the cycle clock counter keeps synchronous with the synchronous signal, generating a periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter.
It should be noted that the main body of the implementation of the clock domain conversion method for periodic signals provided in this embodiment may be specifically the clock domain conversion apparatus 2 for periodic signals shown in fig. 1.
Specifically, in order to solve the problem that the periodic signal provided by the existing clock domain conversion method mentioned in the prior art is not stable enough and cannot meet the actual use requirement, a cycle clock counter is established in the present application, so that a cycle counting mechanism of the cycle clock counter is utilized to synchronize the synchronous signal obtained by acquiring the periodic signal of the source clock domain from the current clock domain, and the cycle clock counter with the stable counting period and completing synchronization is utilized to generate the periodic signal of the current clock domain.
Fig. 3 is a schematic diagram of relationship between signals in a clock domain conversion method of a periodic signal according to an embodiment of the present invention, and in order to explain this embodiment, a scheme will be described below by taking the schematic diagram of relationship between signals shown in fig. 3 as an example.
Specifically, the clock signal frequency of the source clock domain is 61.44MHz, and the clock signal frequency of the current clock domain is 122.88MHz, where the source clock domain is the clock domain on which the synchronized execution units are based, and the current clock domain is the clock domain on which the synchronized execution units are based.
First, the execution units to be synchronized or the clock domain conversion device based on the periodic signal of the execution units to be synchronized can sample the periodic signal of 10ms by using the clock signal of 61.44MHz of the source clock domain to obtain the periodic signal shown in fig. 3, and obtain the periodic signal shown in fig. 3. The periodic signal is sent to the clock domain conversion device of the periodic signal based on the present embodiment.
Then, the clock domain conversion device of the periodic signal samples the received periodic signal based on the clock signal of 122.88MHz of the current clock domain to obtain the synchronous signal. Under the condition that the received periodic signal is a normal signal and no signal jitter or signal loss occurs in the sampling process, based on the difference of sampling points, the synchronous signal obtained by sampling in the current clock domain will have four cases as shown in fig. 3, namely synchronous signal a, synchronous signal B, synchronous signal C and synchronous signal D. The four kinds of synchronous signals are synchronous signals which can be used and accepted in the clock domain crossing data processing process, namely when the four kinds of synchronous signals exist, no jitter or loss of sampling signals occurs in the process of sampling the signals. In other words, when the synchronization signal sampled by the clock domain conversion device of the periodic signal is not in the four cases, signal jitter or loss may occur during the sampling process of the synchronization signal, and the sampled synchronization signal does not satisfy the periodicity and stability during the synchronization process, and cannot be used.
In order to obtain a signal with a stable period and a high synchronization with the periodic signal of the original clock domain, in this embodiment, the clock domain converting apparatus of the periodic signal creates a cyclic clock counter, and the initial counting period of the cyclic clock counter needs to be the same as the signal period of the periodic signal, i.e. 10 ms. In other words, the cycle clock counter will start counting from a value of 0 up to 1228799 and return to a value of 0 at the next counting moment, thus repeating the cycle count.
Then, based on the acquired synchronization signal, the clock domain conversion device of the periodic signal will extract the rising edge of the synchronization signal, and set the cycle clock counter to 0 at the time of the first extracted rising edge, so that the counting start point of the cycle clock counter is kept synchronous with the first rising edge, and then the cycle clock counter will start counting according to the aforementioned counting period.
Then, the clock domain switching device of the periodic signal monitors the synchronism of the next rising edge and the counting period thereof, and determines whether the cycle clock counter is kept synchronous with the synchronous signal according to the monitoring result. When the cycle clock counter is found to be synchronous with the synchronous signal, the clock domain conversion device of the periodic signal can generate the periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter.
Further, taking the signal relationship diagram shown in fig. 3 as an example, when the synchronicity of the synchronization signal is determined in the above manner, if the synchronization signal satisfies the above four conditions, the counting condition of the cycle clock counter should be as shown in the counting sequence a and the counting sequence B in fig. 3:
if the acquired current clock domain synchronous signals are synchronous signals A and B, the counting sequence obtained by the cycle clock counter corresponds to the counting sequence A, and the next rising edge in the synchronous signals A and B respectively corresponds to the numerical values 0 and 1 in the counting sequence A, at this time, the cycle clock counter is determined to be synchronous with the synchronous signals, and the clock domain conversion device of the periodic signals can obtain the periodic signals A of the current clock domain according to the counting sequence A.
If the acquired current clock domain synchronization signal is a synchronization signal C and a synchronization signal D, the counting sequence obtained by the cycle clock counter corresponds to the counting sequence B, and in the synchronization signal C and the synchronization signal D, the next rising edge corresponds to the values 1228799 and 0 in the counting sequence B, respectively, at this time, the cycle clock counter has already determined to be synchronized with the synchronization signal, and the clock domain conversion device of the cycle signal can obtain the cycle signal B of the current clock domain according to the counting sequence B.
That is, in the present embodiment, it is determined whether the current cycle clock counter is synchronized with the acquired synchronization signal of the current clock domain by determining whether the next rising edge of the synchronization signal is aligned with the preset counting interval of the cycle clock counter, and in the case that the cycle clock counter is synchronized with the synchronization signal, the period signal of the current clock domain is generated according to the counting start point and the counting period of the cycle clock counter, i.e., the illustrated counting sequence. And under the condition that the cycle clock counter is not kept synchronous with the synchronous signal, resetting the counting start point and the counting period of the cycle clock counter, returning to the step of extracting the rising edge of the synchronous signal and synchronizing the counting start point of the reset cycle clock counter to the first rising edge of the synchronous signal until the cycle clock counter is kept synchronous with the synchronous signal.
Of course, it should be noted that 1228799, 0 and 1 are only exemplary, and in practical use, the cycle count period of the cycle clock counter is from 0 to N, where N is a positive integer; the preset counting interval comprises N-M, 0 and M; wherein, M is a positive integer smaller than N, and both N and M can be set by a person skilled in the art.
The clock domain conversion method for the periodic signal provided by the embodiment of the invention adopts the steps of receiving the periodic signal of a source clock domain, wherein the periodic signal of the source clock domain is obtained by sampling the clock signal of the source clock domain; sampling the periodic signal of the source clock domain by using the current clock domain to obtain a synchronous signal; creating a cycle clock counter; extracting a rising edge of the synchronous signal, and synchronizing a counting starting point of the cycle clock counter to a first rising edge of the synchronous signal; determining whether the cycle clock counter is synchronous with the synchronous signal according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal; when the cycle clock counter keeps synchronous with the synchronous signal, the technical scheme of generating the periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter effectively avoids signal jitter and signal loss caused by the sampling process of clock domain conversion, and further provides a stable and reliable periodic signal for the clock domain conversion.
On the basis of the first embodiment, in order to further improve the stability of the periodic signal, fig. 4 is a flowchart illustrating a clock domain conversion method of the periodic signal according to a second embodiment of the present invention.
As shown in fig. 4, the clock domain conversion method of the periodic signal includes:
And step 204, synchronizing the counting start point of the cycle clock counter to the first rising edge of the synchronization signal.
if not, go to step 207; if yes, go to step 206.
And step 206, generating a period signal of the current clock domain according to the counting start point and the counting period of the cycle clock counter.
if yes, go to step 208; if not, go to step 209.
And step 208, re-extracting the rising edge of the synchronous signal, and resetting the counting period of the cycle clock counter.
Returning to step 204.
And 209, generating a periodic signal of the current clock domain directly according to the counting start point and the counting period of the current cycle clock counter, and generating a prompt message that the periodic signal of the source clock domain is lost.
Similar to the foregoing embodiments, the main body of the implementation of the clock domain conversion method for periodic signals provided in this embodiment may specifically be the clock domain conversion apparatus 2 for periodic signals shown in fig. 1.
In this embodiment, fig. 4 is a schematic diagram of relationship among signals in a clock domain conversion method of a periodic signal according to a second embodiment of the present invention, and in order to explain this embodiment, a scheme will be described below by taking the schematic diagram of relationship among signals shown in fig. 3 as an example.
Specifically, the clock signal frequency of the source clock domain is 61.44MHz, and the clock signal frequency of the current clock domain is 122.88MHz, wherein the source clock domain is the clock domain based on which the synchronized execution units are based, and the current clock domain is the clock domain based on which the synchronized execution units are based.
Similar to the previous embodiment, the synchronized execution unit or the clock domain conversion device based on the periodic signal of the synchronized execution unit may sample the 10ms periodic signal with the 61.44MHz clock signal of the source clock domain, resulting in the periodic signal shown in fig. 3. The periodic signal is sent to the clock domain conversion device of the periodic signal based on the present embodiment. Then, the clock domain conversion device of the periodic signal samples the received periodic signal based on the clock signal of 122.88MHz of the current clock domain to obtain the synchronous signal.
Then, the clock domain conversion device of the periodic signal samples the received periodic signal based on the clock signal of 122.88MHz of the current clock domain to obtain the synchronous signal. Under the condition that the received periodic signal is a normal signal and no signal jitter or signal loss occurs in the sampling process, based on the difference of sampling points, there are two cases, namely, a synchronization signal a and a synchronization signal B, in the synchronization signal obtained by sampling in the current clock domain as shown in fig. 4. In order to obtain a signal with a stable period and a high synchronization with the periodic signal of the original clock domain, in this embodiment, the clock domain converting apparatus of the periodic signal creates a cyclic clock counter, and the initial counting period of the cyclic clock counter needs to be the same as the signal period of the periodic signal, i.e. 10 ms. In other words, the cycle clock counter will start counting from a value of 0 up to 1228799 and return to a value of 0 at the next counting moment, thus repeating the cycle count.
Then, based on the acquired synchronization signal, the clock domain conversion device of the periodic signal will extract the rising edge of the synchronization signal, and set the cycle clock counter to 0 at the time of the first extracted rising edge, so that the counting start point of the cycle clock counter is kept synchronous with the first rising edge, and then the cycle clock counter will start counting according to the aforementioned counting period.
Then, the clock domain switching device of the periodic signal monitors the synchronism of the next rising edge and the counting period thereof, and determines whether the cycle clock counter is kept synchronous with the synchronous signal according to the monitoring result. When the cycle clock counter is found to be synchronous with the synchronous signal, the clock domain conversion device of the periodic signal can generate the periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter.
Different from the foregoing embodiment, in this embodiment, after determining whether the next rising edge of the synchronization signal is aligned with the preset counting interval of the cycle clock counter, if it is found that the next rising edge of the synchronization signal does not exist, the clock domain conversion device of the periodic signal generates the periodic signal of the current clock domain directly according to the counting start point and the counting period of the current cycle clock counter, and generates the notification message indicating that the periodic signal of the source clock domain is lost.
Specifically, as shown in a synchronization signal E in fig. 5, a synchronization signal sampled in a current clock domain is unstable, and a problem of loss of the periodic signal is inevitable due to instability of the periodic signal of a source clock domain, at this time, a clock domain conversion device receiving device of the periodic signal may receive the periodic signal with only one signal period, and accordingly, the acquired synchronization signal also includes only one signal period, and the synchronization signal E also has only one rising edge, that is, after the clock domain conversion device of the periodic signal finishes setting a cycle clock counter to 0 at a time of the first extracted rising edge, a determination result that the synchronization signal does not have a next rising edge is obtained, and the determination result means that the periodic signal has been lost. At this time, the clock domain converting device of the periodic signal can directly generate the periodic signal C of the current clock domain according to the counting start and the counting period of the cycle clock counter, i.e. the counting sequence C, so as to ensure that the periodic signal of the current clock domain is stable, and of course, the new periodic signal has the same signal period as the periodic signal of the source clock domain.
Meanwhile, in this embodiment, when the clock domain converter of the periodic signal determines that the next rising edge of the synchronization signal exists, i.e. the synchronization signal F shown in fig. 5, the clock domain converter of the periodic signal re-extracts the rising edge of the synchronization signal, resets the counting period of the cycle clock counter, and returns to the step of synchronizing the counting start point of the cycle clock counter to the first rising edge of the synchronization signal again until the counting sequence D is obtained. Specifically, due to signal jitter during sampling, the clock domain conversion apparatus for the periodic signal may obtain the synchronization signal as an aperiodic signal by sampling the periodic signal of the source clock domain by using the current clock domain. At this time, the rising edge of the synchronization signal may be extracted again, the counting period of the cycle clock counter may be reset, and the cycle clock counter and the counting start point may be reset, so as to ensure synchronization with the synchronization signal, and on this basis, if it is still not ensured that the next rising edge of the synchronization signal is aligned with the preset counting interval of the cycle clock counter, the periodic signal of the original clock domain may be an aperiodic signal.
In any case, during the resetting of the cycle clock counter, the obtained counting sequence should be the counting sequence D shown in fig. 4, and the periodic signal of the current clock domain generated according to the counting sequence D should also be the periodic signal D of the current clock domain.
Of course, it should be noted that 1228799, 0 and 1 are only exemplary, and in practical use, the cycle count period of the cycle clock counter is from 0 to N, where N is a positive integer; the preset counting interval comprises N-M, 0 and M; wherein, M is a positive integer less than N, and both N and M can be set by a person skilled in the art.
In the clock domain conversion method for the periodic signal provided in the second embodiment of the present invention, based on the first embodiment, the periodic signal of the current clock domain is generated according to the counting start point and the counting period of the current cyclic clock counter, and a prompt message indicating that the periodic signal of the source clock domain is lost is generated, so that the signal stability obtained by clock domain conversion is further improved.
Fig. 6 is a schematic structural diagram of a clock domain converting device of a periodic signal according to a third embodiment of the present invention, as shown in fig. 6, the clock domain converting device of the periodic signal includes:
a signal input terminal 10, configured to receive a periodic signal of a source clock domain, where the periodic signal of the source clock domain is obtained by sampling a clock signal of the source clock domain;
a sampling circuit 20, configured to sample a periodic signal of the source clock domain by using a current clock domain to obtain a synchronization signal;
a cycle clock counter 30 for synchronizing a start point of counting of the created cycle clock counter to a first rising edge of the synchronization signal according to the extraction of the rising edge of the synchronization signal; the clock synchronization device is also used for determining whether the cycle clock counter is synchronous with the synchronous signal or not according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal;
and a periodic signal generator 40, configured to generate a periodic signal of the current clock domain according to a count start point and a count period of the cycle clock counter when the cycle clock counter keeps synchronous with the synchronization signal.
Optionally, the cycle clock counter 30 is specifically configured to determine whether a next rising edge of the synchronization signal is aligned with a preset counting interval of the cycle clock counter; if yes, the cycle clock counter keeps synchronous with the synchronous signal; if not, re-extracting the rising edge of the synchronous signal, resetting the counting period of the cycle clock counter, and re-returning to the step of synchronizing the counting starting point of the cycle clock counter to the first rising edge of the synchronous signal.
Optionally, the periodic signal generator 40 is further configured to, when the cycle clock counter determines that the synchronization signal does not have a next rising edge, generate a periodic signal of the current clock domain according to a count start point and a count period of the current cycle clock counter, and generate a notification message that the periodic signal of the source clock domain is lost.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process and corresponding beneficial effects of the system described above may refer to the corresponding process in the foregoing method embodiment, and are not described herein again.
The clock domain conversion device for the periodic signal provided by the third embodiment of the invention adopts a receiving source clock domain periodic signal, wherein the source clock domain periodic signal is obtained by sampling a source clock domain clock signal;
sampling the periodic signal of the source clock domain by using the current clock domain to obtain a synchronous signal; creating a cycle clock counter; extracting a rising edge of the synchronous signal, and synchronizing a counting starting point of the cycle clock counter to a first rising edge of the synchronous signal; determining whether the cycle clock counter is synchronous with the synchronous signal according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal; when the cycle clock counter keeps synchronous with the synchronous signal, the technical scheme of generating the periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter effectively avoids signal jitter and signal loss caused by the sampling process of clock domain conversion, and further provides a stable and reliable periodic signal for the clock domain conversion.
In other embodiments, fig. 7 is a schematic diagram of a hardware structure of a clock domain conversion apparatus for periodic signals according to a fourth embodiment of the present invention. As shown in fig. 7, the clock domain converting apparatus of the periodic signal may specifically include:
a processor 42;
a memory 41 for storing processor-executable instructions;
wherein the processor 42 is configured to:
receiving a periodic signal of a source clock domain, wherein the periodic signal of the source clock domain is obtained by sampling a clock signal of the source clock domain;
sampling the periodic signal of the source clock domain by using the current clock domain to obtain a synchronous signal;
creating a cycle clock counter;
extracting a rising edge of the synchronous signal, and synchronizing a counting starting point of the cycle clock counter to a first rising edge of the synchronous signal;
determining whether the cycle clock counter is synchronous with the synchronous signal according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal;
and when the cycle clock counter keeps synchronous with the synchronous signal, generating a periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter.
The memory 41 may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like. And processor 42 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital signal processor architectures (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessor architectures or other electronic components.
The above-mentioned instructions can be written by using languages such as C/C + +, Java, Shell, Python, etc., which is not limited in this embodiment.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process and corresponding beneficial effects of the system described above may refer to the corresponding process in the foregoing method embodiment, and are not described herein again.
The clock domain conversion device for the periodic signal provided by the fourth embodiment of the present invention receives the periodic signal of the source clock domain, where the periodic signal of the source clock domain is obtained by sampling the clock signal of the source clock domain; sampling the periodic signal of the source clock domain by using the current clock domain to obtain a synchronous signal; creating a cycle clock counter; extracting a rising edge of the synchronous signal, and synchronizing a counting starting point of the cycle clock counter to a first rising edge of the synchronous signal; determining whether the cycle clock counter is synchronous with the synchronous signal according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal; when the cycle clock counter keeps synchronous with the synchronous signal, the technical scheme of generating the periodic signal of the current clock domain according to the counting starting point and the counting period of the cycle clock counter effectively avoids signal jitter and signal loss caused by the sampling process of clock domain conversion, and further provides a stable and reliable periodic signal for the clock domain conversion.
The invention provides a readable storage medium, which comprises instructions, when the instructions are run on the computer, the computer can execute the method of any of the first embodiment or the second embodiment.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (8)
1. A method for clock domain conversion of a periodic signal, comprising:
receiving a periodic signal of a source clock domain, wherein the periodic signal of the source clock domain is obtained by sampling a clock signal of the source clock domain;
sampling the periodic signal of the source clock domain by using the current clock domain to obtain a synchronous signal;
creating a cycle clock counter;
extracting a rising edge of the synchronous signal, and synchronizing a counting starting point of the cycle clock counter to a first rising edge of the synchronous signal;
determining whether the cycle clock counter is synchronous with the synchronous signal according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal;
when the cycle clock counter keeps synchronous with the synchronous signal, generating a periodic signal of a current clock domain according to a counting starting point and a counting period of the cycle clock counter;
when the cycle clock counter is not synchronous with the synchronous signal, the rising edge of the synchronous signal is extracted again, the counting period of the cycle clock counter is reset, and the step of synchronizing the counting starting point of the cycle clock counter to the first rising edge of the synchronous signal is returned again.
2. The method of claim 1, wherein the determining whether the cycle clock counter is synchronized with the synchronization signal according to the synchronicity of the cycle clock counter with a next rising edge of the synchronization signal comprises:
judging whether the next rising edge of the synchronous signal is aligned with a preset counting interval of the cycle clock counter or not;
if yes, the cycle clock counter keeps synchronous with the synchronous signal;
if not, the cycle clock counter is not synchronous with the synchronous signal.
3. The method according to claim 1 or 2, wherein the determining whether the cycle clock counter is synchronized with the synchronization signal according to the synchronicity of the cycle clock counter with a next rising edge of the synchronization signal further comprises:
and if the synchronous signal has no next rising edge, directly generating a periodic signal of the current clock domain according to the counting starting point and the counting period of the current cycle clock counter, and generating a prompt message of the loss of the periodic signal of the source clock domain.
4. The method according to claim 1, wherein the count period of the cycle clock counter is from 0 to N, wherein N is a positive integer;
the preset counting interval comprises N-M; wherein M is a positive integer less than N.
5. An apparatus for clock domain conversion of a periodic signal, comprising:
the clock signal sampling circuit comprises a signal input end, a signal output end and a clock signal output end, wherein the signal input end is used for receiving a periodic signal of a source clock domain, and the periodic signal of the source clock domain is obtained by sampling a clock signal of the source clock domain;
the sampling circuit is used for sampling the periodic signal of the source clock domain by utilizing the current clock domain to obtain a synchronous signal;
the cycle clock counter is used for synchronizing the counting starting point of the created cycle clock counter to the first rising edge of the synchronous signal according to the rising edge of the extracted synchronous signal; the clock synchronization device is also used for determining whether the cycle clock counter is synchronous with the synchronous signal or not according to the synchronism of the cycle clock counter and the next rising edge of the synchronous signal;
the periodic signal generator is used for generating a periodic signal of a current clock domain according to the counting starting point and the counting period of the cycle clock counter when the cycle clock counter keeps synchronous with the synchronous signal;
the cycle clock counter is specifically configured to determine whether a next rising edge of the synchronization signal is aligned with a preset counting interval of the cycle clock counter; if yes, the cycle clock counter keeps synchronous with the synchronous signal; if not, re-extracting the rising edge of the synchronous signal, resetting the counting period of the cycle clock counter, and re-returning to the step of synchronizing the counting starting point of the cycle clock counter to the first rising edge of the synchronous signal.
6. The apparatus of claim 5, wherein the periodic signal generator is further configured to generate the periodic signal of the current clock domain according to a count start point and a count period of the current cycle clock counter and generate a notification message indicating that the periodic signal of the source clock domain is lost when the cycle clock counter determines that the synchronization signal does not have a next rising edge.
7. An apparatus for clock domain conversion of a periodic signal, comprising:
a processor;
a memory for storing executable instructions of the processor;
the processor, when executing the executable instructions, may perform the method of any of claims 1-4 above.
8. A readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the method of any of claims 1-4.
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| CN114185396A (en) * | 2021-07-19 | 2022-03-15 | 芯华章科技股份有限公司 | Designed clock domain conversion method, verification system and storage medium |
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