CN111143068A

CN111143068A - File operation method and device and embedded controller

Info

Publication number: CN111143068A
Application number: CN201911378573.7A
Authority: CN
Inventors: 黄越华; 龚义萍; 陈雪峰
Original assignee: Guangdong Bozhilin Robot Co Ltd
Current assignee: Guangdong Bozhilin Robot Co Ltd
Priority date: 2019-12-27
Filing date: 2019-12-27
Publication date: 2020-05-12
Anticipated expiration: 2039-12-27
Also published as: CN111143068B

Abstract

The application discloses a file operation method, a file operation device and an embedded controller, and relates to the technical field of embedded control. Wherein, the method comprises the following steps: performing data transmission operation on the storage equipment through the DMA controller, waiting for the data transmission operation to be executed, and starting suspensible abnormal interrupt in the process of waiting for the data transmission operation to be executed; the target task is executed by an interrupt service routine that can suspend the abort. Therefore, the resources of the embedded controller can be released in the process of waiting for the transmission operation to be executed, so that the target task can be executed, and the resources are saved.

Description

File operation method and device and embedded controller

Technical Field

The present disclosure relates to the field of embedded control technologies, and in particular, to a file operation method and apparatus, and an embedded controller.

Background

In the field of embedded control, an embedded controller is often required to perform a data transmission operation on a storage device, and after a data transmission operation is performed once, the embedded controller needs to wait for the data of the operation to complete transmission and then perform the next transmission, which results in waste of processing resources of the embedded controller.

Disclosure of Invention

In view of the foregoing problems, the present application provides a file operating method, a file operating apparatus, and an embedded controller to improve the foregoing problems.

In a first aspect, an embodiment of the present application provides a file operating method, which is applied to an embedded controller electrically connected to a storage device, where the embedded controller includes a direct memory access DMA controller, and the method includes: performing, by the DMA controller, a data transfer operation on the storage device; waiting for the data transmission operation to be executed, and starting suspensible abnormal interruption in the process of waiting for the data transmission operation to be executed; executing a target task by the interrupt service routine that can suspend the abort.

In a second aspect, an embodiment of the present application provides a file operating apparatus, which is applied to an embedded controller electrically connected to a storage device, where the embedded controller includes a direct memory access DMA controller, and the apparatus includes: the operation module is used for executing data transmission operation on the storage device through the DMA controller; the waiting module is used for waiting for the completion of the execution of the data transmission operation and starting suspensible abnormal interruption in the process of waiting for the completion of the execution of the data transmission operation; executing a target task by the interrupt service routine that can suspend the abort.

In a third aspect, an embodiment of the present application provides an embedded controller, including: one or more processors; a memory; one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the methods described above.

In a fourth aspect, the present application provides a computer-readable storage medium, in which a program code is stored, and the program code can be called by a processor to execute the above method.

Compared with the prior art, the scheme provided by the application releases the processing resources of the embedded controller in the process that the embedded controller waits for the completion of the data transmission operation through the suspendable abnormal interruption for executing the target task, so that the utilization rate of the processing resources of the embedded controller is improved, and the waste of the processing resources is reduced.

These and other aspects of the present application will be more readily apparent from the following description of the embodiments.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a schematic diagram of an application environment suitable for the embodiment of the present application.

FIG. 2 shows a flowchart of a file manipulation method according to one embodiment of the present application.

FIG. 3 shows a flowchart of a file manipulation method according to another embodiment of the present application.

Fig. 4 is another flow chart diagram illustrating the file operation method shown in fig. 3.

Fig. 5 is a block diagram of an embedded controller for executing a file operation method according to an embodiment of the present application.

Fig. 6 shows a block diagram of a file manipulation device according to an embodiment of the present application.

Fig. 7 is a storage unit according to an embodiment of the present application, configured to store or carry program code for implementing a file operation method according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

The embedded controller may perform data transfer operations on the storage device, such as read operations to retrieve data from the storage device and transfer the data to the embedded controller, or write operations to transfer data to the storage device for storage. After the embedded controller executes the read operation, it needs to wait for the data to be read, and after the write operation is executed, it needs to wait for the data to be written, and in the waiting process, the processing resources of the embedded controller are not used and are in an idle state, which results in the waste of the processing resources.

The inventor provides a file operation method, a file operation device and an embedded controller through long-term research, and can release unused processing resources of the embedded controller in a data transmission process for executing other tasks, so that the utilization rate of the processing resources of the embedded controller can be improved.

Referring to fig. 1, fig. 1 is a schematic diagram of an application environment suitable for the embodiment of the present application. The embedded controller 100 is electrically connected to the Memory device 200, and the Memory device 200 may be any Memory device based on a semiconductor flash Memory, such as an SD Memory Card (Secure Digital Memory Card). The embedded controller may be any microcontroller capable of performing data transfer operations on the memory device, such as a single chip microcomputer with an arm (advanced RISC machines) core-M core, such as STM 32.

The embedded controller 100 and the storage DEVICE 200 may communicate via an SDIO (Secure Digital Input and output) bus, where the embedded controller 100 is an SDIO HOST (HOST) terminal and the storage DEVICE 200 is an SDIO DEVICE (DEVICE) terminal.

The embedded controller 100 may include a processor 101 and a Direct Memory Access (DMA) controller 102, the DMA controller 102 being electrically connected to the processor 101. In the case that the embedded controller 100 is configured in the DMA transfer mode, when data transfer is required, the processor 101 may give control to the DMA controller 102 over the SDIO bus, and the DMA controller 102 may implement data transfer with the storage device 200 over the SDIO bus.

Referring to fig. 2, fig. 2 is a flowchart illustrating a file operating method according to an embodiment of the present application, where the method can be applied to the embedded controller 100 shown in fig. 1. The steps of the method are explained below.

In step S110, a data transfer operation is performed on the storage device by the DMA controller 102.

In view of the fact that the data transfer operation performed by the DMA controller 102 can bypass the processor 101, thereby improving the data transfer efficiency and avoiding resource occupation of the processor 101, in this embodiment, the embedded controller 100 may be configured to perform data transfer in a DMA transfer mode.

Wherein the data transfer operation may be a read operation or a write operation. In detail, the processor 101 may call a read function for causing the DMA controller 102 to read data from the storage device 200 through the SDIO bus when the embedded controller 100 is in the DMA transfer mode, the read data being transferred to a data buffer of the DMA controller through the SDIO bus. The processor 101 may invoke a write function to implement a write operation that is used to cause the DMA controller 102 to write data to the storage device 200 over the SDIO bus while the embedded controller 100 is in the DMA transfer mode.

Step S120, waiting for the completion of the data transmission operation, and starting a suspendable exception (PendSV) interrupt in the process of waiting for the completion of the data transmission operation.

And step S130, executing a target task through the interrupt service program capable of suspending the abnormal interrupt.

The processor 101 may call a wait-to-read function after each read operation is performed, for waiting for the read operation to be performed. The processor 101 may call a wait-to-write function after each write operation is performed, for waiting for the write operation to be performed.

In this embodiment, an instruction for starting a suspensible abort may be added to the wait-to-read function and the wait-to-write function. The suspendable abort may be configured to have the lowest priority, and may be preempted by any interrupt, and the interrupt service routine of the suspendable abort is only responded when the priority of the suspendable abort is the currently highest priority, so that the starting of the suspendable abort does not affect the processing of other interrupts in the embedded controller 100.

In the implementation process, the DMA transfer process does not involve the processor 101, and while waiting for the data transfer operation (e.g., the read operation or the write operation) to be performed, the processor 101 does not perform other processes, and the processing resources thereof are idle. Therefore, in the embodiment, the task instruction needing to be executed is added to the interrupt service program capable of suspending the abnormal interrupt, so that the target task can be processed in the interrupt service program capable of suspending the abnormal interrupt. And the target task is the task instruction needing to be executed. Furthermore, since the DMA transfer process does not participate in the processor 101, the processing of the interrupt service routine that can suspend the abort does not affect the DMA transfer process.

The process shown in fig. 2 releases the idle processing resources in the process of waiting for data transmission by setting suspendable abnormal interrupts, so as to execute the required tasks, thereby improving the resource utilization efficiency of the embedded controller 100 and avoiding resource waste.

Referring to fig. 3, fig. 3 is a flowchart illustrating a file operating method according to another embodiment of the present application, where the method can be applied to the embedded controller 100 shown in fig. 1. The flow of the process is illustrated below.

Step S210, migrating the preset file system to the embedded controller 100.

Step S220, the driver of the storage device 200 is migrated to the embedded controller 100.

In step S230, the DMA controller 100 performs a data transfer operation on the storage device 200, and starts a DMA interrupt each time the data transfer operation is completed.

In this embodiment, in order to implement normal communication between the embedded controller 100 and the storage device 200, first, an interface function of the storage device 200 may be configured, taking the storage device 200 as an SD memory card as an example, a General-purpose input/output (GPIO) pin connected to a data pin of the storage device 200 may be configured to multiplex push-pull output, pull up an interface level (i.e., a level of the data pin) of the SD memory card, and configure an output frequency of the data pin as 50 MHz. In addition, a GPIO pin bus clock connected with a data pin of the SD memory card can be started.

The embedded controller may then be configured, for example where the embedded controller 100 is STM32, to enable DMA channels of STM32 and to enable DMA interrupts. In detail, the STM32 has two DMA controllers, DMA1 and DMA2, respectively, and illustratively, may enable channels 3 and 6 of the DMA2 and open a DMA interrupt channel of the interrupt controller.

In this embodiment, a preset File system for organizing and managing data in the storage device 200 may be deployed on the storage device 200, and the preset File system may be, for example, a File Allocation Table File System (FATFS). The default file system provides a bottom interface function for operating data in the storage device 200, such as a disk read function, a disk write function, a disk initialization function, a disk state function, a disk IO (input/output) control function, an RCT (Real _ Time _ Clock) acquisition function, and the like. In order to allow the embedded controller 100 to normally operate the storage device 200, a driver of the storage device 200 may also be ported into the embedded controller.

The migration process will be described below by taking the default file system as FATFS and the storage device 200 as an SD memory card as an example.

In the implementation process, parameters may be set for the configuration file of the migrated FATFS during the process of migrating the FATFS to the embedded controller 100. For example, the long filename support of FATFS may be turned on, the dynamic working buffer of the heap area for the long filename is enabled, and the sector size for read and write operations is set to 512 bytes. For another example, a disk initialization function may be modified, the SD memory card initialization function in the SD memory card driver is called in the disk initialization function, and the first value is set as a return value to represent that initialization is successful. Wherein the first value may be 0, for example.

For another example, a disk state function may be modified, an SD memory card state obtaining function in a driver of the SD memory card is called in the disk state function, and the second value is set as a return value to represent that the state obtaining is successful. Wherein the second value and the first value may be the same or different. Illustratively, the second value may be 0. For another example, the information related to the SD memory card can be transferred to the data buffer in the embedded controller 100 for receiving the data transmitted by the SD memory card according to the parameters given by the FAFTS. The related information may comprise, for example, a defined data block size, a number of data blocks, etc.

In this embodiment, for target data to be transmitted, multiple data transmission operations are usually required to complete the transmission of the target data. For example, the desired target data1 may be read from the memory device 200 through a plurality of read operations, each of which may read a part of the data of the target data 1; for another example, the target data2 may be written to the storage device 200 by a plurality of write operations, each of which may write a part of the data of the target data2 to the storage device 200.

In the implementation process, data transmission is generally performed in units of data blocks, and based on this, the disk operation function may be modified in the process of migrating the preset file system to the embedded controller 100, and specifically, the data block operation function in the driver of the storage device 200 may be called in the disk operation function. The data block operation function comprises a DMA transmission instruction which is used for transmitting the data block in the target data needing to be transmitted. Based on this modification, the step of performing the data transfer operation on the storage device by the DMA controller in step S230 can be implemented by the following flow:

and calling a data block operation function in a driver of the storage device 200 through a disk operation function of a preset file system of the storage device 200 to perform DMA transfer on a data block in target data through a DMA transfer instruction in the data block function.

Optionally, in this embodiment, different data block operation functions may be called according to the number of bytes of data to be transmitted (for example, the number of bytes of target data). For example, when the number of bytes of data to be transmitted does not exceed the target number of bytes, a single data block operation function is called; the multiple data block operation function may be invoked when the number of bytes of data to be transmitted exceeds the target number of bytes. The target byte number may be 512 bytes, for example. Thus, the efficiency of data operation can be improved.

When the preset file system is FATFS, the disk operation function may be a disk read function or a disk write function, and correspondingly, the data block operation function may be a data block read function or a data block write function. Further, the data block read function may include a multiple data block read function and a multiple single data block read function, and the data block write function may include a multiple data block write function and a single data block write function.

As described above, the embedded controller 100 requires one or more data transfer operations to complete the transfer of the target data. Because the DMA transfer mode is adopted and the DMA interrupt is turned on, when the DMA transfer is performed once, that is, when the data transfer operation (for example, a read operation or a write operation) is performed once, a DMA interrupt request is generated, and the DMA interrupt request is sent to the processor 101, and the processor 101 may execute an interrupt service routine of the DMA interrupt, so as to implement subsequent processing, for example, checking and the like, on the transferred data.

Step S240, waiting for the data transmission operation to be completed.

Step S250, in the process of waiting for the data transmission operation to be completed, detecting whether the storage device is in a busy state. If not, go to step S260; if yes, go to step S270.

In step S260, no processing is performed.

Step S270, open suspendable abort.

Step S280, executing a target task through the interrupt service program capable of suspending the abnormal interrupt.

The memory device 200 is typically in a busy state when in the middle of a data transfer. Based on this, in this embodiment, the disk state function may be called in the read waiting function and the write waiting function to acquire the state of the storage device 200, and identify the acquired state, and when the identified state is a busy state, the suspendable exception interrupt may be started. In the implementation process, target tasks needing to be executed can be added to the interrupt service program capable of suspending the abnormal interrupt according to needs.

It will be appreciated that when a DMA interrupt is generated, the processor 101 will stop executing the interrupt service routine that may suspend the abort during the execution of the interrupt service routine for the DMA interrupt. In the event that the DMA interrupt ends, but the target data has not been transferred to completion, the processor 101 may continue executing the interrupt service routine that may suspend the abort.

In this embodiment, for the case that the target data needs multiple data transmission operations, in the process of waiting for the data transmission operation to be executed for the ith time (i is an integer greater than or equal to 2), the suspendable abnormal interrupt is already in the on state, and only the suspendable abnormal interrupt needs to be controlled to continue to be in the on state.

Step S290, when the target data is completely transmitted, ending the suspendable abort.

In this embodiment, when the multiple data transfer operations for the target data are completed, it may be determined that the target data transfer is completed, and thus the suspendable abort may be ended, that is, the suspendable abort is exited.

Alternatively, in this embodiment, whether the target data is completely transmitted may be detected through the flow shown in fig. 4, which is explained below.

Step S410, detecting whether the DMA interrupt is in an end state. If yes, go to step S420; if not, go to step S450.

Optionally, in this embodiment, whether the DMA interrupt is currently in the ending state may be determined by detecting the DMA interrupt flag bit.

In step S420, it is detected whether the DMA controller 102 is in a transfer complete state. If yes, go to step S430; if not, go to step S450.

Illustratively, a value of the DMA _ sxnttr register may be read, which indicates the number of data blocks that the DMA controller needs to transfer, and if the read value is 0, it may be determined that the DMA controller 102 is already in a transfer complete state.

In step 430, it is detected whether the memory device 200 is in a data operation complete state. If yes, go to step S440; if not, go to step S450.

Step S440, determining that the target data is completely transmitted.

In this embodiment, when the data transfer operation is a write operation, the value of the TXACT bit of the SDIO _ STA register may be read in real time, and when the read value is 1, it indicates that the write is successful, i.e., the data operation is in a complete state. Correspondingly, when the data transfer operation is a read operation, the value of the RXACT bit of the SDIO _ STA register may be read in real time, and if the read value is 1, it indicates that the read is successful, i.e., the data operation is in a complete state.

In step S450, control may suspend the abort in the ON state.

When the determination result of any one of the above steps S410 to S430 is negative, the suspensible abort may be continuously maintained in the on state.

By the file operation method provided by the embodiment, the utilization rate of processor resources of the embedded controller can be improved, and the waste of the processor resources is avoided.

Referring to fig. 5, a block diagram of an embedded controller 100 according to an embodiment of the present disclosure is shown. The embedded controller 100 may be any embedded microcontroller. The embedded controller device 100 in the present application may include one or more of the following components: a processor 101, a DMA controller 102, a memory 103, and one or more programs, wherein the one or more programs may be stored in the memory 103 and configured to be executed by the one or more processors 101, the one or more programs configured to perform the methods as described in the foregoing method embodiments.

Processor 101 may include one or more processing cores. The processor 101 connects various parts within the overall embedded controller 100 using various interfaces and lines, performs various functions of the embedded controller 100 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 103, and calling data stored in the memory 103. Optionally, the processor 101 may be implemented by an ARM Cortex-M based core, for example, an ARM core-M0, an M0+, an M3, an M4, and an M7 core, which is not limited in this embodiment. The processor 101 may be implemented by being externally connected to at least one hardware form of a Digital Signal Processing (DSP), a Field-Programmable gate Array (FPGA), and a Programmable Logic Array (PLA). The processor 110 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications.

The Memory 103 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 103 may be used to store instructions, programs, code sets or instruction sets. The memory 103 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The stored data area may also store data (e.g., various status data) created by the embedded controller 100 in use, and the like.

It is understood that the structure shown in fig. 5 is only an illustration, and the embedded controller 100 may also include more or less components than those shown in fig. 5, or have a completely different configuration from that shown in fig. 5, and the present embodiment is not limited thereto. For example, the embedded controller 100 may further include an SDIO module that may communicate with an SDIO interface of the storage device 200 through an SDIO bus. An SDIO module may generally include an SDIO adapter, which may provide SDIO host-side functions, such as may provide an SD clock, send commands, and perform data transfers, and an APB2(Advanced Peripheral Bus 2) interface. The APB2 interface may provide the DMA controller with access to registers of the SDIO adapter and may generate interrupts, as well as DMA request signals.

Referring to fig. 6, a block diagram of a file operating apparatus 600 according to an embodiment of the present disclosure is shown. The file operating apparatus 600 may include: an operation module 610 and a wait module 620.

The operation module 610 is configured to perform a transfer operation on target data in the storage device through the DMA controller.

The waiting module 620 is configured to wait for the transmission operation to be completed, and start a suspensible abort during the process of waiting for the transmission operation to be completed; executing a target task by the interrupt service routine that can suspend the abort.

Optionally, in this embodiment of the application, the manner for starting the suspensible abort by the waiting module 620 in the process of waiting for the completion of the execution of the data transmission operation may be:

detecting whether the storage equipment is in a busy state or not in the process of waiting for the data transmission operation to be executed; if so, the suspendable abort is turned on.

Optionally, in this embodiment of the present application, one data transmission operation is used to transmit at least part of the target data. In this case, the wait module 620 may be further configured to end the suspendable abort when the target data is completely transferred.

Optionally, in this embodiment of the present application, the apparatus 600 may further include a detection module.

The detection module may be to: starting DMA interruption when the data transmission operation is executed each time; detecting whether the DMA interruption is in an ending state; if the DMA interruption is in the ending state, detecting whether the DMA controller is in a transmission completion state; if the DMA controller is in a transmission completion state, detecting whether the storage equipment is in a data operation completion state; and if the storage equipment is in a transmission completion state, determining that the target data is completely transmitted.

The detection module may trigger the waiting module 620 to perform a corresponding operation when determining that the target data is completely transmitted.

Optionally, the manner of the waiting module 620 performing the data transfer operation on the storage device through the DMA controller may be:

and calling a data block operation function in a driver of the storage device through a disk operation function of a preset file system of the storage device, wherein the data block operation function comprises a DMA transmission instruction and is used for performing DMA transmission on a data block in the target data.

Alternatively, the waiting module 620 may call a data block operation function in a driver of the storage device by:

when the number of bytes of data to be transmitted does not exceed the target number of bytes, calling a single data block operation function; and calling a multi-data block operation function when the number of bytes of the data to be transmitted exceeds the target number of bytes.

Optionally, in this embodiment of the present application, the apparatus 600 may further include a transplantation module.

The migration module may be to: migrating the preset file system into the embedded controller 100; the driver of the storage device is migrated into the embedded controller 100.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses and modules may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, the coupling or direct coupling or communication connection between the modules shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or modules may be in an electrical, mechanical or other form.

In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

Referring to fig. 7, a block diagram of a computer-readable storage medium according to an embodiment of the present application is shown. The computer-readable medium 700 has stored therein program code that can be called by a processor to perform the methods described in the above-described method embodiments.

The computer-readable storage medium 700 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium 700 includes a non-transitory computer-readable storage medium. The computer readable storage medium 700 has storage space for program code 710 to perform any of the method steps of the method described above. The program code can be read from or written to one or more computer program products. The program code 710 may be compressed, for example, in a suitable form.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A method for operating a file, the method being applied to an embedded controller electrically connected to a storage device, the embedded controller including a Direct Memory Access (DMA) controller, the method comprising:

performing, by the DMA controller, a data transfer operation on the storage device;

waiting for the data transmission operation to be executed, and starting suspensible abnormal interruption in the process of waiting for the data transmission operation to be executed;

executing a target task by the interrupt service routine that can suspend the abort.

2. The method of claim 1, wherein turning on a suspendable abort while waiting for the data transfer operation to be performed comprises:

detecting whether the storage equipment is in a busy state or not in the process of waiting for the data transmission operation to be executed;

if so, the suspendable abort is turned on.

3. The method of claim 1 or 2, wherein one of the data transfer operations is used to transfer at least part of the target data, the method further comprising:

ending the suspendable abort when the target data is completed transferred.

4. The method of claim 3, further comprising:

starting DMA interruption when the data transmission operation is executed each time;

detecting whether the DMA interruption is in an ending state;

if the DMA interruption is in the ending state, detecting whether the DMA controller is in a transmission completion state;

if the DMA controller is in a transmission completion state, detecting whether the storage equipment is in a data operation completion state;

and if the storage equipment is in a transmission completion state, determining that the target data is completely transmitted.

5. The method of claim 1 or 2, wherein the performing, by the DMA controller, a data transfer operation on the storage device comprises:

6. The method of claim 5, wherein said invoking a data block manipulation function in a driver of said storage device comprises:

when the number of bytes of data to be transmitted does not exceed the target number of bytes, calling a single data block operation function;

and calling a multi-data block operation function when the number of bytes of the data to be transmitted exceeds the target number of bytes.

7. The method of claim 5, further comprising, prior to the performing, by the DMA controller, a transfer operation on target data in the storage device:

transplanting the preset file system into the embedded controller;

and migrating the driver of the storage device into the embedded controller.

8. A file manipulation apparatus for use in an embedded controller electrically connected to a storage device, the embedded controller including a Direct Memory Access (DMA) controller, the apparatus comprising:

the operation module is used for executing data transmission operation on the storage device through the DMA controller;

the waiting module is used for waiting for the completion of the execution of the data transmission operation and starting suspensible abnormal interruption in the process of waiting for the completion of the execution of the data transmission operation; executing a target task by the interrupt service routine that can suspend the abort.

9. An embedded controller, comprising:

one or more processors;

a memory;

one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method of any of claims 1-7.

10. A computer-readable storage medium, characterized in that a program code is stored in the computer-readable storage medium, which program code can be called by a processor to perform the method according to any of claims 1-7.