CN109710548A - A kind of DMA control data transmission method, system and equipment - Google Patents
A kind of DMA control data transmission method, system and equipment Download PDFInfo
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Abstract
The present invention relates to a kind of DMA control data transmission method, system and equipment is related to, belong to data control technology field.The DMA controls data transmission method, comprising: reading and writing configuring request transmitted by PCIe terminal receiving host；PCIe terminal configures base register and command register；PCIe is addressed by base register；PCIe sends memory reading and writing operation requests to dma controller；Dma controller receives the memory reading and writing operation requests that PCIe is sent；Dma controller carries out corresponding reading and writing configuration；Dma controller executes DMA reading, DMA write process according to the configuration of host.The present invention utilizes dma controller connection PCIe module and Subscriber Interface Module SIM, the high-speed transfer task of mass data can be completed in the case where occupying less cpu resource, dma controller based on PCIe bus interface solves the problems, such as data communication rates bottleneck in the prior art, it is also applied in acquisition system, has great importance to the performance of the system of raising.
Description
Technical field
The invention belongs to data control technology fields, and in particular to a kind of DMA control data transmission method, system and set
It is standby.
Background technique
Information technology is in development by leaps and bounds, and the data scale for needing to transmit and handle increases in multiple, the height of bus performance
The low influence to present information equipment is increasing.Currently, common bus is pci bus, pci bus is a kind of parallel bus,
Its bus bandwidth range is only applicable to the basic interfaces such as 1.1 standards of sound card, 10/100M network interface card and USB.With the communication technology
Further development, I/O interface of new generation starts to occur, including gigabit, 10,000,000,000 ethernet technology and the FC skill of 4G/8G
Art, pci bus bandwidth have been unable to meet the high bandwidth concurrent reading and concurrent writing requirement of inside computer system, and bottle occur in data communication rates
Neck.
PCI Express is a kind of widely used computer extended serial bus standard, high with data transfer bandwidth,
Speed is fast, configures flexible advantage.The high data rate that its use in computer architecture can satisfy computer system passes
Defeated requirement, it has also become the important way that processor is interacted with peripheral hardware.
But in the data transmission system of PCIe bus interface, it usually needs cpu peripheral carries out data transmission, consumption
Time is long, transmission rate is slow.
Summary of the invention
In order to solve the problems, such as that data communication time of the existing technology is long, rate is slow, the present invention provides a kind of DMA
Data transmission method, system and equipment are controlled, it is fast with data transfer bandwidth height, speed, configure the features such as flexible.
Technical solution provided by the invention is as follows:
On the one hand, a kind of DMA controls data transmission method, which comprises
Reading and writing configuring request transmitted by PCIe terminal receiving host；
PCIe terminal configures base register and command register；
PCIe is addressed by base register；
PCIe sends memory reading and writing operation requests to dma controller；
Dma controller receives the memory reading and writing operation requests that the PCIe is sent；
Dma controller carries out corresponding reading and writing configuration；
Dma controller executes DMA reading, DMA write process according to the configuration of host.
Still optionally further, the dma controller executes DMA reading, DMA write process according to the configuration of host, comprising:
Memory, which is sent, to host reads TLP；
The Cp1D for waiting host to return；
Data in the CplD received are extracted, memory is stored in.
Still optionally further, the dma controller executes DMA reading and writing process according to the configuration of host, comprising:
Target data is read out from memory, load memory writes TLP, is sent by PCIe bus to host.
On the one hand, a kind of DMA controls data transmission system, comprising: dma controller, PCIe terminal, memory, host
Root complex；
The dma controller is connected by transaction interface and configuration interface with the IP kernel of the PCIe terminal, to use
PCIe bus carries out data transmission；
Pass through the PCIe link of a single pass double simplex modes between the PCIe terminal and root complex, i.e., it is a pair of
Differential signal is sent to be connected with a pair of reception differential signal；
Connection signal between the dma controller and the memory includes address wire, Data In-Line, data output
Line, write enable signal.
Still optionally further, the dma controller include: PCIe interface, receive engine Rx, send engine Tx and control/
Status register.
Still optionally further, the working condition for receiving engine Rx includes: reset state, receives Memory read request shape
State, wait Memory read request be disposed state, receive Memory write request state, wait Memory write request be disposed
State receives Cpl state and receives CplD state.
Still optionally further, the working condition for sending engine Tx includes: reset state, sends CplD state, sends
Memory write request state and transmission read request state.
Still optionally further, the memory includes: address generating module and single port memory in one's power.
Still optionally further, the interface input/output signal of the PCIe terminal includes: system interface, PCI Express
Interface, configuration interface and transaction interface.
Another aspect, a kind of DMA control data transmission set characterized by comprising processor, and with the place
The memory that reason device is connected；
For storing computer program, the computer program is at least used to execute described in any of the above-described the memory
DMA control data transmission method；
The processor is for calling and executing the computer program in the memory.
The invention has the benefit that connect PCIe module and Subscriber Interface Module SIM using dma controller, can occupy compared with
The high-speed transfer task of mass data is completed in the case where few cpu resource, the dma controller based on PCIe bus interface solves
It in the prior art the problem of data communication rates bottleneck, is also applied in acquisition system, has to the performance of the system of raising
Important meaning.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the flow diagram that a kind of DMA provided by the invention controls one embodiment of data transmission method.
Fig. 2 is that a kind of DMA provided by the invention controls simple dma controller embodiment composition signal in data transmission method
Figure.
Fig. 3 is the typical system topology schematic diagram of PCIe bus provided by the invention.
Fig. 4 is PCIe bus protocol hierarchical diagram provided by the invention.
Fig. 5 is that a kind of DMA provided by the invention controls data transmission system example structure schematic diagram.
Fig. 6 provides PCIe interface operation principle schematic diagram in embodiment for the present invention.
Fig. 7 is shared transaction interface provided by the invention and the signal waveforms for sending transaction interface.
Fig. 8 is shared transaction interface provided by the invention and the signal waveforms for receiving transaction interface.
Fig. 9 provides the basic structure and working principle of dma controller in an embodiment for the present invention.
Figure 10 is Rx status diagram provided by the invention.
Figure 11 is Tx status diagram provided by the invention.
Figure 12 provides schematic illustration in an embodiment for the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, technical solution of the present invention will be carried out below
Detailed description.Obviously, described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art are obtained all without making creative work
Other embodiment belongs to the range that the present invention is protected.
In order to clearly illustrate that the process and advantage of the present embodiment inventive method, the present invention provide a kind of DMA control
The method of data transmission method, the embodiment of the present invention includes:
Reading and writing configuring request transmitted by PCIe terminal receiving host；
PCIe terminal configures base register and command register；
PCIe is addressed by base register；
PCIe sends memory reading and writing operation requests to dma controller；
Dma controller receives the memory reading and writing operation requests that the PCIe is sent；
Dma controller carries out corresponding reading and writing configuration；
Dma controller executes DMA reading, DMA write process according to the configuration of host.
A kind of DMA provided in an embodiment of the present invention controls data transmission method, using dma controller connection PCIe module and
Subscriber Interface Module SIM can complete the high-speed transfer task of mass data in the case where occupying less cpu resource, total based on PCIe
The dma controller of line interface solves the problems, such as data communication rates bottleneck in the prior art, is also applied to acquisition system
In, have great importance to the performance of the system of raising.
Based on a kind of above-mentioned DMA control data transmission method, the embodiment of the present invention provides an alternative embodiment:
Fig. 1 is the flow diagram that a kind of DMA provided by the invention controls one embodiment of data transmission method, referring to
The DMA control data method of Fig. 1, the present embodiment may comprise steps of:
Reading and writing configuring request transmitted by s101, PCIe terminal receiving host.
In order to meet requirement of the people to information transmission quality, the especially biography of the video image of high-resolution, high frame per second
Defeated demand, the data scale that need to be transmitted and handle increase in multiple, and the data transfer rate of information is greatly improved, and present information equipment is to band
Wide requirement is gradually upgrading, while also to bus performance, more stringent requirements are proposed.Pci bus is a kind of parallel bus,
Bus bandwidth range is only applicable to the basic interfaces such as 1.1 standards of sound card, 10/100M network interface card and USB.With the communication technology into
The development of one step, I/O interface of new generation starts to occur, including gigabit, 10,000,000,000 ethernet technology and the FC technology of 4G/8G,
Pci bus bandwidth has been unable to meet the high bandwidth concurrent reading and concurrent writing requirement of inside computer system, selects in the embodiment of the present invention
PCIe bus.PCI-Express (peripheral component interconnect express) is a kind of high speed serialization
Computer expansion bus standard, its original entitled " 3GIO ".PCI Express is a kind of widely used computer extension
Serial bus standard has data transfer bandwidth height, speed fast, configures flexible advantage.Its use in computer architecture
It can satisfy the high speed data transfers requirement of computer system, it has also become the important way that processor is interacted with peripheral hardware.
Fig. 2 is that a kind of DMA provided by the invention controls simple dma controller embodiment composition signal in data transmission method
Figure.Referring to fig. 2, simple dma controller is actually the interface electricity used between the peripheral equipment of dma mode and system bus
Road, this interface circuit are to add DMA mechanism composition again on the basis of interrupt interface.Traditionally by the interface circuit of dma mode
Referred to as dma controller.
In dma controller, including memory-address counter: for storing the address for the data to be exchanged in memory.?
Before DMA transmission, the initial position (first address) of data in memory must be sent to memory-address counter by program.And work as
When DMA is transmitted, data of every exchange, by address counter plus " 1 ", to provide to be exchanged in memory one with incremental mode
The address of batch data.
Word counter: for recording the length (how many number of words) of transmission data block.Its content is also before the data transmission
Preset by program, the number of words of exchange is usually indicated with complement form.In DMA transmission, as soon as every transmission word, word counter add
"1".When counter overflow, that is, highest order generates carry, indicate that the transmission of this batch data finishes, then cause dma controller to
CPU issues interrupt signal.
Data buffer register: for the temporary data (word) transmitted every time.When input, by equipment (such as disk)
It is sent to data buffer register, then memory is sent to by data/address bus by buffer register.Conversely, being passed through when output by memory
Data/address bus is sent to data buffer register, is then then sent through equipment.
" DMA request " mark: a control signal is provided after equipment gets out one data word, makes " DMA request "
Indicate set.Backward " control/state " logic of the flag set issues DMA request, and the latter issues the bus right to use to CPU again
Request (HOLD), CPU respond this request after send back to response signal HLDA, " control/state " logic issues after receiving this signal
DMA response signal makes " DMA request " Flag Reset, is ready to exchange next word.
" control N/ state " logic: it is made of control and sequence circuit and Status Flag etc., by modifying based on memory address
Number device and word counter are specified transmission type (input or output), and are assisted to " DMA request " signal and CPU response signal
It reconciles and synchronizes.
Interrupt mechanism: when word counter overflows (full 0), it is meant that one group of data exchange finishes, and is triggered by spill over
Interrupt mechanism proposes to interrupt report to CPU.
Fig. 3 is the typical system topology schematic diagram of PCIe bus provided by the invention.
As shown in figure 3, by a root complex (Root Complex, abbreviation RC), alteration switch (Switch) and several
A endpoint device (PCIe Endpoint) is constituted.System is tree structure, and RC is similar to the root of tree, by central processing unit (CPU)
It is mounted to PCIe bus with main memory, represents that CPU and the other components in whole system communicate and data are transmitted, CPU
The other equipment in main memory and PCIe system are accessed by RC.PCIe Endpoint is exactly PCIe terminal device, such as
PCIe SSD, PCIe network interface card etc., and Legacy Endpoint, interface are PCIe, but internal behavior but with it is traditional
PCI or PCI-X the same (for example supporting three kinds of input/output space, memory, configuration affairs, support INTx and MSI interrupt).These
Terminal device can be connected directly between on RC, can also be connected in PCIe bus by alteration switch.Alteration switch is for expanding
Link is opened up, provides the port to connect for more terminal devices.Port on alteration switch close to RC is known as upstream port
(Upstream Port), and other ports branched away, referred to as downstream port (Downstream Port).One alteration switch
Only one upstream port can expand several downstream ports, and downstream port can be directly connected to terminal device, can also be with
Another alteration switch is connected, more PCIe ports are expanded.Bridging device (Bridge) be used to realize PCI or PCI-X with
Switching between PCIe bus, to make its compatibility in same bus system.
Compared with using the pci bus of the shared communication mode of bus, PCIe bus uses point-to-point (Endpoint to
Endpoint communication mode), each equipment exclusively enjoy bandwidth chahnel, and the speed and efficiency of data transmission are all better than PCI.
Fig. 4 is PCIe bus protocol hierarchical diagram provided by the invention.
Most of bus or interface are realized using layering.PCIe is no exception, its hierarchical structure is such as
Shown in Fig. 4.PCIe protocol defines following three layers: transaction layer (Transaction Layer), data link layer (Data Link
Layer) and physical layer (Physical Layer), there is different functions every layer, and lower layer is for top service.Layering is set
The benefit of meter is, when interface edition upgrading, hardware design only needs to change a certain layer therein, and other levels can be kept not
Become.The data of PCIe transmission are all to be transmitted in the form of packet, each packet is the lattice for having it to fix from top to bottom
Formula.
The major function of transaction layer is to generate (transmission) and parsing (reception) transaction layer data packet (Transaction
Layer packet, abbreviation TLP), while being responsible for flow control, QoS, transaction orderings etc. in data transmission procedure.
Data link layer is mainly responsible for generation (transmission) and parsing (reception) data link layer packets (Data Link
Layer packet, abbreviation DLLP), link layer EDC error detection and correction is carried out by CRC check and Ack/Nak agreement, is upper layer TLP
Transmission establish a reliable PCIe link.Additionally participate in the items such as flow control, power management.
The major responsibility of physical layer is the physical transfer of each layer data packet, can be further divided into logical sub-layer and electrical sub layer.It patrols
It collects sublayer to be connected with data link layer, electrical sub layer is the circuit interface of PCIe link.The transmitting terminal of physical layer will pass through 8/
It is transmitted (Stripe) in data distribution to each channel after 10 or 128/130 coding, receiving end is on each channel
Data decode and take together (De-stripe).In addition, physical layer is responsible for scrambling (Scramble) on each channel and be gone
Disturb (De-scramble), it is therefore an objective to make in transmission process 0 and 1 to be evenly distributed, remove the electromagnetic interference (EMI) of channel.
Since application layer needs to be docked with transaction layer at work and data exchange, in the design for carrying out application layer
When, we need to only pay close attention to the specification of PCIe bus transaction layer.The data link layer and physical layer of its bottom can temporarily be ignored.Under
The classification of the TLP specified in the transaction layer protocol and format are simply introduced.
Between host and PCIe device or between PCIe device and PCIe device, data transmission is all with data packet
What form carried out.Transaction layer requests the type of (Request), destination address and other according to upper layer (software layer or application layer)
These requests are packaged, generate Transaction Layer Packet, that is, TLP by association attributes.Then these TLP to
Lower experience data link layer and physical layer, eventually arrive at target device.
According to the difference request of software layer, transaction layer generates four kinds of different TLP and requests: Memory, IO,
Configuration,Message.First three is respectively used to access memory space, I/O space and configuration space, these three requests
It is just had existed in PCI PCI-X bus, and last Message request is the content increased newly in PCIe bus.?
It is all to pass through sideband signals as relevant informations such as interruption, mistake and power managements in PCI PCI-X bus
(Sideband signal) is transmitted, but PCIe bus eliminates these sideband lines, and all communications are all tape transports
Interior signal is transmitted by Packet, therefore, past some data transmitted by sideband lines, such as interrupting information, mistake
Information etc. just transfers to Message to transmit now.
(Configuration) and I/O access are configured, no matter reading and writing all is Non-posted, and such request is necessary
Obtain the response of equipment；Message TLP is Posted；Memory reads (Memory Read) request and equipment is needed to respond and return
Return data, it is therefore necessary to be Non-posted.And it is Posted that memory, which writes (Memory Write), data, which are sent, to be not necessarily to
It is responded, such host or equipment can not wait other side to reply, and directly send next data packet, certain in this way
The performance of write operation is improved in degree.If not obtaining the response of other side, sender just has no idea to know data actually
Either with or without being successfully written, there are the risks of loss of data.Although this risk has (probability very little), data link layer is provided
ACK/NAK mechanism, can guarantee that TLP is correctly interacted to a certain extent, therefore can largely subtract small write failure
It may.
Configuration (Configuration) request has Type 0 and 1 two kinds of Type.This is because PCIe device is in addition to terminal
Except equipment (Endpoint), there are also alteration switch (Switch), therefore need to be configured when configuring to equipment and be asked with Type 0
It asks and terminal device is configured, alteration switch is configured with Type 1.
Request for Non-Posted is centainly other side to be needed to respond, and other side is by returning to a completion
(Completion) TLP is in response.To read request, respondent is this by data needed for completing TLP return requestor
Completing TLP includes valid data, is called Completion with data, referred to as CplD；To configuration write request
For (Configuration Write) such request, respondent tells requestor to execute state by completing TLP, in this way
Completion TLP be free of valid data, be called Completion, referred to as Cpl.
In a kind of DMA control data transmission method provided by the invention, firstly, transmitted by PCIe terminal receiving host
Reading and writing configuring request.Specifically, in DMA write or read procedure, host first pass through terminal send Type 0 look after a patient by staying with him in hospital reading and writing operation
Request.
S102, PCIe terminal configure base register and command register.
Specifically, during DMA is read with DMA write, PCIe terminal matches base register and command register
It sets.
S103, PCIe are addressed by base register.
Specifically, during DMA is read with DMA write, PCIe is addressed by above-mentioned base register.
S104, PCIe send memory reading and writing operation requests to dma controller.
Specifically, during DMA is read with DMA write, PCIe sends memory reading and writing operation requests to dma controller.
S105, dma controller receive the memory reading and writing operation requests that PCIe is sent.
Specifically, during DMA is read with DMA write, dma controller receives the memory reading and writing that PCIe is sent
Operation requests.
S106, dma controller carry out corresponding reading and writing configuration.
Specifically, during DMA is read with DMA write, dma controller carries out corresponding reading and writing configuration.In DMA write mistake
Cheng Zhong carries out configuration corresponding with DMA write to the control inside dma controller/status register.It is right in DMA read procedure
Control/status register inside dma controller carries out configuration corresponding with DMA reading.
S107, dma controller execute DMA reading, DMA write process according to the configuration of host.
Specifically, during DMA is read with DMA write, dma controller executes DMA reading, DMA write according to the configuration of host
Process.During DMA write, dma controller executes DMA write process according to the configuration of host, and the data that host is required are from depositing
It is read out in reservoir, load memory writes TLP, thinks that host is sent by PCIe bus.During DMA is read, dma controller
DMA read procedure is executed according to the configuration of host, memory is sent to host and reads TLP, the CplD for waiting host to return will be received
CplD in data extract, be stored in memory.
The embodiment of the present invention can occupy less CPU money using dma controller connection PCIe module and Subscriber Interface Module SIM
The high-speed transfer task of mass data is completed in the case where source, the dma controller based on PCIe bus interface solves existing skill
It in art the problem of data communication rates bottleneck, is also applied in acquisition system, has to the performance of the system of raising important
Meaning.
Technical solution in order to further illustrate the present invention, the present invention also provides a kind of DMA control data transmission system is real
Apply example.
Fig. 5 is that a kind of DMA provided by the invention controls data transmission system example structure schematic diagram.
Referring to Fig. 5, the DMA control data transmission system of the present embodiment includes: dma controller 41, PCIe terminal 42, storage
The root complex 44 of device 43, host.
Specifically, dma controller 41 is connected by transaction interface and configuration interface with the IP kernel of PCIe terminal 42, to make
Carried out data transmission with PCIe bus.
Direct Memory Access (direct memory access (DMA)).This refers to a kind of data transfer operation of high speed, permits
Perhaps the direct read/write data between external equipment and memory do not need CPU intervention neither by CPU yet.Entire data transmission
It is carried out under the control that operation is known as " dma controller " at one.CPU at the beginning and end of data are transmitted in addition to doing at a bit
Reason is outer, and CPU can carry out other work in transmission process.In this way, CPU and input and output are all located in the most of the time
In parallel work-flow.Therefore, the efficiency of entire computer system is greatly improved.
In the present embodiment, dma controller passes through transaction interface (TRN) and configuration interface (CFG) and PCIe terminal IP kernel
It is connected, to be carried out data transmission using PCIe bus.
Pass through the PCIe link of a single pass double simplex modes between PCIe terminal 42 and root complex 44, i.e., it is a pair of
Differential signal is sent to be connected with a pair of reception differential signal；
Connection signal between dma controller 41 and memory 43 include address wire, Data In-Line, DOL Data Output Line,
Write enable signal.
Specifically, the PCIe interface in the present embodiment uses the Endpoint Block Plus for of Xilinx company
PCI Express core generates the rtl description file of the module by the CORE Generator tool in ISE software.It generates
The parameters of IP kernel include: that reference clock frequency is set as 100MHz, and port number is set as 1, and interface frequency is default value
62.5MHz；Vendor id is 0x10EE, device id 0x0007；Base register BAR 0, BAR 2 and extension read-only memory
BAR is set as available, and wherein BAR 0 is mapped as 64 bit memories, and BAR 2 is mapped as 32 bit memories, and address space size is equal
For 2 kilobytes, the address space size for extending read-only memory BAR is 1 Mbytes；Payload capacity is set as 512 bytes etc..
Fig. 6 provides PCIe interface operation principle schematic diagram in embodiment for the present invention.Referring to Fig. 6, PCIe interface module work
It is as shown in Figure 6 to make principle.All input/output signals of the module can be divided into four group interfaces, respectively system interface (SYS),
PCI Express interface (PCI_EXP), configuration interface (CFG) and transaction interface (TRN).
When system interface (SYS) includes systematic reset signal sys_reset_n, clock signal of system sys_clk and reference
Clock output signal refclkout.
PCI Express interface (PCI_EXP) by the transmitting-receiving Difference signal pair of multiple channel organizations by being formed.In the design
The PCIe core in a channel is used, therefore the interface only sends positive signal pci_exp_txp0, PCIe by PCIe and sends negative letter
Number pci_exp_txn0, PCIe receive positive signal pci_exp_rxp0 and PCIe and receive negative signal pci_exp_rxn0 composition.
PCI_EXP interface is connected to host, the data sent by serial received Difference signal pair receiving host, by serially sending difference
Sub-signal opposite direction host transmits data.
Configuration interface (CFG) is connect with the configuration interface of dma controller, is used to check that PCIe terminal is matched for dma controller
State between emptying.The interface includes that configuration data exports cfg_do, configuration read-write finishes cfg_rd_wr_done_n, configuration
The address DWORD cfg_dwaddr, configuration read enabled cfg_rd_en_n, the signals such as cfg_interrupt_n are interrupted in configuration.For
For dma controller, the configuration space of PCIe core be it is read-only, configuration can only pass through host initiate configuration write operation carry out
Modification.
Transaction interface (TRN) is connect with the transaction interface of dma controller, is provided generation for dma controller and is used TLP
Mechanism, be divided into shared transaction interface signal, send transaction interface signal and receive transaction interface signal.Share TRN interface packet
Include affairs clock trn_clk, affairs reset trn_reset_n and affairs uplink trn_lnk_up_n.Send TRN interface packet
Transmission frame is included to start trn_tsof_n, send frame end trn_teof_n, send data trn_td, send data redundancy trn_
The ready trn_tsrc_rdy_n of trem_n, transmission source, the ready trn_tdst_rdy_n of target, transmission source suspension trn_ are sent
Tsrc_dsc_n and transmission buffer can use trn_tbuf_av.Receiving TRN interface includes that receiving frame starts trn_rsof_n, connects
Frame end trn_reof_n is received, data trn_rd is received, receives data redundancy trn_rrem_n, receives mistake transmission trn_
Rerrfwd_n, the ready trn_rsrc_rdy_n in reception source, receive the ready trn_rdst_rdy_n of target, allow to receive it is non-
The signals such as Posted packet trn_rnp_ok_n.
Fig. 7 is shared transaction interface provided by the invention and the signal waveforms for sending transaction interface.It can from Fig. 7
Out, occur on trn_td signal wire a header length be 3DW, the TLP that data length is 1DW, trn_tsof_n signal is low
Level flag the beginning of this TLP, trn_teof_n signal low level indicate that it terminates.Trn_trem_n value is 0, is indicated
There is bag data on all 64 signal wires of trn_td.Trn_tsrc_rdy_n signal designation dma controller is just in trn_td
Upper submission valid data, period trn_tsrc_rdy_n and trn_tdst_rdy_n are set to effectively simultaneously, and expression successfully passes
Defeated two data beats.
Fig. 8 is shared transaction interface provided by the invention and the signal waveforms for receiving transaction interface.It is seen that
Occur the TLP that multiple header lengths are 3DW, data length is 1DW, trn_rsof_n signal low level on trn_rd signal wire
Indicate the beginning of this TLP, trn_reof_n signal low level indicates that it terminates.Trn_rrem_n value is 0, indicates trn_
There is bag data on all 64 signal wires of rd.Trn_rsrc_rdy_n signal designation IP kernel is controlled just on trn_td to DMA
Device processed submits valid data, and period trn_rsrc_rdy_n and trn_rdst_rdy_n are set to effectively simultaneously, and expression has succeeded
Two data beats are transmitted, trn_rdst_rdy_n is set in vain later, is indicated that dma controller is being handled at this time and is worked as forward pass
Defeated successful data, it is unripe to receive data new on trn_rd.Trn_rnp_ok_n is effective, indicates that dma controller prepares
Non- Posted request data package is received well.Trn_rcpl_streaming_n is effective, indicates to enable without controlling function
Line storage reads transmission.Current BAR, the current value 0x7B for receiving affairs and finding of the value instruction of trn_rbar_hit_n, indicates
That find is BAR 2.Remaining four signals trn_rfc_ph_av, trn_rfc_pd_av, trn_rfc_nph_av, trn_rfc_
Npd_av is used for flow control.
Fig. 9 provides the basic structure and working principle of dma controller in an embodiment for the present invention.It is controlled referring to Fig. 9, DMA
Device processed is made of PCIe interface, reception engine Rx, transmission engine Tx and control/status register.
Engine Rx is received to be responsible for judging type of data packet from received data packet on trn_rd signal wire and making corresponding place
Reason.Rx has following several working conditions: reset state receives Memory read request state, Memory read request is waited to handle
Finish state, receive Memory write request state, wait Memory write request be disposed state, receive Cpl state, receive CplD
State etc..
Figure 10 is Rx status diagram provided by the invention.It is connect when Rx is in reset state if detecting referring to Figure 10
Frame start signal trn_rsof_n is received, source ready signal trn_rsrc_rdy_n is received, receives target ready signal trn_rdst_
Rdy_n is effectively, to illustrate first QWORD for occurring TLP on trn_rd signal wire at this time.Rx according to trn_rd [62:
56] judge the type of the TLP, and enter the reception state of respective type TLP in next clock.When Rx is in reception state
When, if detecting, receiving frame end signal trn_reof_n, reception source ready signal trn_rsrc_rdy_n, reception target are ready
Signal trn_rdst_rdy_n is effectively, then to issue and indicate to Tx, make its respond request, and enter in next clock simultaneously
The state to be processed finished.When Tx completes response, Rx returns to reset state, and waiting receives TLP next time.
The type that engine Tx is responsible for the data packet sent as needed is sent, is corresponding flag bit on trn_td signal wire
Assignment issues data packet.Tx has following several working conditions: reset state sends CplD state, sends memory write request shape
State, transmission read request state etc..Figure 11 is Tx status diagram provided by the invention.Referring to Figure 11, each work shape
Conversion between state is as shown in figure 11.When Tx is in reset state, if detect complete packet request signal req_compl_q,
Transmission source ready signal trn_tdst_rdy_n is effective, and completes packet and sent signal compl_done_o and sent target
Termination signal trn_tdst_dsc_n is in vain, then first QWORD of CplD to be sent on trn_td signal wire, and under
One clock, which enters, sends CplD state, sends the other content comprising address and valid data, will complete to wrap after being sent completely
Signal compl_done_o has been sent to be set to effectively.Similarly, memory writes commencing signal mwr_start_i and memory reading is opened
Beginning signal mrd_start_i controls Tx respectively and enters transmission memory write request state and send read request state.
Control/status register is for controlling the work that Rx and Tx are received and transmitted, and display DMA work shape
State, including following register: device control register 1 (DCR1), writes DMA address register at device control register 2 (DCR2)
(WDMATLPA), DMA sized registers (WDMATLPS) are write, DMA counter register (WDMATLPC) is write, writes DMA data deposit
Device (WDMATLPP), reading DMA address register (RDMATLPA), reading DMA sized registers (RDMATLPS), reading DMA counting are posted
Storage (RDMATLPC), reading DMA data register (RDMATLPP) etc..0 bit of the Byte 0 of DCR1 is used for initial reset,
Therefore, 0x00000001 first is written to DCR1, then 0x00000000 is written, the read-write capability of dma controller can be enabled.DCR2
Byte 00 bit for opening DMA write operation, 0 bit of Byte 1 for checking whether DMA write operation is completed,
0 bit of Byte 2 is for opening DMA read operation, and 0 bit of Byte 3 is for checking whether DMA read operation is completed.Other
Register is used to deposit the relevant informations such as host specified operation address, data length, data counts, to instruct DMA control
The operation of device.
In the present embodiment, when host initiates DMA write or DMA read request, dma controller deposits address according to host
The configuration of device, length register, counter register and data register is written corresponding from reading in memory or into memory
Data.
Figure 12 provides schematic illustration in an embodiment for the present invention.Referring to Figure 12, the design of memory portion is divided into two
A module --- address generating module and single port random access memory (RAM).
Address generating module input signal is initial address Addr_in and data length Len_in, the two signals generate
From control/status register of dma controller.During dma controller executes DMA write, the value of register WDMATLPP
As the initial address for reading data from memory, the value of register WDMATLPS is as the number for needing to read from memory
According to number.Address generating module gradually adds up on the basis of initial address, generates actual address ram input signal, until
Accumulated value reaches the data amount check of requirement, so that all data that host requires are read and be sent.It is held in dma controller
In row DMA read procedure, the value of register RDMATLPP is as the initial address to memory write-in data, register RDMATLPS
Value as the data amount check that is written to memory of needs.Similar with DMA is write, address generating module is on the basis of initial address
It gradually adds up and generates address, until all data for sending host are stored in RAM according to appropriate address.
The address input signal Addr of RAM is the output address of address generating module.Data input signal Data_in comes
From the part Rx of dma controller, during carrying out reading DMA, Rx receives the CplD of host transmission, and data are sent to RAM
The port Data_i.Write enable signal Write_En is generated by Rx, have been prepared for being written on Data_in signal wire data,
When having had been prepared for appropriate address on Addr signal wire, it is set to effectively, data is stored in RAM.Data output signal Data_out
It is always the data of address input signal Addr meaning.
The embodiment of the present invention can occupy less CPU money using dma controller connection PCIe module and Subscriber Interface Module SIM
The high-speed transfer task of mass data is completed in the case where source, the dma controller based on PCIe bus interface solves existing skill
It in art the problem of data communication rates bottleneck, is also applied in acquisition system, has to the performance of the system of raising important
Meaning.
The present invention also provides a kind of embodiment of DMA control data transmission set, the DMA control data of the present embodiment are passed
Transfer device, comprising: processor, and the memory being connected with processor.
Specifically, for memory for storing computer program, computer program is at least used to execute an any of the above-described DMA
Control data transmission method.
Processor is for calling and executing the computer program in memory.
The embodiment of the present invention can occupy less CPU money using dma controller connection PCIe module and Subscriber Interface Module SIM
The high-speed transfer task of mass data is completed in the case where source, the dma controller based on PCIe bus interface solves existing skill
It in art the problem of data communication rates bottleneck, is also applied in acquisition system, has to the performance of the system of raising important
Meaning.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
It is understood that same or similar part can mutually refer in the various embodiments described above, in some embodiments
Unspecified content may refer to the same or similar content in other embodiments.
It should be noted that in the description of the present invention, term " first ", " second " etc. are used for description purposes only, without
It can be interpreted as indication or suggestion relative importance.In addition, in the description of the present invention, unless otherwise indicated, the meaning of " multiple "
Refer at least two.
Any process described otherwise above or method description are construed as in flow chart or herein, and expression includes
It is one or more for realizing specific logical function or process the step of executable instruction code module, segment or portion
Point, and the range of the preferred embodiment of the present invention includes other realization, wherein can not press shown or discussed suitable
Sequence, including according to related function by it is basic simultaneously in the way of or in the opposite order, Lai Zhihang function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
It should be appreciated that each section of the invention can be realized with hardware, software, firmware or their combination.Above-mentioned
In embodiment, software that multiple steps or method can be executed in memory and by suitable instruction execution system with storage
Or firmware is realized.It, and in another embodiment, can be under well known in the art for example, if realized with hardware
Any one of column technology or their combination are realized: having a logic gates for realizing logic function to data-signal
Discrete logic, with suitable combinational logic gate circuit specific integrated circuit, programmable gate array (PGA), scene
Programmable gate array (FPGA) etc..
Those skilled in the art are understood that realize all or part of step that above-described embodiment method carries
It suddenly is that relevant hardware can be instructed to complete by program, the program can store in a kind of computer-readable storage medium
In matter, which when being executed, includes the steps that one or a combination set of embodiment of the method.
It, can also be in addition, each functional unit in each embodiment of the present invention can integrate in a processing module
It is that each unit physically exists alone, can also be integrated in two or more units in a module.Above-mentioned integrated mould
Block both can take the form of hardware realization, can also be realized in the form of software function module.The integrated module is such as
Fruit is realized and when sold or used as an independent product in the form of software function module, also can store in a computer
In read/write memory medium.
Storage medium mentioned above can be read-only memory, disk or CD etc..
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiment or examples in can be combined in any suitable manner.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (10)
1. a kind of DMA controls data transmission method, which is characterized in that the described method includes:
Reading and writing configuring request transmitted by PCIe terminal receiving host；
PCIe terminal configures base register and command register；
PCIe is addressed by base register；
PCIe sends memory reading and writing operation requests to dma controller；
Dma controller receives the memory reading and writing operation requests that the PCIe is sent；
Dma controller carries out corresponding reading and writing configuration；
Dma controller executes DMA reading, DMA write process according to the configuration of host.
2. the method according to claim 1, wherein the dma controller executes DMA according to the configuration of host
It reads, DMA write process, comprising:
Memory, which is sent, to host reads TLP；
The Cp1D for waiting host to return；
Data in the CplD received are extracted, memory is stored in.
3. the method according to claim 1, wherein the dma controller executes DMA according to the configuration of host
Reading and writing process, comprising:
Target data is read out from memory, load memory writes TLP, is sent by PCIe bus to host.
4. a kind of DMA controls data transmission system characterized by comprising dma controller, PCIe terminal, memory, host
Root complex；
The dma controller is connected by transaction interface and configuration interface with the IP kernel of the PCIe terminal, to use PCIe
Bus carries out data transmission；
Pass through the PCIe link of a single pass double simplex modes between the PCIe terminal and root complex, i.e., it is a pair of to send
Differential signal receives differential signal with a pair and is connected；
Connection signal between the dma controller and the memory include address wire, Data In-Line, DOL Data Output Line,
Write enable signal.
5. system according to claim 4, which is characterized in that the dma controller includes: PCIe interface, receives engine
Rx, engine Tx and control/status register are sent.
6. system according to claim 5, which is characterized in that the working condition for receiving engine Rx includes: reset shape
State, receive Memory read request state, wait Memory read request be disposed state, receive Memory write request state, etc.
To Memory write request be disposed state, receive Cpl state and receive CplD state.
7. system according to claim 5, which is characterized in that the working condition for sending engine Tx includes: reset shape
State sends CplD state, sends memory write request state and sends read request state.
8. system according to claim 4, which is characterized in that the memory includes: address generating module and single port institute
And memory.
9. system according to claim 4, which is characterized in that the interface input/output signal of the PCIe terminal includes:
System interface, PCI Express interface, configuration interface and transaction interface.
10. a kind of DMA controls data transmission set characterized by comprising processor, and be connected with the processor
Memory；
The memory is at least used for perform claim and requires any one of 1-3 for storing computer program, the computer program
The DMA controls data transmission method；
The processor is for calling and executing the computer program in the memory.
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