CN111129130B - 一种沟槽栅igbt器件 - Google Patents
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Abstract
本发明提供的一种沟槽栅IGBT器件,该沟槽栅IGBT器件包括第一关断通路和第二关断通路,第一关断通路和第二关断通路均为IGBT关断过程中载流子抽取的通道,相对于现有技术新增了一条额外的关断通路,新增的关断通路和原关断通路同时工作能够加快对漂移区的载流子的抽取,使载流子快速复合,提高了抗闩锁能力,缩短了关断时间,同时也增大了可关断电流。
Description
技术领域
本发明属于半导体领域,尤其涉及一种沟槽栅IGBT器件。
背景技术
现有技术中的IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)器件通常只有靠近发射极的一条关断通路(空穴通路),关断损耗大,通流能力差,漂移区的载流子复合时间长,因而现有IGBT器件可关断的电流相对较小,关断所需时间长。
发明内容
为解决现有技术中IGBT器件可关断电流小,关断时间长的技术问题,本发明提供一种沟槽栅IGBT器件,具体方案如下:
一种沟槽栅IGBT器件,包括第一关断通路和第二关断通路,所述第一关断通路位于栅极的侧部,所述第二关断通路位于栅极的底部。
进一步的,所述第二关断通路包括第二P区和第二P+区,所述第二P+区位于所述第二P区的上方,所述第二P+区至少部分地与发射极金属层接触。
进一步的,所述栅极的底部设置有栅极氧化层,所述第二P区的顶端与所述栅极氧化层的底端齐平。
进一步的,所述第一关断通路包括第一P区和第一P+区,所述第一P+区位于所述第一P区的上方,所述第一P+区至少部分地与发射极金属层接触。
进一步的,所述栅极的侧部设置有栅极氧化层,所述第一P区与所述栅极的侧部的栅极氧化层接触;
所述第一P区的上方设置N+区,所述N+区位于所述第一P+区与所述栅极的侧部的栅极氧化层之间,所述第一P+区不与栅极氧化层接触;
所述第一P区的底端高于所述栅极的底端,所述栅极的顶端高于所述N+区的底端,所述栅极的侧部的栅极氧化层的顶端高于所述N+区的底端。
进一步的,与所述栅极氧化层所在侧部相对的栅极的侧部和栅极的顶部设置有栅极隔离氧化层,所述栅极隔离氧化层至少部分地与N+区接触,所述栅极隔离氧化层至少部分地与第二P+区接触。
进一步的,所述第一P+区顶端低于N+区的顶端;或所述第二P+区的顶端低于栅极氧化层的底端。
进一步的,所述第一P区的底部设置有第一N区,或所述第二P区的底部和侧面设置有第二N区。
进一步的,所述栅极的底部依次设置有N-区、N’区、第三P+区和集电极金属层。
一种沟槽栅IGBT器件,将如上所述的沟槽栅IGBT器件的N型掺杂区替换为P型掺杂区,将如上所述的沟槽栅IGBT器件的P型掺杂区替换为N型掺杂区。
与现有技术相比,本发明的第一关断通路和第二关断通路均为IGBT关断过程中载流子抽取的通道,相对于现有技术新增了一条额外的关断通路,新增的关断通路和原关断通路同时工作能够加快对漂移区的载流子的抽取,使载流子快速复合,提高了抗闩锁能力,缩短了关断时间,同时也增大了可关断电流。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中:
图1为本发明实施例中的沟槽栅IGBT器件的区域结构示意图;
图2为本发明实施例中的沟槽栅IGBT器件内的电流走向示意图;
图3为本发明实施例中的在第一P区与漂移区之间设置N区的示意图;
图4为本发明实施例中的第一P+区与发射极金属层的接触面偏移示意图。
在附图中,相同的部件采用相同的附图标记,附图并未按实际比例绘制。
具体实施方式
下面将结合附图对本发明作进一步的说明。
本发明中的P、P+、N-、N、N’、N+,是对掺杂浓度的相对大小的表述,具体的浓度的相对大小为:
(P+)>P,该式中的括号仅为避免“+”与“>”混淆;
(N+)>N’>N>N-;该式中的括号仅为避免“+”与“>”混淆。
本发明中的P型掺杂区是指,在该区域的半导体材料(如硅、碳化硅等)中掺入三价元素(如硼、铟、镓等)。P型掺杂区包括P、P+,如果有,还包括P-等不同掺杂浓度的区域;
本发明中的N型掺杂区是指,在该区域的半导体材料(如硅、碳化硅等)中掺入五价元素(如磷、砷等),N型掺杂区包括N-、N、N’、N+,如果有,还包括其它不同掺杂浓度的区域。
如图1所示,本实施例提供一种沟槽栅IGBT器件,该IGBT器件的沟道类型为N沟道,该IGBT器件包括漂移区,所述漂移区为N-区101。在N-区101的顶部挖槽,刻蚀出槽形,并氧化形成栅极氧化层102,在栅极氧化层102背离漂移区即N-区101的一侧设置栅极103。栅极氧化层102为一个整体,栅极氧化层102布置在栅极103的侧部和底部,栅极氧化层102将栅极103的侧部和底部完全覆盖。本实施例中的栅极103由多晶硅制成。栅极103也可以采用其它材料,例如,碳化硅。
在栅极氧化层102背离栅极103的侧部和漂移区即N-区101的上方布置第一P区104,第一P区104与栅极103左侧的栅极氧化层102接触,第一P区104的底端高度高于栅极103的底端;在第一P区104的上方靠近栅极氧化层102的区域布置N+区105,栅极103的顶端高于N+区105的底端,栅极氧化层102位于栅极103左侧的部分的顶端高于N+区105的底端。这种高度设置使得第一P区104位于N+区105和漂移区即N-区101之间且朝向栅极103一侧的面能够与栅极氧化层102接触且与栅极103完全对应,这样,在向栅极施加电压时,第一P区104位于N+区105和漂移区即N-区101之间且朝向栅极103一侧的面能够被栅极电压完全覆盖,从而在第一P区104靠近栅极氧化层102的一侧形成完全导通N+区105和漂移区即N-区101的反型层,实现IGBT的导通。
在第一P区104的上方和N+区105远离栅极氧化层102的一侧设置第一P+区106,N+区105和第一P区104将第一P+区106与栅极氧化层102分隔开,第一P+区106与栅极氧化层102不接触。在栅极103的底部的栅极氧化层102的下方布置第二P区107,第二P区107的顶端与栅极氧化层102的底端齐平,在第二P区107的上方布置第二P+区108。栅极103的顶部和右侧部未覆盖栅极氧化层102,栅极隔离氧化层109覆盖在栅极103的顶部和右侧部。栅极103的顶部的栅极隔离氧化层109向N+区105延伸并部分覆盖N+区105;栅极103右侧部的栅极隔离氧化层109部分覆盖第二P+区108。栅极隔离氧化层109分别部分覆盖N+区105和第二P+区108能够获得较好的隔离效果。
在N-区101的下方设置有N’区110,N’区110为沟槽栅IGBT器件的缓冲区。在N’区110的下方还布置有第三P+区111,第三P+区111为集电区。发射极金属层112分别与N+区105、第一P+区106和第二P+区108接触。集电极金属层113位于第三P+区111的下方。第三P+区111、N’区110和N-区101依次接触。如图1所示发射极E位于上方,集电极C位于下方。
上述图1所示区域结构中,N-区101、第一P区104、第一P+区106和发射极金属层112依次接触,N-区101、第二P区107、第二P+区108和发射极金属层112依次接触,且N-区101、第一P区104和第二P区107均不与发射极金属层112接触,第一P区104和第一P+区106均不与第二P区107接触,第一P区104和第一P+区106均不与第二P+区108接触,第一P+区106和第二P+区108均不与N-区101接触。
如图1所示,第一关断通路主要由第一P区104和第一P+区106组成,第二关断通路主要由第二P区107和第二P+区108组成,第一关断通路位于栅极103的侧部,第二关断通路位于栅极103的底部。当向栅极103施加工作电压时,第一P区104朝向栅极103的一侧形成N沟道将N-区101和N+区105导通,电流由N-区101经第一P区104和N+区105流向发射极金属层112,如图2箭头所示路径132。当栅极103的工作电压去除后,N沟道瞬间关闭,由集电极端注入的载流子进入N-区101后将通过第一关断通道和第二关断通道迅速抽走。相对于现有技术,本实施例新增了一条额外的关断通路,新增的空穴通道和原空穴通道同时工作能够加快对漂移区的过剩载流子的抽取,使载流子快速复合提高了抗闩锁能力,缩短了关断时间,同时也增大了可关断电流。当栅极103的工作电压去除后,经第一关断通道和第二关断通道抽走的载流子形成两路电流,一路电流从N-区101经第一P区104和第一P+区106流向发射极金属112,如图2箭头所示路径130;另一路电流从N-区101经第二P区107和第二P+区108流向发射极金属112,如图2箭头所示路径131。因此,本实施例中的沟槽栅IGBT器件在栅极103去除工作电压后能够快速实现IGBT的关断。
本实施例的半导体材料为硅,在其它实施例中,也可以使用碳化硅或其它半导体材料。
如图1所示,本实施例中,第一P+区106与发射极金属层112的接触面相对于N+区105与发射极金属层112的接触面齐平,第二P+区108与发射极金属层112的接触面相对于第二P区107与栅极氧化层102的接触面齐平。
在其它实施例中,可以是第一P+区106与发射极金属层112的接触面相对于N+区105与发射极金属层112的接触面朝向第一P区104偏移,即,第一P+区106的顶端低于N+区105的顶端,如图4所示。或者第二P+区108与发射极金属层112的接触面相对于所述第二P区107与栅极氧化层102的接触面朝向第二P区107偏移,即,第二P+区108的顶端低于栅极氧化层102的底端。因第一P+区106和第二P+区108基本上属于硅体内的发射极一侧最末尾的加工工艺了,其掺杂深度主要靠离子注入控制,为了使第一P+区106注入的P型杂质不与N+区105的N型掺杂发生补偿,而降低有效的P型浓度,可以通过刻蚀掉部分硅材料,再注入P+,来达到效果。因此,该实施例中接触面的偏移,有利于沟槽栅IGBT器件的加工制作。
在其它实施例中,还可以在N-区101与第一P区104之间设置第一N区120,在第二P区107的侧面和底部设置第二N区130。第一N区120位于第一P区104的底部,第一N区120分别与N-区101、第一P区104以及栅极氧化层102接触,第一N区120将N-区101和第一P区104分隔开,N-区101与第一P区104不接触。第二N区130位于第二P区107的底部和侧面,第二N区130的侧面不超出栅极氧化层102的侧面边缘,第二N区130的顶端与栅极氧化层102的底端齐平,第二N区130在栅极氧化层102的底端的端面上的正投影均在该栅极氧化层102的底端的端面范围内,第二N区130位于N-区101与第二P区107之间将N-区101和第二P区107分隔开,如图3所示。第一N区120相当于空穴阻挡层,可以提高IGBT导通时的载流子注入水平,降低导通电阻,降低导通损耗。导通状态中第二P区107和N-区101的边界处会形成耗尽层,其中N-区101一侧的耗尽层减小了N-区101的有效导电面积,影响导通特性。设置第二N区130,可缩窄第二N区130和第二P区107的边界靠近第二N区130一侧的耗尽层宽度,削弱由于引入第二P区107对导通特性降低的影响。
在另外的实施例中,将上述各实施例的沟槽栅IGBT器件中的原有N型掺杂区替换为P型掺杂区,原有P型掺杂区替换为N型掺杂区。这将使原沟槽栅IGBT器件的沟道类型由N沟道转换为P沟道。该替换只涉及掺杂类型的改变,掺杂浓度相对大小不变,例如,P替换为N,P+替换为N+,N-替换为P-,N替换为P,N’替换为P’,N+替换为P+。
在上述各实施例及对应的附图中,仅示出本发明内容的最小功能单元。以各附图的结构最右侧边界往右做镜像,可得到新的符合本发明内容的最小功能单元。以各附图的结构最左侧边界往左做镜像,可得到上述右侧镜像操作相同的新的符合本发明内容的最小功能单元。因此本说明书中的“左”和“右”仅针对附图结构而言,如做镜像,则“左”和“右”的表述可互换,不限定本发明内容。
虽然已经参考优选实施例对本发明进行了描述,但在不脱离本发明的范围的情况下,可以对其进行各种改进并且可以对其中部分或者全部技术特征进行等同替换。尤其是,只要不存在逻辑或结构冲突,各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例,而是包括落入权利要求的范围内的所有技术方案。
Claims (8)
1.一种沟槽栅IGBT器件,其特征在于,包括第一关断通路和第二关断通路,所述第一关断通路位于栅极的侧部,所述第二关断通路位于栅极的底部;
所述第一关断通路包括第一P区和第一P+区,所述第一P+区位于所述第一P区的上方,所述第一P+区至少部分地与发射极金属层接触;
所述第二关断通路包括第二P区和第二P+区,所述第二P+区位于所述第二P区的上方,所述第二P+区至少部分地与发射极金属层接触。
2.根据权利要求1所述的沟槽栅IGBT器件,其特征在于,所述栅极的底部设置有栅极氧化层,所述第二P区的顶端与所述栅极氧化层的底端齐平。
3.根据权利要求1或2所述的沟槽栅IGBT器件,其特征在于,所述栅极的侧部设置有栅极氧化层,所述第一P区与所述栅极的侧部的栅极氧化层接触;
所述第一P区的上方设置N+区,所述N+区位于所述第一P+区与所述栅极的侧部的栅极氧化层之间,所述第一P+区不与栅极氧化层接触;
所述第一P区的底端高于所述栅极的底端,所述栅极的顶端高于所述N+区的底端,所述栅极的侧部的栅极氧化层的顶端高于所述N+区的底端。
4.根据权利要求3所述的沟槽栅IGBT器件,其特征在于,与所述栅极氧化层所在侧部相对的栅极的侧部和栅极的顶部设置有栅极隔离氧化层,所述栅极隔离氧化层至少部分地与N+区接触,所述栅极隔离氧化层至少部分地与第二P+区接触。
5.根据权利要求3所述的沟槽栅IGBT器件,其特征在于,所述第一P+区顶端低于N+区的顶端;或所述第二P+区的顶端低于栅极氧化层的底端。
6.根据权利要求3所述的沟槽栅IGBT器件,其特征在于,所述第一P区的底部设置有第一N区,或所述第二P区的底部和侧面设置有第二N区。
7.根据权利要求1或2所述的沟槽栅IGBT器件,其特征在于,所述栅极的底部依次设置有N-区、N’区、第三P+区和集电极金属层。
8.一种沟槽栅IGBT器件,其特征在于,将权利要求1-7中任一项所述的沟槽栅IGBT器件的N型掺杂区替换为P型掺杂区,将权利要求1-7中任一项所述的沟槽栅IGBT器件的P型掺杂区替换为N型掺杂区。
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