CN111129024A - Method for manufacturing flash memory device - Google Patents
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- CN111129024A CN111129024A CN201911373600.1A CN201911373600A CN111129024A CN 111129024 A CN111129024 A CN 111129024A CN 201911373600 A CN201911373600 A CN 201911373600A CN 111129024 A CN111129024 A CN 111129024A
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 107
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 19
- 239000006227 byproduct Substances 0.000 claims description 13
- 229920000642 polymer Polymers 0.000 claims description 12
- 239000012495 reaction gas Substances 0.000 claims description 8
- 239000000376 reactant Substances 0.000 claims description 7
- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- NTQGILPNLZZOJH-UHFFFAOYSA-N disilicon Chemical compound [Si]#[Si] NTQGILPNLZZOJH-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract
The application discloses a method for manufacturing a flash memory device, which comprises the following steps: providing a substrate, wherein a gate oxide layer, a floating gate polycrystalline silicon layer, an isolation layer and a control gate are sequentially formed on the substrate, a silicon nitride layer is formed at the top end of the control gate, side walls are formed on the peripheral sides of the silicon nitride layer and the control gate, each side wall comprises a silicon oxide layer, and the floating gate polycrystalline silicon layer between the side walls is covered with the silicon oxide layer; etching the silicon oxide layer by ICP etching equipment to expose the floating gate polysilicon layer between the side walls; and etching the floating gate polycrystalline silicon layer between the side walls by ICP etching equipment until the gate oxide layer between the side walls is exposed to form a floating gate. According to the method, the silicon oxide layer and the floating gate polycrystalline silicon layer of the flash memory device are etched through the ICP etching equipment, so that the complexity of the manufacturing process of the flash memory device is reduced.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a flash memory device.
Background
A Flash memory (Nand-Flash, hereinafter referred to as "Flash memory") is a memory using a Non-volatile memory (NVM) technology, and is currently widely applied to electronic products with a storage function, such as smart phones, tablet computers, digital cameras, Universal Serial Bus Flash disks (USB Flash disks, hereinafter referred to as "USB disks"). The flash memory is mainly characterized in that: the capacity is relatively large, the rewriting speed is high, the method is suitable for storing a large amount of data, and the data can be still stored after power failure, so that the method is widely applied.
The Gate of the flash memory device comprises a Floating Gate (FG) and a Control Gate (CG), and a Gate oxide layer is arranged between the Gate and the substrate. In the related art, in the manufacturing process of the flash memory device, after the control gate etching step is completed, oxide etching and floating gate etching need to be performed respectively. Because the etching rates of the oxide and the polysilicon forming the floating gate are different, and the thicknesses and the structures of the oxide and the polysilicon are different, the etching step of the oxide is carried out in a Capacitive Coupled Plasma (CCP) etching device with stronger bombardment capability, and the etching step of the floating gate is carried out in an Inductively Coupled Plasma (ICP) etching machine with weaker bombardment capability and smaller Plasma damage.
Fig. 1 to 3 are schematic diagrams illustrating etching of a silicon oxide layer 101 and a floating gate polysilicon layer 102 in a manufacturing process of a flash memory device provided in the related art. Referring to fig. 1, a substrate 110 is formed with a pattern formed during a manufacturing process, and a portion to be etched is shown by a dotted line; referring to fig. 2, the silicon oxide layer 101 is etched in the CCP etching apparatus to expose the floating gate polysilicon layer 102; referring to fig. 3, the floating gate polysilicon layer 102 is etched in an ICP etching apparatus to expose the gate oxide layer 103, forming a floating gate.
As can be seen from the above, the oxide etching and the floating gate etching need to be completed in different etching apparatuses, and in different apparatuses, the polymer (Dry Strip), the Wet cleaning (Wet Clean) and the corresponding measurement need to be removed at the end of each etching, so the process steps are complicated, and the manufacturing efficiency is low.
Disclosure of Invention
The application provides a manufacturing method of a flash memory device, which can solve the problems of complex process and low manufacturing efficiency caused by the fact that silicon oxide and a floating gate polycrystalline silicon layer need to be etched in different etching equipment in the manufacturing method of the flash memory device provided in the related technology.
In one aspect, an embodiment of the present application provides a method for manufacturing a flash memory device, including:
providing a substrate, wherein a gate oxide layer, a floating gate polycrystalline silicon layer, an isolation layer and a control gate are sequentially formed on the substrate, a silicon nitride layer is formed at the top end of the control gate, side walls are formed on the silicon nitride layer and the peripheral sides of the control gate, the side walls comprise silicon oxide layers, silicon nitride isolation layers are formed in the side walls, and the silicon oxide layers cover the floating gate polycrystalline silicon layer between the side walls;
etching the silicon oxide layer by ICP etching equipment to expose the floating gate polycrystalline silicon layer between the side walls, and adjusting reaction byproducts accumulated on the side walls by adjusting parameters in the etching process;
and etching the floating gate polycrystalline silicon layer between the side walls by the ICP etching equipment until the gate oxide layer between the side walls is exposed to form a floating gate, and adjusting parameters in the etching process to enable the etching rate of the polycrystalline silicon to be greater than the etching rate of silicon oxide.
Optionally, adjusting the reaction byproducts deposited on the sidewall by adjusting parameters in the etching process includes:
and adjusting the reaction by-products accumulated on the side wall by adjusting at least one of Bias Radio Frequency (Bias) power, Source power, reaction gas flow rate and gas pressure in the etching process.
Optionally, the bias power has a value in a range of 50 watts (W) to 100 watts:
optionally, the value of the source power ranges from 500 watts to 800 watts.
Optionally, the reactant gas flow rate ranges from 50 Standard milliliter per Minute (SCCM) to 100 SCCM.
Optionally, the reactant gas comprises carbon tetrafluoride (CF)4)。
Optionally, the gas pressure ranges from 5 mTorr (mTorr) to 15 mTorr.
Optionally, the adjusting the parameters in the etching process to make the rate of etching the polysilicon larger than the rate of etching the silicon oxide includes:
and adjusting at least one of bias power, source power, flow rate of reaction gas and gas pressure in the etching process to enable the etching rate of the polycrystalline silicon to be larger than the etching rate of the silicon oxide.
Optionally, the bias power has a value in a range of 50 w to 100 w
Optionally, the value of the source power ranges from 300 watts to 500 watts.
Optionally, the reaction gas includes hydrobromic acid (Hbr), helium (He), and oxygen (O)2)。
Optionally, the flow rate of the hydrobromic acid ranges from 100SCCM to 300 SCCM.
Optionally, the flow rate of the helium gas ranges from 100SCCM to 300 SCCM.
Optionally, the flow rate of the oxygen gas ranges from 5SCCM to 10 SCCM.
Optionally, the air pressure ranges from 20 mtorr to 50 mtorr.
Optionally, the reaction byproduct includes a Polymer (Polymer), and after the etching of the floating gate polysilicon layer between the control gates in the ICP etching apparatus, the method further includes:
etching to remove the polymer;
carrying out wet stripping on a Photoresist (PR) in the etching process;
and respectively measuring the width between the floating gates, the thickness of the etched floating gate polycrystalline silicon layer and the thickness of the residual silicon nitride layer.
Optionally, the isolation layer includes an Oxide Nitride Oxide (ONO) layer.
The technical scheme at least comprises the following advantages:
the silicon oxide layer of the flash memory device is etched through the ICP etching equipment, reaction byproducts accumulated on the side walls are adjusted through adjusting parameters in the etching process, the floating gate polycrystalline silicon layer between the side walls of the flash memory device is etched through the ICP etching equipment, and the rate of etching the polycrystalline silicon is larger than the rate of etching the silicon oxide through adjusting the parameters in the etching process, so that the silicon oxide layer and the floating gate polycrystalline silicon layer of the flash memory device are etched in the same etching equipment, the complexity of the manufacturing process of the flash memory device is reduced, and the manufacturing efficiency of the flash memory device is improved to a certain extent.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 to 3 are schematic views illustrating etching of a silicon oxide layer and a floating gate polysilicon layer in a manufacturing process of a flash memory device provided in the related art;
FIG. 4 is a flow chart of a method of fabricating a flash memory device provided by one exemplary embodiment of the present application;
FIGS. 5 and 6 are schematic diagrams of a manufacturing process of a flash memory device provided by an exemplary embodiment of the present application;
fig. 7 is a flowchart of a method for manufacturing a flash memory device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 4, which shows a flowchart of a method for manufacturing a flash memory device according to an exemplary embodiment of the present application, as shown in fig. 4, the method includes:
step S1, providing a substrate, on which a gate oxide layer, a floating gate polysilicon layer, an isolation layer and a control gate are sequentially formed, a silicon nitride layer is formed on the top end of the control gate, side walls are formed on the silicon nitride layer and the periphery of the control gate, the side walls include a silicon oxide layer, a silicon nitride isolation layer is formed in each side wall, and the floating gate polysilicon layer between the side walls is covered with the silicon oxide layer.
Referring to fig. 5, a cross-sectional view of a pattern formed during the fabrication of a flash memory device provided by an exemplary embodiment of the present application is shown. As shown in fig. 5, a gate oxide layer 510, a floating gate polysilicon layer 520, an isolation layer 501, and a control gate 530 are sequentially formed on a substrate 500. Silicon nitrogen is formed on top of control gate 530Side walls 503 are formed on the peripheral sides of oxide (SiN) layer 502, silicon nitride 502 and control gate 530, and side walls 503 comprise silicon oxide (e.g., SiO, disilicon)2) The layer 5031 is formed with silicon nitride spacers 5032 formed in the sidewalls 503, and the floating gate polysilicon layer 520 between the sidewalls 503 is covered with a silicon oxide layer 5031.
Optionally, in this embodiment, the isolation layer 501 includes an ONO layer, specifically, the ONO layer includes an oxide layer 5011 (e.g., silicon oxide), a nitride layer 5012 (e.g., silicon nitride), and an oxide layer 5013 sequentially from bottom to top.
Optionally, in this embodiment, a Shallow Trench Isolation (STI) structure 504 is further formed on the substrate 500.
And step S2, etching the silicon oxide layer by an ICP etching device, and adjusting reaction byproducts accumulated on the side wall by adjusting parameters in the etching process.
Optionally, in this embodiment, the reaction byproducts deposited on the side walls 503 are adjusted by adjusting at least one of bias power, source power, flow rate of the reaction gas, and gas pressure during the etching process, so that after the etching step, the width between the side walls 503 is the same as the width after the silicon oxide layer 5031 is etched by using the CCP etching apparatus. Wherein the reaction by-product comprises a polymer.
Optionally, in this embodiment, the bias power has a value range of 50 watts to 100 watts: optionally, the value of the source power ranges from 500 watts to 800 watts.
Optionally, in this embodiment, the flow rate of the reactant gas ranges from 50SCCM to 100SCCM, and the reactant gas may include carbon tetrafluoride.
Optionally, in this embodiment, the value of the air pressure ranges from 5 mtorr to 15 mtorr.
And step S3, etching the floating gate polysilicon layer between the side walls by ICP etching equipment until the gate oxide layer between the side wall gates is exposed to form a floating gate, and adjusting parameters in the etching process to enable the rate of etching the polysilicon to be greater than the rate of etching silicon oxide.
Referring to fig. 6, a cross-sectional view after etching the floating gate polysilicon layer 520 between the silicon oxide layer 5031 and the sidewall 503 according to the manufacturing method provided by the embodiment of the present application is shown. As shown in fig. 3 and 6, the effect after etching by the manner of the present embodiment is substantially the same as the etching effect of the manufacturing method provided in the related art.
Optionally, in this embodiment, the rate of etching the polysilicon is greater than the rate of etching the silicon oxide by adjusting at least one of the bias power, the source power, the flow rate of the reaction gas, and the gas pressure during the etching process.
Optionally, in this embodiment, the bias power has a value range of 50 w to 100 w; the source power ranges from 300 watts to 500 watts.
Optionally, in this embodiment, the reaction gas includes hydrobromic acid, helium and oxygen; optionally, the flow rate of hydrobromic acid ranges from 100SCCM to 300 SCCM; optionally, the flow rate of the helium gas ranges from 100SCCM to 300 SCCM; optionally, the flow rate of oxygen is in the range of 5SCCM to 10 SCCM.
Optionally, in this embodiment, the range of the air pressure is 20 mtorr to 50 mtorr.
In summary, in the embodiment, the silicon oxide layer of the flash memory device is etched by the ICP etching apparatus, reaction byproducts accumulated on the side walls are adjusted by adjusting parameters in the etching process, the floating gate polysilicon layer between the side walls of the flash memory device is etched by the ICP etching apparatus, and the rate of etching the polysilicon is greater than the rate of etching the silicon oxide by adjusting the parameters in the etching process, so that the silicon oxide layer and the floating gate polysilicon layer of the flash memory device are etched in the same etching apparatus, the complexity of the manufacturing process of the flash memory device is reduced, and the manufacturing efficiency of the flash memory device is improved to a certain extent.
Referring to fig. 7, which shows a flowchart of a method for manufacturing a flash memory device according to an exemplary embodiment of the present application, the method may be the method after step S3 in fig. 4, and the method includes:
in step S4, the Polymer (Polymer RM) is etched away.
In step S5, a Wet Strip (Photoresist Wet Strip) is performed on the Photoresist during etching.
Step S6, measure the width between floating gates, the thickness of the etched floating gate polysilicon layer and the thickness of the remaining silicon nitride layer, respectively.
A method for manufacturing a flash memory device provided in the related art and a method for manufacturing a flash memory device provided in an exemplary embodiment of the present application are compared with each other by specific examples below.
Specifically, a method for manufacturing a flash memory device in the related art includes:
the first stage is as follows: step 1, etching silicon oxide in CCP etching equipment; step 2, etching to remove the polymer; step 3, carrying out wet stripping on the photoresist in the etching process; and 4, measuring the thickness of the silicon oxide.
And a second stage: step 5, cleaning the wafer; step 6, etching the floating gate polysilicon layer in ICP etching equipment to form a floating gate; step 7, etching to remove the polymer; step 8, carrying out wet stripping on the light resistance in the etching process; step 9, measuring the width between the floating gates; step 10, measuring the thickness of the etched floating gate polycrystalline silicon layer; step 11, measuring the thickness of the residual silicon nitride layer.
That is, the etching of the silicon oxide and the floating gate polysilicon layer in the manufacturing method takes 11 steps.
A method of manufacturing a flash memory device according to an exemplary embodiment of the present application includes:
step 1, respectively etching silicon oxide and a floating gate polycrystalline silicon layer in ICP equipment to form a floating gate; step 2, etching to remove the polymer; step 3, carrying out wet stripping on the photoresist in the etching process; step 4, measuring the width between the floating gates; step 5, measuring the thickness of the etched floating gate polycrystalline silicon layer; and 6, the thickness of the residual silicon nitride layer.
Namely, the manufacturing method has 6 steps of etching the silicon oxide and the floating gate polysilicon layer, thereby reducing the complexity of the manufacturing process of the flash memory device to a certain extent.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (17)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, wherein a gate oxide layer, a floating gate polycrystalline silicon layer, an isolation layer and a control gate are sequentially formed on the substrate, a silicon nitride layer is formed at the top end of the control gate, side walls are formed on the silicon nitride layer and the peripheral sides of the control gate, the side walls comprise silicon oxide layers, silicon nitride isolation layers are formed in the side walls, and the silicon oxide layers cover the floating gate polycrystalline silicon layer between the side walls;
etching the silicon oxide layer by ICP etching equipment to expose the floating gate polycrystalline silicon layer between the side walls, and adjusting reaction byproducts accumulated on the side walls by adjusting parameters in the etching process;
and etching the floating gate polycrystalline silicon layer between the side walls by the ICP etching equipment until the gate oxide layer between the side walls is exposed to form a floating gate, and adjusting parameters in the etching process to enable the etching rate of the polycrystalline silicon to be greater than the etching rate of silicon oxide.
2. The method of claim 1, wherein adjusting the reaction byproducts deposited on the sidewall by adjusting parameters during the etching comprises:
and adjusting reaction byproducts accumulated on the side wall by adjusting at least one of bias power, source power, flow rate of reaction gas and gas pressure in the etching process.
3. The method of claim 2, wherein the bias power has a value in a range of 50 watts to 100 watts:
4. the method of claim 2, wherein the source power has a value in a range of 500 watts to 800 watts.
5. The method of claim 2, wherein the reactant gas flow rate has a value in the range of 50SCCM to 100 SCCM.
6. The method of claim 5, wherein the reactant gas comprises carbon tetrafluoride.
7. The method of claim 2, wherein the gas pressure is in a range of 5 mtorr to 15 mtorr.
8. The method of claim 1, wherein adjusting the parameters during etching to cause the rate of etching the polysilicon to be greater than the rate of etching the silicon oxide comprises:
and adjusting at least one of bias power, source power, flow rate of reaction gas and gas pressure in the etching process to enable the etching rate of the polycrystalline silicon to be larger than the etching rate of the silicon oxide.
9. The method of claim 8, wherein the bias power has a value in a range of 50 watts to 100 watts
10. The method of claim 8, wherein the source power has a value in a range of 300 watts to 500 watts.
11. The method of claim 8, wherein the reactant gas comprises hydrobromic acid, helium and oxygen.
12. The method of claim 11, wherein the hydrobromic acid flow rate ranges from 100SCCM to 300 SCCM.
13. The method of claim 12, wherein the flow rate of the helium gas ranges from 100SCCM to 300 SCCM.
14. The method of claim 13, wherein the flow rate of oxygen is in a range of 5SCCM to 10 SCCM.
15. The method of claim 8, wherein the gas pressure ranges from 20 mtorr to 50 mtorr.
16. The method according to any one of claims 1 to 15, wherein the reaction by-products comprise polymers, and after etching the floating gate polysilicon layer between the control gates by the ICP etching apparatus, the method further comprises:
etching to remove the polymer;
carrying out wet stripping on the light resistance in the etching process;
and respectively measuring the width between the floating gates, the thickness of the etched floating gate polycrystalline silicon layer and the thickness of the residual silicon nitride layer.
17. The method of any of claims 1 to 15, wherein the isolation layer comprises an ONO layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111653480A (en) * | 2020-05-09 | 2020-09-11 | 华虹半导体(无锡)有限公司 | Etching method applied to preparation process of memory device |
| CN112736024A (en) * | 2020-12-23 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Etching method |
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| CN105789132A (en) * | 2014-12-16 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Side wall forming method |
| CN106206451A (en) * | 2016-07-27 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory device making method |
| CN109103085A (en) * | 2018-08-06 | 2018-12-28 | 上海华虹宏力半导体制造有限公司 | Flash memory and its manufacturing method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105789132A (en) * | 2014-12-16 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Side wall forming method |
| CN106206451A (en) * | 2016-07-27 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory device making method |
| CN109103085A (en) * | 2018-08-06 | 2018-12-28 | 上海华虹宏力半导体制造有限公司 | Flash memory and its manufacturing method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653480A (en) * | 2020-05-09 | 2020-09-11 | 华虹半导体(无锡)有限公司 | Etching method applied to preparation process of memory device |
| CN112736024A (en) * | 2020-12-23 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Etching method |
| CN112736024B (en) * | 2020-12-23 | 2022-06-07 | 华虹半导体(无锡)有限公司 | Etching method |
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