CN114023746A - NORD flash device and manufacturing method thereof - Google Patents

Abstract

The application discloses a NORD flash manufacturing method, which comprises the following steps: forming a storage unit area and a logic area on a semiconductor substrate, forming a side wall between a word line and a control gate polycrystalline silicon layer in the storage unit area, forming a gate polycrystalline silicon layer in the logic area, and sequentially depositing a first etching barrier layer and a second etching barrier layer; performing dry etching on the logic area, and reserving a first etching barrier layer in the logic area and the storage unit area; removing the first etching barrier layer; and protecting the grid of the logic region, and performing dry etching on the memory cell region to form a floating gate and a control gate of the memory device. In the NORD flash manufacturing process, the hard mask layer is etched and removed in two steps, so that the side wall can be prevented from being etched laterally, pits can not appear on word lines, and the performance of a device is guaranteed.

Description

NORD flash device and manufacturing method thereof

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to an NORD flash device and a manufacturing method thereof.

Background

Flash memory (flash) has been widely used as the best choice for non-volatile memory applications due to its high density, low cost, and electrically programmable, erasable advantages. In general, a floating gate type flash memory generally includes a memory cell (flash cell) formed on a substrate and a logic device located at the periphery of the memory cell. The memory cells (flash cells) have a stacked gate structure including a floating gate and a control gate at least covering the floating gate, wherein the control gate is coupled to control storage and release of electrons in the floating gate.

In the manufacturing process of the NORD flash memory with the floating gate structure, after word line polysilicon of the NORD flash memory device is formed, a polysilicon gate is formed in a logic area, and then etching forming of the NORD flash memory device in a storage unit area is carried out. FIG. 1 is a schematic cross-sectional view of a cell structure to be etched in a memory cell region after a logic region is etched in a current NORD Flash process. Referring to fig. 1, the NORD Flash cell structure includes a semiconductor substrate 100, the semiconductor substrate 100 includes a memory cell region 100A and a logic region 100B, wherein a gate oxide layer 101 is formed on the semiconductor substrate 100 of the memory cell region 100A, a word line 102 is formed on the gate oxide layer 101, a floating gate polysilicon layer 103, a first dielectric layer 104 and a control gate polysilicon layer 105 are sequentially formed on the gate oxide layer 101 at two sides of the word line 102 from bottom to top, and a sidewall 106 is formed between the word line 102 and the control gate polysilicon layer 105. The logic region 100B is formed with a shallow trench isolation structure 109 at the periphery of each region where a logic device needs to be formed. The gate forming of the logic region 100B is prioritized, which may result in the memory cell region 100A having a hard mask layer 107 (the hard mask layer 107 covers the gate 108 formed in the logic region 100B) remaining during the gate forming process of the logic region 100B on the surface of the memory cell region 100A, and finally, an additional etching process for the remaining hard mask layer 107 may be added during the etching forming process of the memory cell region 100A.

Fig. 1a is a schematic cross-sectional view of a cell structure after wet etching is performed on fig. 1 to remove a hard mask layer and a memory cell region is formed by etching. Referring to fig. 1a, the hard mask layer 107 on the surfaces of the memory cell region 100A and the logic region 100B is removed by wet etching, due to the characteristic of isotropy of wet etching, HF causes side etching to silicon dioxide of the sidewall 106 between the word line 102 and the control gate polysilicon layer 105 while removing the hard mask layer by using HF, so that the control gate polysilicon layer 105 and the floating gate polysilicon layer 103 are etched by using the sidewall 106 as a mask in the process of completing the etching formation of the memory cell region 100A in the later period, the control gate and the floating gate formed due to the side etching of the sidewall 106 are shortened, the effective length of the channel is shortened, and the device performance is reduced.

Fig. 1b is a schematic cross-sectional view of the cell structure after dry etching is performed on fig. 1 to remove the hard mask layer and the memory cell region is etched and formed. Referring to fig. 1b, when the memory cell region 100A is dry etched to form the control gate and the floating gate, since the control gate polysilicon layer 105 is covered by the hard mask layer 107, the hard mask layer needs to be additionally etched in the dry etching process, and since the height of the word line is higher than that of the surrounding region, in the dry etching process of the memory cell region 100A, since the hard mask layer 107 on the top of the word line is lower than that of the other regions, the oxide on the top of the word line is excessively etched, so that the problem of pits on the top of the word line occurs, and the reliability of the product is reduced.

Disclosure of Invention

The application provides an NORD flash device and a manufacturing method thereof, and aims to solve the problems that in the NORD flash manufacturing process provided in the related technology, a hard mask is removed by wet etching, so that a side wall is etched laterally, and a pit appears at the top of a word line when dry etching is performed.

In one aspect, an embodiment of the present application provides a method for manufacturing an NORD flash, including:

forming a storage unit area and a logic area on a semiconductor substrate, wherein a side wall is formed between a word line and a control gate polycrystalline silicon layer in the storage unit area, a gate polycrystalline silicon layer is formed in the logic area, and a first etching barrier layer and a second etching barrier layer are sequentially deposited;

performing dry etching on the logic region, forming a gate of a logic device in the logic region, and reserving the first etching barrier layer in the logic region and the memory cell region;

removing the first etching barrier layer;

and fourthly, protecting the grid of the logic region, and performing dry etching on the memory cell region to form a floating gate and a control gate of the memory device.

Optionally, the first etch stop layer comprises a silicon nitride layer.

Optionally, the second etch stop layer comprises a plasma enhanced oxide layer.

Optionally, the first etch stop layer is removed by a wet process using phosphoric acid.

Optionally, the memory cell region includes a gate oxide layer formed on the semiconductor substrate, a word line is formed on the gate oxide layer, a floating gate polysilicon layer, a first dielectric layer and a control gate polysilicon layer are sequentially formed on the gate oxide layer on two sides of the word line from bottom to top, and a gate oxide layer is formed between the polysilicon layer of the logic region and the semiconductor substrate.

Optionally, the first dielectric layer includes ONO, and the ONO includes a silicon dioxide layer, a silicon nitride layer, and a silicon dioxide layer in sequence from bottom to top.

Optionally, the side walls are used as a hard mask to perform dry etching on the memory cell region to form a floating gate and a control gate of the memory device.

Optionally, photoresist is coated on the gate of the logic region in a spinning mode, and the floating gate and the control gate of the memory device are formed by performing dry etching on the memory unit region by taking the side wall as a hard mask.

Alternatively, the NORD flash manufacturing process is further improved and can be used in processes including, but not limited to, the 55nm NORD flash process.

In order to solve the technical problems, the invention provides an NORD flash device which is manufactured by any one of the NORD flash manufacturing methods.

The technical scheme at least comprises the following advantages:

in the NORD flash manufacturing process, after a second etching blocking layer and a first etching blocking layer (a hard mask layer is formed by the first etching blocking layer and the second etching blocking layer) are removed by dry etching and wet etching respectively, the problem that pits are easily formed at the top of a word line due to the fact that the hard mask is removed only by means of the dry etching is avoided, the defect that side walls are laterally etched due to the fact that the hard mask is removed only by means of the wet etching is overcome, the hard mask layer is removed by means of the two-step etching, a grid electrode is formed in a logic area by the dry etching in the first step, the second etching blocking layer is removed by the dry etching, the first etching blocking layer serves as a stopping layer to protect the top of the word line, the first etching blocking layer is removed by the wet etching in the second step, a wet acid agent used can remove the first etching blocking layer and cannot react with silicon dioxide of the side walls, so that the side walls are protected from being laterally etched, and then floating gates and control gates of a storage unit are formed by the dry etching by taking the side walls as the hard mask layer, the lengths of the formed floating gate and the control gate can be ensured, so that the length of a channel is ensured, and the performance of the device is improved.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic cross-sectional view of a cell structure to be etched in a memory cell region after a logic region is etched in a current NORD Flash process;

FIG. 1a is a schematic cross-sectional view of a cell structure after wet etching is performed to remove a hard mask layer and a memory cell region in FIG. 1;

FIG. 1b is a schematic cross-sectional view of the cell structure after dry etching is performed to remove the hard mask layer and the memory cell region in FIG. 1;

FIG. 2 is a schematic flow chart illustrating steps of a method for manufacturing a NORD flash according to an exemplary embodiment of the present application;

FIG. 2a is a schematic cross-sectional view of a NORD flash cell structure prior to a first step of the NORD flash fabrication method;

FIG. 2b is a schematic cross-sectional view of a NORD flash cell structure after a first step of the NORD flash fabrication method;

FIG. 2c is a schematic cross-sectional view of a NORD flash cell structure after a second step of the NORD flash fabrication method;

FIG. 2d is a schematic cross-sectional view of a NORD flash cell structure after a third step of the NORD flash fabrication method;

FIG. 2e is a schematic cross-sectional view of the NORD flash cell structure after performing step four of the NORD flash fabrication method.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

FIG. 2 is a flow chart illustrating steps of a method for manufacturing a NORD flash according to an exemplary embodiment of the present application. Referring to fig. 2, the method for manufacturing NORD flash according to the present invention includes the steps of:

s21, forming a storage unit area and a logic area on the semiconductor substrate, wherein a side wall is formed between a word line and a control gate polycrystalline silicon layer in the storage unit area, a polycrystalline silicon layer is formed in the logic area, and a first etching barrier layer and a second etching barrier layer are deposited in sequence;

s22, performing dry etching on the logic area, forming a gate of a logic device in the logic area, and reserving the first etching barrier layer in the logic area and the memory cell area;

s23, removing the first etching barrier layer;

s24, protecting the grid of the logic area, and dry etching the memory unit area to form the floating grid and the control grid of the memory device.

In order to more intuitively disclose the technical features of the present invention and to highlight the beneficial effects of the present invention, the working principle of the method for manufacturing NORD flash according to the present invention will now be explained with reference to the specific embodiments. In the specific embodiments, the formation processes, methods, structural properties, dimensions, and the like of the functional layers are merely examples, and should not be construed as limiting the technical scope of the present invention. Conventional processes, materials, etc. in this field are not described in detail.

For completeness of disclosure of the technical solution, before the specific steps of the method for manufacturing NORD flash according to the present invention are performed, the structure of the NORD flash unit is properly illustrated, and fig. 2a is a schematic cross-sectional structure of the NORD flash unit before the step of the method for manufacturing NORD flash is performed. Referring to fig. 2a, a memory cell region 200A and a logic region 200B are formed on a semiconductor substrate 200, wherein the memory cell region 200A includes a gate oxide layer 201 formed on the semiconductor substrate 200, a word line 202 is formed on the gate oxide layer 201, a floating gate polysilicon layer 203, a first dielectric layer 204 and a control gate polysilicon layer 205 are sequentially formed on the gate oxide layer 201 on two sides of the word line 202 from bottom to top, in an embodiment of the present invention, the first dielectric layer 204 includes ONO, which sequentially includes a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer from bottom to top, and a sidewall 206 is formed between the word line 202 and the control gate polysilicon layer 205 in the memory cell region 200A. A shallow trench isolation structure 209 is formed in the periphery of each region in the logic region 200B where a logic device needs to be formed. The logic region 200B includes a gate oxide layer 202 and a gate polysilicon layer 208 sequentially formed on the semiconductor substrate 200, and the logic region 200B is not etched to form a gate of a logic device.

S21, forming a storage unit area and a logic area on the semiconductor substrate, wherein a side wall is formed between a word line and a control gate polycrystalline silicon layer in the storage unit area, a gate polycrystalline silicon layer is formed in the logic area, and a first etching barrier layer and a second etching barrier layer are deposited in sequence;

FIG. 2b is a schematic cross-sectional view of a NORD flash cell structure after a first step of the NORD flash fabrication method. Referring to fig. 2b, a first etch stop layer 207a and a second etch stop layer 207b are sequentially deposited on the NORD flash cell structure based on the above structure, specifically, the first etch stop layer 207a includes, but is not limited to, a silicon nitride layer, and the second etch stop layer 207b includes, but is not limited to, a plasma enhanced oxide layer. The first etch stopper 207a and the second etch stopper 207B constitute a hard mask layer for dry etching the logic region 200B.

S22, performing dry etching on the logic area, forming a gate of a logic device in the logic area, and reserving the first etching barrier layer in the logic area and the memory cell area;

FIG. 2c is a schematic cross-sectional view of the NORD flash cell structure after performing step two of the NORD flash fabrication method. Referring to fig. 2c, the logic region 200B is dry etched, in the process of the dry etching, the second etching stop layer 207B is completely removed as a depletion layer, a gate 208 of a logic device is formed in the logic region 200B after the dry etching, the first etching stop layer 207a is reserved in both the logic region 200B and the memory cell region 200A, that is, the first etching stop layer 207a (silicon nitride layer) covers the surface of the gate 208 of the logic region 200B, and the first etching stop layer 207a (silicon nitride layer) covers the control gate polysilicon layer 205, the sidewall 206 and the word line 202 of the memory cell region 200A.

S23, removing the first etching barrier layer;

FIG. 2d is a schematic cross-sectional view of the NORD flash cell structure after the third step of the NORD flash fabrication method. Referring to fig. 2d, after the first etching stop layer 207a is removed by wet etching with phosphoric acid, the memory cell region 200A has a portion of the exposed control gate polysilicon layer 205, exposed sidewalls 206, and a gate 208 of a logic device is formed in the logic region 200B. In the embodiment of the present invention, the first etching stop layer 207a is a silicon nitride layer, and during the phosphoric acid wet etching process, phosphoric acid reacts with the silicon nitride layer to remove the silicon nitride layer, and phosphoric acid does not react with silicon dioxide of the sidewall 206, so that the sidewall 206 does not have a side etching phenomenon.

S24, protecting the grid of the logic area, and dry etching the memory unit area to form the floating grid and the control grid of the memory device.

FIG. 2e is a schematic cross-sectional view of the NORD flash cell structure after performing step four of the NORD flash fabrication method. Referring to fig. 2e, a photoresist 210 is spun on the gate 208 of the logic region 200B to protect the gate 208 of the logic region 200B, and the sidewall spacers 206 are used as a hard mask to perform a dry etching on the memory cell region 200A to form a floating gate and a control gate of the memory device. Since the sidewall 206 maintains a normal shape during the process of removing the hard mask layer formed by the first etching stop layer 207a and the second etching stop layer 207b, the floating gate and the control gate obtained by dry etching with the sidewall 206 as the hard mask can ensure normal lengths, thereby ensuring the length of the channel and improving the performance of the device.

To sum up, in the embodiment of the present application, after removing the second etching blocking layer and the first etching blocking layer (the first etching blocking layer and the second etching blocking layer constitute the hard mask layer) by dry etching and wet etching respectively in the NORD flash manufacturing process, the problem that pits are easily generated at the top of the word line due to only relying on dry etching is avoided, the disadvantage that the side wall is laterally etched due to only relying on wet etching to remove the hard mask is overcome, the etching is performed in two steps to remove the hard mask layer, the gate is formed in the logic region by the dry etching performed in the first step, the second etching blocking layer is removed by the dry etching, the first etching blocking layer is used as a stop layer to protect the top of the word line, the first etching blocking layer is removed by the wet etching performed in the second step, and the used wet acid agent can remove the first etching blocking layer of the side wall without reacting with silicon dioxide, so as to protect the side wall from being laterally etched, and then the side wall is used as a hard mask layer to etch the storage unit region by a dry method to form a floating gate and a control gate of the storage device, so that the lengths of the formed floating gate and the formed control gate can be ensured, the length of a channel is ensured, and the performance of the storage device is improved.

Alternatively, the method of making the NORD flash described in the above example: which can be used in processes including, but not limited to, the 55nmNORD flash process.

The invention also provides an NORD flash device, which is manufactured by the NORD flash manufacturing method according to the above embodiment, and which includes: a memory cell region 200A and a logic region 200B are formed on a semiconductor substrate 200, wherein the memory cell region 200A includes a gate oxide layer 201 formed on the semiconductor substrate 200, a word line 202 is formed on the gate oxide layer 201, a floating gate 203, a first dielectric layer 204 and a control gate 205 are sequentially formed on the gate oxide layer 201 on both sides of the word line 202 from bottom to top, in an embodiment of the present invention, the first dielectric layer 204 includes an ONO, which sequentially includes a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer from bottom to top, and a sidewall 206 is formed between the word line 202 and the control gate polysilicon layer 205 in the memory cell region 200A. The logic region 200B includes a gate oxide layer 202 and a gate 208 sequentially formed on the semiconductor substrate 200, and further includes a photoresist 210 spin-coated to protect the gate 208 of the logic region 200B when a floating gate and a control gate of the memory device are formed by dry etching the memory cell region 200A. In the process of forming the NORD flash device, the logic region 200B is subjected to dry etching to form the gate 208 and remove the second etching stop layer 207B, which is equivalent to reducing the thickness of a mask layer of the NORD flash device, and is beneficial to further removing the first etching stop layer 207a (the first etching stop layer 207a and the second etching stop layer 207B are equivalent to mask layers), and because the first etching stop layer 207a and the second etching stop layer 207B have different chemical compositions, the sidewall 206 is not undercut while the first etching stop layer 207a is removed by adopting a wet etching process different from the wet etching process for removing the second etching stop layer 207B, so that the floating gate and the control gate of the memory device are formed by dry etching the memory cell region 200A by using the hard mask layer 206 as the hard mask layer, the lengths of the formed floating gate and the control gate can be ensured, and the length of a channel can be ensured, and the performance of the device is improved.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (9)

1. A method for manufacturing NORD flash, which is characterized by comprising the following steps:

forming a storage unit area and a logic area on a semiconductor substrate, wherein a side wall is formed between a word line and a control gate polycrystalline silicon layer in the storage unit area, a gate polycrystalline silicon layer is formed in the logic area, and a first etching barrier layer and a second etching barrier layer are sequentially deposited;

performing dry etching on the logic region, forming a gate of a logic device in the logic region, and reserving the first etching barrier layer in the logic region and the memory cell region;

removing the first etching barrier layer;

and fourthly, protecting the grid of the logic region, and performing dry etching on the memory cell region to form a floating gate and a control gate of the memory device.

2. The method of claim 1 wherein said first etch stop layer comprises a silicon nitride layer.

3. The method of manufacturing NORD flash as claimed in claim 1 or 2, wherein the second etch stop layer comprises a plasma enhanced oxide layer.

4. The method of manufacturing NORD flash as claimed in claim 1, wherein the first etch stop layer is removed by a phosphoric acid wet process.

5. The method of claim 1, wherein the memory cell region comprises a gate oxide layer formed on a semiconductor substrate, a word line is formed on the gate oxide layer, a floating gate polysilicon layer, a first dielectric layer and a control gate polysilicon layer are sequentially formed on the gate oxide layer on two sides of the word line from bottom to top, and a gate oxide layer is formed between the polysilicon layer of the logic region and the semiconductor substrate.

6. The method of claim 5, wherein the first dielectric layer comprises ONO comprising a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer from bottom to top.

7. The method of claim 1, wherein a photoresist is applied to the gate of the logic region by spin coating, and the sidewall is used as a hard mask to perform dry etching on the memory cell region to form a floating gate and a control gate of the memory device.

8. The method of making NORD flash as claimed in claim 1, wherein it can be used in the process including but not limited to 55nm NORD flash.

9. An NORD flash device manufactured by the method of manufacturing an NORD flash according to any one of claims 1 to 8.

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