CN111653482B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN111653482B CN111653482B CN202010401650.2A CN202010401650A CN111653482B CN 111653482 B CN111653482 B CN 111653482B CN 202010401650 A CN202010401650 A CN 202010401650A CN 111653482 B CN111653482 B CN 111653482B
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- 238000000034 method Methods 0.000 title claims abstract description 78
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 118
- 229920005591 polysilicon Polymers 0.000 claims abstract description 87
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 50
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 238000001259 photo etching Methods 0.000 claims abstract description 13
- 238000003860 storage Methods 0.000 claims abstract description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- -1 phosphorus ions Chemical class 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 5
- 238000002513 implantation Methods 0.000 abstract description 2
- 230000006870 function Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 238000010586 diagram Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 229940079593 drug Drugs 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The application discloses a manufacturing method of a semiconductor device, and relates to the field of semiconductor manufacturing. The method comprises the steps of providing a substrate, wherein a grid structure of a flash memory device is formed in a storage device area of the substrate; performing well region ion implantation on the logic device region; sequentially forming a gate oxide layer and a polysilicon layer; opening the memory device region and closing the logic device region through a photoetching process; removing the polysilicon layer, the gate oxide layer and the silicon nitride layer corresponding to the memory device region; carrying out N-type doping on a polycrystalline silicon layer corresponding to the logic device region; and etching the polysilicon layer corresponding to the logic device area to form the polysilicon gate of the logic device. The method has the advantages that the reasonable process method comprises the process sequence, and the function failure caused by the obvious influence on the thickness of grid polycrystalline silicon of a logic area and the POLY resistance due to the integration of the embedded flash memory can be avoided in the process integration of the embedded flash memory, particularly in the advanced process with the implantation doping of the N-type polycrystalline silicon.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
As a nonvolatile semiconductor device, flash memory has the advantages of convenience, high storage density, good reliability, and the like, and is widely applied to various devices such as mobile phones, notebook computers, and usb disks along with the development of economy and technology. A typical flash memory device has a stacked gate structure including a floating gate and a control gate overlying the floating gate.
In the field of semiconductor technology, embedded flash memory technology is a technology in which a flash memory device and a logic device are integrated and manufactured on the same substrate. In a conventional manufacturing method, a gate of an embedded flash memory device is formed first, and then a gate of a logic device in a peripheral circuit region is formed. In the advanced process of the nodes of 90nm and below, the electrical thickness of the gate oxide layer is reduced, and in order to reduce the polycrystalline silicon depletion effect and the influence of polycrystalline silicon doping diffusion on the logic device, the polycrystalline silicon layer of the logic device is doped before the polycrystalline silicon grid of the logic device is formed.
Before forming the polysilicon gate of the logic device, the silicon nitride on the outer side of the gate of the embedded flash memory device needs to be removed, however, in the process of removing the silicon nitride, the doped polysilicon layer is also corroded to be greatly reduced, and the process of the subsequent logic device area and the performance of the logic device are seriously influenced.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a method of manufacturing a semiconductor device. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, where the method includes:
providing a substrate, wherein the substrate comprises a storage device area and a logic device area, a grid structure of a flash memory device is formed in the storage device area, and a silicon nitride layer is arranged on the outer side of the grid structure of the flash memory device;
performing well region ion implantation on the logic device region;
sequentially forming a gate oxide layer and a polysilicon layer, wherein the gate oxide layer and the polysilicon layer are used for forming a gate of a logic device;
opening the memory device region and closing the logic device region through a photoetching process;
removing the polysilicon layer, the gate oxide layer and the silicon nitride layer corresponding to the memory device region;
carrying out N-type doping on a polycrystalline silicon layer corresponding to the logic device region;
and etching the polysilicon layer corresponding to the logic device area to form the polysilicon gate of the logic device.
Optionally, performing well region ion implantation on the logic device region, including:
forming a first hard mask layer, wherein the first hard mask layer is made of silicon nitride;
removing the first hard mask layer corresponding to the logic device area through photoetching and etching processes;
and carrying out well region ion implantation on the logic device area.
Optionally, removing the polysilicon layer, the gate oxide layer and the silicon nitride layer corresponding to the memory device region includes:
etching and removing the polysilicon layer above the grid structure of the flash memory device;
and removing the gate oxide layer above the gate structure of the flash memory device and the silicon nitride layer outside the flash memory device structure by a wet etching process.
Optionally, the removing the gate oxide layer above the gate structure of the flash memory device and the silicon nitride layer outside the flash memory device structure by a wet etching process includes:
determining the dosage of dilute hydrofluoric acid according to the thickness of the gate oxide layer, and removing the gate oxide layer by using the dilute hydrofluoric acid;
the amount of hot phosphoric acid used is determined according to the thickness of the silicon nitride layer, and the silicon nitride layer is removed by using the hot phosphoric acid.
Optionally, the N-type doping is performed on the polysilicon layer corresponding to the logic device region, including:
defining an N-type doped region of the logic device through a photoetching process;
and according to the N-type doped region, performing ion implantation on the polycrystalline silicon layer corresponding to the logic device region.
Optionally, performing ion implantation on the polysilicon layer corresponding to the logic device region according to the N-type doped region, including:
and injecting phosphorus ions into the polycrystalline silicon layer corresponding to the logic device region according to the N-type doped region.
Optionally, etching the polysilicon layer corresponding to the logic device region to form a polysilicon gate of the logic device includes:
defining a gate region of the logic device through a photoetching process;
and etching the polysilicon layer corresponding to the logic device region according to the gate region of the logic device to form the polysilicon gate of the logic device.
Optionally, before the polysilicon layer corresponding to the logic device region is etched to form a polysilicon gate of the logic device, the method further includes:
a second hard mask layer is formed.
Optionally, the gate structure of the flash memory device includes a floating gate, an inter-gate dielectric layer located above the floating gate, a control gate located above the inter-gate dielectric layer, an isolation oxide layer located above the control gate, and a word line polysilicon gate.
Optionally, the inter-gate dielectric layer is an ONO structure, and the ONO structure is formed by stacking an oxide layer, a silicon nitride layer, and an oxide layer.
The technical scheme at least comprises the following advantages:
in an advanced embedded flash memory integration process, when a polysilicon gate of a logic device is manufactured, a gate oxide layer and a polysilicon layer are sequentially formed on a substrate, then a memory device area is opened, the logic device area is closed, the polysilicon layer, the gate oxide layer and a silicon nitride layer corresponding to the memory device area are sequentially removed, then the polysilicon layer of the logic device area is subjected to N-type doping, and then the polysilicon gate of the logic device is formed through an etching process; because the logic device area is sealed when the silicon nitride layer of the flash memory device is removed, and the N-type doping is carried out on the polycrystalline silicon layer of the logic device after the silicon nitride layer of the flash memory device is removed, the polycrystalline silicon layer of the logic device is prevented from being consumed by corrosive liquid for removing the silicon nitride, the thickness of the polycrystalline silicon layer of the logic device is ensured, and the effect that the resistance value of the polycrystalline silicon gate of the logic device is prevented from being influenced by the embedded flash memory process is achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method of semiconductor fabrication according to an embodiment of the present application;
FIG. 2 is a flow chart of a method of semiconductor fabrication according to another embodiment of the present application;
FIG. 3 is a schematic diagram illustrating an embodiment of a semiconductor manufacturing method according to the present disclosure;
FIG. 4 is a schematic diagram illustrating an embodiment of a semiconductor manufacturing method according to the present disclosure;
FIG. 5 is a schematic diagram illustrating an embodiment of a semiconductor manufacturing method according to the present disclosure;
FIG. 6 is a schematic diagram illustrating an embodiment of a semiconductor manufacturing method according to the present disclosure;
FIG. 7 is a schematic diagram illustrating an embodiment of a semiconductor manufacturing method according to the present disclosure;
FIG. 8 is a schematic diagram illustrating an embodiment of a semiconductor manufacturing method according to the present disclosure;
FIG. 9 is a schematic diagram illustrating an embodiment of a semiconductor manufacturing method according to the present disclosure;
fig. 10 is a schematic diagram illustrating an implementation of a semiconductor manufacturing method according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown, the method at least includes the following steps:
in step 101, a substrate is provided, the substrate includes a memory device region and a logic device region, the memory device region is formed with a gate structure of a flash memory device, and a silicon nitride layer is disposed outside the gate structure of the flash memory device.
The memory device region on the substrate is used to form a flash memory device and the logic device region on the substrate is used to form a logic device.
In the process of manufacturing a semiconductor device, a gate electrode of a logic device is formed after a gate electrode structure of a flash memory device is formed, silicon nitride is used in the process of forming the gate electrode structure of the flash memory device, a silicon nitride layer is remained on the outer side of the gate electrode structure of the flash memory device after the gate electrode structure of the flash memory device is formed, and the remained silicon nitride layer is removed in the subsequent processing.
In step 102, well region ion implantation is performed on the logic device.
And defining a trap injection region of the logic device through a photoetching process, and then carrying out ion injection according to the trap injection region to form a well region of the logic device in a logic device region in the substrate.
In step 103, a gate oxide layer and a polysilicon layer are sequentially formed, and the gate oxide layer and the polysilicon layer are used for forming a gate of a logic device.
And forming a gate oxide layer on the substrate, depositing a polycrystalline silicon layer, wherein the gate oxide layer and the polycrystalline silicon layer corresponding to the logic area are used for forming a grid electrode of the logic device.
In step 104, the memory device region is opened and the logic device region is closed by a photolithography process.
Because the polycrystalline silicon layer and the gate oxide layer corresponding to the memory device region need to be removed and the polycrystalline silicon layer and the gate oxide layer corresponding to the logic device region need to be reserved, the logic device region is covered by photoresist, and the memory device region is not covered by the photoresist.
In step 105, the polysilicon layer, the gate oxide layer and the silicon nitride layer corresponding to the memory device region are removed.
And etching to remove the polysilicon layer corresponding to the memory device region, and removing the gate oxide layer and the silicon nitride layer corresponding to the memory device region by a wet etching process.
Optionally, determining the dosage of dilute hydrofluoric acid according to the thickness of the gate oxide layer, and removing the gate oxide layer by using the dilute hydrofluoric acid; the amount of hot phosphoric acid is determined according to the thickness of the silicon nitride layer, and the silicon nitride layer is removed by using the hot phosphoric acid.
In step 106, the polysilicon layer corresponding to the logic device region is doped N-type.
And removing the photoresist above the logic device area, opening the logic device area by utilizing the photoetching process again, and closing the storage device area.
And carrying out N-type doping on the polycrystalline silicon layer corresponding to the logic device region through an ion implantation process.
Optionally, a window is opened in the logic device region through a photolithography process, and the polysilicon layer is N-doped through the opened window, or all the polysilicon layers in the logic device region are N-doped.
In step 107, the polysilicon layer corresponding to the logic device region is etched to form a polysilicon gate of the logic device.
And defining a polysilicon gate pattern of the logic device in the logic device area through a photoetching process, and etching the polysilicon layer according to the polysilicon gate pattern to obtain the polysilicon gate of the logic device.
In summary, in the method for manufacturing a semiconductor device according to the embodiment of the present application, when a logic device is manufactured, a gate oxide layer and a polysilicon layer are sequentially formed on a substrate, then a memory device region is opened, the logic device region is closed, the polysilicon layer, the gate oxide layer and a silicon nitride layer corresponding to the memory device region are sequentially removed, then N-type doping is performed on the polysilicon layer of the logic device region, and then a polysilicon gate of the logic device is formed through an etching process; because the logic device area is sealed when the silicon nitride layer of the flash memory device is removed, and the N-type doping is carried out on the polycrystalline silicon layer of the logic device after the silicon nitride layer of the flash memory device is removed, the polycrystalline silicon layer of the logic device is prevented from being consumed by corrosive liquid for removing the silicon nitride, the thickness of the polycrystalline silicon layer of the logic device is ensured, and the effect that the resistance value of the polycrystalline silicon gate of the logic device is prevented from being influenced by the embedded flash memory process is achieved.
Referring to fig. 2, a flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present application is shown, the method at least includes the following steps:
in step 201, a substrate is provided, where the substrate includes a memory device region and a logic device region, the memory device region is formed with a gate structure of a flash memory device, and a silicon nitride layer is disposed outside the gate structure of the flash memory device.
As shown in fig. 3, the substrate includes a memory device region 31 formed with a gate structure 33 of a flash memory device and a logic device region 32.
The gate structure 33 of the flash memory device includes a floating gate 34, an intergate dielectric layer 35 over the floating gate 34, a control gate 36 over the intergate dielectric layer 35, a spacer oxide layer 37 over the control gate 36, and a word line polysilicon gate 38.
As shown in fig. 3, an oxide layer is provided between the floating gate 34 and the substrate 30, an oxide layer is provided on the periphery of the word line 38, a silicon nitride layer is further provided between the spacer oxide layer 37 and the oxide layer on the periphery of the word line 38, and a silicon nitride layer is also provided between the floating gate 34, the inter-gate dielectric layer 35, and the oxide layer on the periphery of the word line 38.
The spacer oxide layer 37 is provided with a silicon nitride layer 39 on the outer side thereof, and the silicon nitride layer 39 is removed in a subsequent process.
Optionally, a silicon oxide layer is provided on top of the word line 38.
Optionally, shallow trench isolation 40 is further disposed on the substrate.
Optionally, the inter-gate dielectric layer is an Oxide-Nitride-Oxide (ONO) structure, and the ONO structure is formed by stacking an Oxide layer, a silicon Nitride layer, and the Oxide layer from bottom to top.
In step 202, a first hard mask layer is formed, wherein the first hard mask layer is made of silicon nitride.
Optionally, the first hard mask layer is removed together with the silicon nitride layer outside the spacer oxide layer in a subsequent process.
In step 203, the first hard mask layer corresponding to the logic device region is removed by photolithography and etching processes.
Spin-coating photoresist on the substrate, defining a first hard mask layer pattern to be etched by using a mask plate, and after exposure and development, covering no photoresist on the logic device area and covering the storage device area with photoresist; and removing the first hard mask layer corresponding to the logic device area by an etching process.
Defining a well injection region pattern of the logic device through a photoetching process; and performing well region ion implantation on the logic device region through an ion implantation process by using a well implantation region pattern of the logic device.
And after the well region ion implantation of the logic device is completed, removing the photoresist above the substrate.
In step 204, a gate oxide layer and a polysilicon layer are sequentially formed, and the gate oxide layer and the polysilicon layer are used to form a gate of the logic device.
Optionally, a gate oxide layer is formed by high-temperature oxidation, and then a polysilicon layer is deposited. The thickness of the gate oxide layer and the thickness of the polysilicon layer are determined according to actual conditions.
As shown in fig. 4, a first hard mask layer 41, a gate oxide layer 42 and a polysilicon layer 43 are sequentially formed above a gate structure of the flash memory device, and a gate oxide layer 42 and a polysilicon layer 43 are formed in a logic device region.
In step 205, the memory region is opened and the logic device region is closed by a photolithography process.
This step is explained in step 104 above and will not be described here.
As shown in fig. 5, the logic device region 32 is covered with photoresist 44, and the memory device region 31 is not covered with photoresist.
In step 206, the polysilicon layer over the gate structure of the flash memory device is etched away.
After the polysilicon layer above the gate structure of the flash memory device is removed, the photoresist on the substrate is removed.
As shown in fig. 6, the polysilicon layer corresponding to the memory device region 31 is removed.
In step 207, the gate oxide layer over the gate structure of the flash memory device and the silicon nitride layer outside the flash memory device structure are removed by a wet etching process.
Removing the gate oxide layer above the gate structure of the flash memory device by using a proper amount of dilute hydrofluoric acid according to the thickness of the gate oxide layer; and removing the silicon nitride layer outside the flash memory device structure by using proper hot phosphoric acid according to the thickness of the silicon nitride layer.
Comparing fig. 7 with fig. 6, it can be seen that the gate oxide layer 42 and the first hard mask layer 41 corresponding to the memory device region 31 are removed, and the silicon nitride layer 39 outside the spacer oxide layer 37 is removed.
In step 208, an N-type doped region of the logic device is defined by a photolithography process.
Because the thickness of the gate oxide layer is thinner in the advanced process of the 90nm node and below, in order to reduce the influence of the polycrystalline silicon depletion effect and the polycrystalline silicon doping diffusion on the logic device, the gate oxide layer of the logic device needs to be subjected to N-type doping after being formed.
Optionally, determining an N-type doped region according to a polysilicon gate of the logic device; the size of the region of the N-type doped region is larger than that of the polysilicon gate, or the size of the region of the N-type doped region is equal to that of the polysilicon gate.
And spin-coating a photoresist on the substrate, defining an N-type doped region through a mask, and transferring the pattern of the N-type doped region to the photoresist layer through exposure and development.
The N-type doped region is located in the logic device region.
In step 209, a polysilicon layer corresponding to the logic device region is ion implanted according to the N-type doped region.
As shown in fig. 8, the substrate is covered with a photoresist 44, and the photoresist layer has a pattern of N-type doped regions; the polysilicon layer 43 corresponding to the logic device region 32 is ion implanted according to the defined N-type doped region.
And after the N-type doping is finished, removing the photoresist on the substrate.
Optionally, according to the N-type doped region, phosphorus ions are implanted into the polysilicon layer corresponding to the logic device region.
Because the polycrystalline silicon N-type doping process is carried out after the wet etching process step, the influence of liquid medicines such as hot phosphoric acid and the like on the thickness of the N-type polycrystalline silicon by wet etching can be avoided, and the resistance characteristic drift of the polycrystalline silicon is avoided.
In step 210, a second hard mask layer is formed.
Optionally, the material of the second hard mask layer is an oxide.
As shown in fig. 9, a second hard mask layer 45 is formed on the substrate 30.
In step 211, a gate region of the logic device is defined by a photolithography process.
As shown in fig. 10, the gate region of the logic device is defined by a photoresist 44.
In step 212, a polysilicon layer corresponding to the logic device region is etched according to the gate region of the logic device to form a polysilicon gate of the logic device.
Optionally, the second hard mask layer is etched according to the gate region of the logic device defined by the photoresist, and then the polysilicon layer is etched by taking the etched second hard mask layer as a mask.
For N-type logic devices, the polysilicon gate is formed with N-type doping.
After the step is finished, the photoresist on the substrate is removed, and the subsequent processing is continued.
In summary, in the method for manufacturing a semiconductor device according to the embodiment of the present application, when a logic device is manufactured, a gate oxide layer and a polysilicon layer are sequentially formed on a substrate, then a memory device region is opened, the logic device region is closed, the polysilicon layer, the gate oxide layer and a silicon nitride layer corresponding to the memory device region are sequentially removed, then N-type doping is performed on the polysilicon layer of the logic device region, and then a polysilicon gate of the logic device is formed through an etching process; the method realizes the integration of the embedded flash memory process, and particularly avoids the effect of functional failure caused by the influence of the thickness of a polysilicon gate of a logic device and the resistance of the polysilicon due to the integration of the embedded flash memory in the advanced process with N-type polysilicon doping.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate, wherein the substrate comprises a storage device area and a logic device area, a grid structure of a flash memory device is formed in the storage device area, and a silicon nitride layer is arranged on the outer side of the grid structure of the flash memory device;
performing well region ion implantation on the logic device region;
sequentially forming a gate oxide layer and a polysilicon layer, wherein the gate oxide layer and the polysilicon layer are used for forming a gate of a logic device;
opening the memory device region through a photoetching process, and closing the logic device region;
removing the polysilicon layer, the gate oxide layer and the silicon nitride layer corresponding to the memory device region;
carrying out N-type doping on the polycrystalline silicon layer corresponding to the logic device region;
and etching the polysilicon layer corresponding to the logic device area to form the polysilicon gate of the logic device.
2. The method of claim 1, wherein the performing a well region ion implantation on the logic device region comprises:
forming a first hard mask layer, wherein the first hard mask layer is made of silicon nitride;
removing the first hard mask layer corresponding to the logic device area through photoetching and etching processes;
and carrying out well region ion implantation on the logic device area.
3. The method of claim 1, wherein removing the polysilicon layer, the gate oxide layer and the silicon nitride layer corresponding to the memory device region comprises:
etching and removing the polysilicon layer above the grid structure of the flash memory device;
and removing the gate oxide layer above the gate structure of the flash memory device and the silicon nitride layer outside the flash memory device structure by a wet etching process.
4. The method of claim 3, wherein the removing the gate oxide layer over the gate structure of the flash memory device and the silicon nitride layer outside the flash memory device structure by a wet etching process comprises:
determining the using amount of dilute hydrofluoric acid according to the thickness of the gate oxide layer, and removing the gate oxide layer by using the dilute hydrofluoric acid;
and determining the using amount of hot phosphoric acid according to the thickness of the silicon nitride layer, and removing the silicon nitride layer by using the hot phosphoric acid.
5. The method of claim 1, wherein the N-type doping the polysilicon layer corresponding to the logic device region comprises:
defining an N-type doped region of the logic device through a photoetching process;
and according to the N-type doped region, performing ion implantation on the polycrystalline silicon layer corresponding to the logic device region.
6. The method of claim 5, wherein performing ion implantation on the polysilicon layer corresponding to the logic device region according to the N-type doped region comprises:
and injecting phosphorus ions into the polycrystalline silicon layer corresponding to the logic device region according to the N-type doped region.
7. The method of claim 1, wherein the etching the polysilicon layer corresponding to the logic device region to form a polysilicon gate of a logic device comprises:
defining a gate region of the logic device through a photoetching process;
and etching the polysilicon layer corresponding to the logic device region according to the gate region of the logic device to form the polysilicon gate of the logic device.
8. The method of claim 1, wherein before the etching the polysilicon layer corresponding to the logic device region to form the polysilicon gate of the logic device, the method further comprises:
a second hard mask layer is formed.
9. The method of claim 1, wherein the gate structure of the flash memory device comprises a floating gate, an intergate dielectric layer over the floating gate, a control gate over the intergate dielectric layer, a spacer oxide layer over the control gate, and a wordline polysilicon gate.
10. The method of claim 9, wherein the intergate dielectric layer is an ONO structure formed by an oxide layer, a silicon nitride layer, and an oxide layer stacked.
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| CN111129021A (en) * | 2019-12-27 | 2020-05-08 | 华虹半导体(无锡)有限公司 | NOR Flash grid polycrystalline silicon process method |
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| CN102637646A (en) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | Preparation method of memory |
| CN111129021A (en) * | 2019-12-27 | 2020-05-08 | 华虹半导体(无锡)有限公司 | NOR Flash grid polycrystalline silicon process method |
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