CN111128936A - 集成芯片及形成集成芯片的方法 - Google Patents
集成芯片及形成集成芯片的方法 Download PDFInfo
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- CN111128936A CN111128936A CN201910887659.6A CN201910887659A CN111128936A CN 111128936 A CN111128936 A CN 111128936A CN 201910887659 A CN201910887659 A CN 201910887659A CN 111128936 A CN111128936 A CN 111128936A
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- layer
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- passivation layer
- conductive
- etch stop
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 344
- 238000002161 passivation Methods 0.000 claims abstract description 126
- 125000006850 spacer group Chemical group 0.000 claims abstract description 102
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 238000001465 metallisation Methods 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000011229 interlayer Substances 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 11
- 239000003989 dielectric material Substances 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000000151 deposition Methods 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- -1 oxides (e.g. Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000005137 deposition process Methods 0.000 description 5
- 230000000873 masking effect Effects 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
在一些实施例中,提供一种集成芯片及一种形成集成芯片的方法。集成芯片包括设置在半导体衬底之上的金属化结构,其中金属化结构包括设置在层间介电结构中的内连结构。钝化层设置在金属化结构之上,其中内连结构的上表面至少部分地设置在钝化层的相对的内侧壁之间。侧壁间隔件沿着钝化层的相对的内侧壁设置,其中侧壁间隔件具有经圆化的侧壁。导电结构设置在钝化层、侧壁间隔件的经圆化的侧壁及内连结构的上表面上。
Description
技术领域
本发明实施例是有关于一种集成芯片及一种形成集成芯片的方法。
背景技术
现代集成芯片包括排列在半导体衬底上/内的数百万个或数十亿个半导体装置。所述半导体装置连接到包括内连结构的金属化结构。所述内连结构包括将半导体装置彼此电连接的多个导电特征(例如,导线、通孔及触点)。通常,所述内连结构终止在位于金属化结构之上的接垫处。所述接垫可包括金属层,所述金属层提供从集成芯片到外部组件(例如,集成芯片封装体)的导电连接。
发明内容
本发明实施例提供一种集成芯片,所述集成芯片包括:半导体衬底、金属化结构、钝化层、侧壁间隔件及导电结构。所述金属化结构设置在所述半导体衬底之上,所述金属化结构包括设置在层间介电结构中的内连结构。所述钝化层设置在所述金属化结构之上,其中所述内连结构的上表面至少部分地设置在所述钝化层的相对的内侧壁之间。所述侧壁间隔件沿着所述钝化层的所述相对的内侧壁设置,所述侧壁间隔件具有多个经圆化的侧壁。所述导电结构设置在所述钝化层、所述侧壁间隔件的所述多个经圆化的侧壁及所述内连结构的所述上表面上,其中所述导电结构是接垫及/或重布线层。
本发明实施例提供一种集成芯片,所述集成芯片包括:半导体衬底、金属化结构、刻蚀停止层、钝化层、侧壁间隔件及导电结构。所述金属化结构设置在所述半导体衬底之上,所述金属化结构包括设置在层间介电结构中的内连结构。所述刻蚀停止层设置在所述金属化结构上,其中所述内连结构包括最上部导电元件,所述最上部导电元件至少部分地设置在所述刻蚀停止层的相对的内侧壁之间。所述钝化层设置在所述刻蚀停止层上,所述钝化层包括相对的内侧壁,所述相对的内侧壁从所述刻蚀停止层的上表面延伸到所述钝化层的上表面。所述侧壁间隔件设置在所述刻蚀停止层上且沿着所述钝化层的所述相对的内侧壁设置,其中所述侧壁间隔件具有面向彼此的多个经圆化的侧壁。所述导电结构设置在所述最上部导电元件、所述刻蚀停止层的所述相对的内侧壁、所述侧壁间隔件的所述多个经圆化的侧壁及所述钝化层的所述上表面上。
本发明实施例提供一种形成集成芯片的方法,所述方法包括:在半导体衬底之上形成金属化结构且在所述半导体衬底上形成半导体装置,所述金属化结构包括设置在层间介电结构中的内连结构;在所述金属化结构之上形成刻蚀停止层;在所述刻蚀停止层上形成介电层;移除所述介电层的一部分以形成钝化层,其中所述钝化层的相对的内侧壁界定第一开口;在所述刻蚀停止层上且沿着所述钝化层的所述相对的内侧壁形成侧壁间隔件,其中所述侧壁间隔件形成有多个经圆化的侧壁;移除所述刻蚀停止层的一部分以形成暴露出所述内连结构的第二开口;以及形成接垫或重布线层,所述接垫或所述重布线层与所述多个经圆化的侧壁、所述钝化层的上表面及所述内连结构接触。
附图说明
结合附图阅读以下详细说明,会最好地理解本公开的各方面。注意,根据行业中的标准惯例,各种特征未按比例绘制。事实上,为论述的清晰起见,可任意地增大或减小各种特征的尺寸。
图1A到图1B示出集成电路的一些实施例的各种视图,所述集成电路具有减小接垫颈缩(bond pad necking)的侧壁间隔件。
图2A到图2B示出集成电路的一些实施例的各种视图,所述集成电路具有减小重布线层颈缩(redistribution layer necking)的侧壁间隔件。
图3A到图3B示出图1A到图1B所示集成电路的一些实施例的各种剖视图。
图4到图12示出形成图3A到图3B所示集成电路的一些实施例的一系列剖视图。
图13示出形成集成电路的方法的一些实施例的流程图,所述集成电路具有减小接垫颈缩的侧壁间隔件。
[符号说明]
100:集成电路
102:半导体衬底
104:半导体装置
106:源极/漏极区
108:栅极介电质
110:栅极电极
112:金属化结构
116:层间介电结构
118:内连结构
119:最上部导电元件
119s:第三内侧壁
119u:上表面
120:钝化层
120s:第一内侧壁
122:侧壁间隔件
122s:经圆化的侧壁
124:接垫
124p、202p、204p:周界
202:重布线层
204:顶盖层
206:输入/输出结构
302:区域
304:刻蚀停止层
304s:第二内侧壁
402:第一介电层
502:第一开口
504:第一刻蚀
602:第二介电层
702:第二刻蚀
802:第三刻蚀
804:第二开口
902:导电层
1002:掩模层
1004:第四刻蚀
1102:剥离剂
1300:流程图
1302、1304、1306、1308、1310:动作
D:距离
H:高度
T1:第一厚度
T2:第二厚度
T3:第三厚度
具体实施方式
将参考图式阐述本公开,在图式中自始至终使用相似的参考编号来指代相似的元件,且在图式中所说明的结构未必按比例绘制。应了解,此详细说明及对应的图绝不限制本公开的范围,且所述详细说明及各图仅提供几个实例来说明可展示本发明概念的一些方式。
本公开提供许多不同的实施例或实例以实施本公开的不同特征。下文阐述组件及排列的具体实例以使本公开简明。当然,这些仅是实例,并不旨在进行限制。举例来说,在以下说明中,第一特征形成在第二特征之上或形成在第二特征上可包括第一特征与第二特征形成为直接接触的实施例,且还可包括额外特征可形成在第一特征与第二特征之间使得第一特征与第二特征不可直接接触的实施例。另外,本公开可在各种实例中重复使用参考编号及/或字母。此重复是出于简明及清晰目的,本质上并不规定所述的各种实施例及/或配置之间的关系。
此外,为便于说明起见,本文中可使用例如“在…之下(beneath)”、“低于(below)”、“下部(lower)”、“在…上方(above)”、“上部(upper)”等空间相对用语来阐述一个元件或特征与另外的元件或特征之间的关系,如图中所说明。除了图中所绘示的定向之外,所述空间相对用语还旨在囊括器件在使用或操作中的不同定向。可以其他方式对设备进行定向(旋转90度或处于其他定向),且同样地可对本文中所使用的空间相对描述符加以相应地解释。
一些集成芯片(integrated chip,IC)包括设置在半导体衬底上/内的多个半导体装置(例如,金属氧化物半导体场效晶体管(Metal-Oxide-Semiconductor Field-EffectTransistor,MOSFET))。金属化结构设置在半导体衬底之上。所述金属化结构包括将所述多个半导体装置电耦合在一起的内连结构(例如,铜内连线)。通常,钝化层设置在所述金属化结构之上。多个接垫设置在金属化层之上且延伸穿过钝化层以在内连结构与输入/输出(Input/Output,I/O)结构(例如,打线接合(wire bond)、焊料凸块(solder bump)等)之间提供导电界面(conductive interface)。
上述集成芯片所面临的一个挑战是接垫颈缩(及/或重布线层颈缩)。接垫颈缩(及/或重布线层颈缩)是接垫(bond pad)(及/或重布线层(redistribution layer,RDL))的厚度沿着钝化层的侧壁减小。举例来说,接垫的第一部分沿着钝化层的侧壁设置且穿过钝化层而延伸到接垫的第二部分,所述第二部分设置在钝化层的侧壁之间且在内连结构的一部分上。由于接垫的第一部分具有大的厚度变化(例如,接垫的第一部分的厚度在接近钝化层的侧壁的顶部处比在接近钝化层的侧壁的底部处大),因此所述接垫的所述第一部分可发生接垫颈缩。由于接垫颈缩,对接垫的后续处理(例如,用以剥离掩模层的清洗工艺)可能会侵蚀内连结构,因此会导致内连结构损坏。因此,接垫颈缩可给集成芯片的性能带来负面影响(例如,功耗增加、使用寿命缩短等)。
在各种实施例中,本公开涉及一种集成芯片(IC)。所述集成芯片包括设置在半导体衬底之上的金属化结构。所述金属化结构包括设置在层间介电(interlayerdielectric,ILD)结构中的内连结构。钝化层设置在金属化结构上,其中内连结构的上表面至少部分地设置在钝化层的相对的内侧壁之间。具有经圆化的侧壁的侧壁间隔件(sidewall spacer)沿着钝化层的相对的内侧壁设置。导电结构(例如,接垫或重布线层)设置在钝化层、侧壁间隔件的经圆化的侧壁及内连结构的上表面上。
由于侧壁间隔件具有经圆化的侧壁且沿着钝化层的侧壁设置,因此沿着经圆化的侧壁延伸的导电结构的一部分的厚度变化可得以减小。因此,侧壁间隔件可减小接垫颈缩(及/或重布线层颈缩)。因此,侧壁间隔件可防止接垫颈缩(及/或重布线层颈缩)所导致的内连结构损坏,借此提高集成芯片的性能(例如,功耗减少、使用寿命延长等)。
图1A到图1B示出集成电路(integrated circuit)100的一些实施例的各种视图,集成电路100具有减小接垫颈缩的侧壁间隔件122。图1A示出图1B所示集成电路100的一些实施例的剖视图。图1B示出图1A所示集成电路100的一些实施例的俯视图,其中接垫124(参见下文)的材料被移除,因此以虚线示出接垫124的周界(perimeter)124p。
如图1A到图1B中所示,集成电路100包括半导体衬底102。在一些实施例中,半导体衬底102包括任何类型的半导体主体(例如,单晶硅/互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)块体、硅锗(SiGe)、绝缘体上有硅(SOI)等)。
半导体装置104设置在半导体衬底102上/内。在一些实施例中,半导体装置104可以是晶体管(例如,金属氧化物半导体场效晶体管(MOSFET))。在这些实施例中,半导体装置104包括设置在半导体衬底102中的一对源极/漏极区106。在其他此类实施例中,栅极介电质108设置在半导体衬底102上、源极/漏极区106之间。在其他此类实施例中,栅极电极110设置在栅极介电质108上。在另外的一些实施例中,半导体装置104可以是高电压MOSFET。
金属化结构112设置在半导体衬底102及半导体装置104之上。在一些实施例中,金属化结构112包括设置在层间介电(interlayer dielectric,ILD)结构116中的内连结构118,层间介电结构116具有一个或多个层间介电层。内连结构118包括多个导电元件(例如,金属线、金属通孔、金属触点等),所述多个导电元件被配置成将半导体装置104电耦合到集成电路100的其他半导体装置(未示出)。在其他实施例中,内连结构118的最上部导电元件119(例如,最上部金属线)具有与层间介电结构116的上表面实质上共面的上表面。在另外的一些实施例中,最上部导电元件119的上表面可与内连结构118的上表面对应。
在一些实施例中,内连结构118可包含例如铜、钨、铝、一些其他导电材料或前述材料的组合。在其他实施例中,层间介电结构116可包含以下中的一者或多者:例如,低介电常数(low-k)介电层(例如,介电常数小于约3.9的介电质)、超低介电常数(ultra-low-k)介电层、氧化物(例如,二氧化硅(SiO2))、一些其他介电材料或前述材料的组合。
钝化层120设置在金属化结构112之上。在一些实施例中,钝化层120设置在层间介电结构116及最上部导电元件119上。在其他实施例中,钝化层120包括从钝化层120的上表面延伸到金属化结构112的多个第一内侧壁120s。在另外的一些实施例中,最上部导电元件119的上表面的至少一部分设置在第一内侧壁120s之间。
在一些实施例中,第一内侧壁120s可实质上垂直。在其他实施例中,钝化层120可具有实质上平坦的上表面。在另外的一些实施例中,钝化层120可包含例如氧化物(例如,SiO2)、氮化物(例如,氮化硅(SiN))、氮氧化物(例如,氮氧化硅(SiOXNY))、一些其他介电材料或前述材料的组合。应了解,在一些实施例中,钝化层120可包括一个或多个介电层。
侧壁间隔件122设置在金属化结构112之上且设置成沿着第一内侧壁120s。在一些实施例中,侧壁间隔件122设置在最上部导电元件119的上表面上。在其他实施例中,侧壁间隔件122可设置在层间介电结构116的上表面上。在其他实施例中,侧壁间隔件122具有多个经圆化的侧壁122s。在另外的一些实施例中,侧壁间隔件122的相对的经圆化的侧壁122s面向彼此。
在其他实施例中,侧壁间隔件122可包含例如氧化物(例如,SiO2)、氮化物(例如,SiN)、氮氧化物(例如,SiOXNY)、一些其他介电材料或前述材料的组合。在另外的一些实施例中,侧壁间隔件122与钝化层120可包含不同的材料。在其他实施例中,侧壁间隔件122与钝化层120可包含相同的材料。
接垫124设置在金属化结构112、侧壁间隔件122及钝化层120之上。在一些实施例中,接垫124设置在最上部导电元件119、侧壁间隔件122的经圆化的侧壁122s及钝化层120的上表面上。其他实施例中,接垫124电耦合到内连结构118,且因此电耦合到半导体装置104。在另外的一些实施例中,接垫124为钝化层120、侧壁间隔件122及内连结构118共形地加衬(conformally lining)。
在一些实施例中,接垫124可包含例如铝、铜、铝铜、一些其他导电材料或前述材料的组合。在其他实施例中,接垫124与内连结构118包含不同的导电材料。举例来说,接垫124可包含铝,且内连结构118可包含铜。在另外的一些实施例中,接垫124可包含内连结构118并不包含的导电材料。
由于侧壁间隔件122沿着第一内侧壁120s设置且由于侧壁间隔件122具有经圆化的侧壁122s,因此沿着侧壁间隔件122的经圆化的侧壁122s延伸的接垫124的一部分的厚度变化可得以减小。因此,侧壁间隔件122可减小接垫颈缩。因此,侧壁间隔件122可防止接垫颈缩所导致的内连结构118损坏,借此提高集成电路100的性能(例如,功耗减少、使用寿命延长等)。
图2A到图2B示出集成电路100的一些实施例的各种视图,所述集成电路100具有减小重布线层(RDL)颈缩的侧壁间隔件122。图2A示出图2B所示集成电路100的一些实施例的剖视图。图2B示出图2A所示集成电路100的一些实施例的俯视图,其中重布线层202(参见下文)的材料及顶盖层204(参见下文)的材料被移除,因此以第一虚线示出重布线层202的周界202p且以第二虚线示出顶盖层204的周界204p。
如图2A到图2B中所示,重布线层(RDL)202设置在金属化结构112、侧壁间隔件122及钝化层120之上。在一些实施例中,重布线层202设置在最上部导电元件119、侧壁间隔件122的经圆化的侧壁122s及钝化层120的上表面上。在另外的一些实施例中,重布线层202为钝化层120、侧壁间隔件122及内连结构118共形地加衬。
在一些实施例中,重布线层202电耦合到内连结构118,且因此电耦合到半导体装置104。重布线层202被配置成提供最上部导电元件119与输入/输出(I/O)结构206之间的电连接,输入/输出结构206设置在与最上部导电元件119间隔的位置处。举例来说,重布线层202可在横向方向上从最上部导电元件119跨越钝化层120的上表面延伸到与最上部导电元件119间隔的位置。因此,输入/输出结构206可设置在所述位置处且经由重布线层202电耦合到半导体装置104。
在一些实施例中,输入/输出结构206设置在重布线层202上。在其他实施例中,输入/输出结构206设置在凸块下金属化结构(under-bump metallization structure)(未示出)上,凸块下金属化结构设置在重布线层202上。在其他实施例中,输入/输出结构206被配置成将重布线层202电耦合到外部电路系统(例如,印刷电路板、外部微处理器等)。在其他实施例中,输入/输出结构206可以是例如凸块结构/球结构、打线接合结构等。在另外的一些实施例中,输入/输出结构206可包含例如金(Au)、焊料(solder)、一些其他导电材料或前述材料的组合。
在一些实施例中,重布线层202可包含例如铝、铜、铝铜、一些其他导电材料或前述材料的组合。在其他实施例中,重布线层202与内连结构118包含不同的导电材料。举例来说,重布线层202可包含铝,且内连结构118可包含铜。在其他实施例中,重布线层202可包含内连结构118并不包含的导电材料。在另外的一些实施例中,重布线层202及/或接垫124(例如,参见图1A到图1B)可被称为导电结构。
由于侧壁间隔件122沿着第一内侧壁120s设置且由于侧壁间隔件122具有经圆化的侧壁122s,因此沿着侧壁间隔件122的经圆化的侧壁122s延伸的重布线层202的一部分的厚度变化可得以减小。因此,侧壁间隔件122可减小重布线层颈缩。因此,侧壁间隔件122可防止重布线层颈缩所导致的内连结构118损坏,借此提高集成电路100的性能(例如,功耗减少,使用寿命延长等)。
在一些实施例中,顶盖层204设置在钝化层120及重布线层202之上。在这些实施例中,输入/输出结构206穿过顶盖层204延伸至与重布线层202接触的位置处,以使得输入/输出结构206电耦合到重布线层202。在其他实施例中,顶盖层204可具有实质上平坦的上表面。在另外的一些实施例中,顶盖层204可包含例如氧化物(例如,SiO2)、氮化物(例如,SiN)、氮氧化物(例如,SiOXNY)、一些其他介电材料或前述材料的组合。
图3A到图3B示出图1A到图1B所示集成电路100的一些实施例的各种剖视图。图3A示出图1A到图1B所示集成电路100的一些更详细实施例的剖视图。图3B示出图3A所示区域302的一些实施例的放大剖视图。应了解,在一些实施例中,图2A到图2B所示集成电路100可包括与图3A到图3B所示出的实质上类似特征。举例来说,在一些实施例中,在阐述图3A到图3B的以下段落中可由“重布线层202”代替“接垫124”。
如图3A到图3B中所示,刻蚀停止层304设置在钝化层120与金属化结构112之间。在一些实施例中,刻蚀停止层304设置在层间介电结构116及最上部导电元件119上。在其他实施例中,钝化层120及侧壁间隔件122设置在刻蚀停止层304上。在这些实施例中,第一内侧壁120s可从刻蚀停止层304的上表面延伸到钝化层120的上表面。在其他此类实施例中,侧壁间隔件122的经圆化的侧壁122s可从刻蚀停止层304延伸到钝化层120。
在一些实施例中,刻蚀停止层304包括从最上部导电元件119延伸到侧壁间隔件122的多个第二内侧壁304s。在其他实施例中,最上部导电元件119的上表面的至少一部分设置在第二内侧壁304s之间。在其他实施例中,相对的第一内侧壁120s与相对的第二内侧壁304s远远间隔开。在其他实施例中,第二内侧壁304s被磨圆。在其他实施例中,第二内侧壁304s可实质上垂直。在其他实施例中,第二内侧壁304s中的一者或多者可从层间介电结构116延伸到侧壁间隔件122。在这些实施例中,层间介电结构116的上表面的至少一部分设置在第二内侧壁304s之间。
在一些实施例中,刻蚀停止层304包含例如氧化物(例如,SiO2)、氮化物(例如,SiN)、氮氧化物(例如,SiOXNY)、一些其他介电材料或前述材料的组合。在其他实施例中,刻蚀停止层304与侧壁间隔件122包含不同的材料。在其他实施例中,刻蚀停止层304与钝化层120及侧壁间隔件122两者包含不同的材料。在另外的一些实施例中,刻蚀停止层304的高度(例如,在刻蚀停止层304的最上部表面与最下部表面之间)可介于约100纳米(nm)与约200纳米之间。
在一些实施例中,最上部导电元件119包括多个第三内侧壁119s,第三内侧壁119s从最上部导电元件119的上表面119u延伸到刻蚀停止层304。在这些实施例中,最上部导电元件119的上表面119u设置在最上部导电元件119的最上部表面与最上部导电元件119的下表面之间。在其他实施例中,相对的第二内侧壁304s与相对的第三内侧壁119s远远间隔开。在另外的一些实施例中,第三内侧壁119s被磨圆。在其他实施例中,第三内侧壁119s可实质上垂直。
在一些实施例中,第三内侧壁119s、第二内侧壁304s及侧壁间隔件122的经圆化的侧壁122s分别界定共同的内侧壁(common inner sidewall),所述共同的内侧壁从最上部导电元件119延伸到钝化层120的上表面。在其他实施例中,所述共同的内侧壁可具有比第一内侧壁120s的曲率半径大的曲率半径。在另外的一些实施例中,接垫124通过沿着共同的内侧壁延伸而从钝化层120的上表面连续延伸到最上部导电元件119的上表面119u。在这些实施例中,设置在钝化层120之上的接垫124的一部分可具有实质上平坦的上表面,设置成沿着共同的内侧壁的接垫124的一部分可具有经圆化的侧壁,且设置在最上部导电元件119的上表面119u之上的接垫124的一部分可具有实质上平坦的上表面。
在一些实施例中,侧壁间隔件122可具有第一厚度T1,第一厚度T1是钝化层120的高度H的至少约40%。在其他实施例中,侧壁间隔件122的高度可与钝化层120的高度H实质上相同。在其他实施例中,钝化层120的高度H与第一厚度T1之间的比率可以是例如7比3、6比4、或1比1。在其他实施例中,钝化层120的高度H可介于约200纳米与约600纳米之间。在其他实施例中,第一厚度T1可介于约80纳米与约600纳米之间。在另外的一些实施例中,侧壁间隔件122的经圆化的侧壁122s可具有比第一内侧壁120s的曲率半径大的曲率半径。
在一些实施例中,相对的第一内侧壁120s之间的距离D可小于或等于约3微米(μm)。在其他实施例中,接垫124可具有第二厚度T2及第三厚度T3。在一些实施例中,第二厚度T2可介于约100纳米与约10,000纳米之间。在其他实施例中,第二厚度T2可小于或等于约300纳米。在其他实施例中,第三厚度T3可介于约100纳米与约10,000纳米之间。在其他实施例中,第三厚度T3可小于或等于约300纳米。在其他实施例中,第二厚度T2与第三厚度T3之间的差可是正/负(±)20%。在其他实施例中,第二厚度T2可大于第三厚度T3。
在一些实施例中,输入/输出结构206设置在接垫124上。在这些实施例中,输入/输出结构206可直接设置在接垫124上方。在其他此类实施例中,输入/输出结构206可直接设置在最上部导电元件119上方。在其他实施例中,输入/输出结构206被配置成将接垫124电耦合到外部电路系统(例如,印刷电路板、外部微处理器等)。
图4到图12示出形成图3A到图3B所示集成电路100的一些实施例的一系列剖视图。
如图4中所示,在金属化结构112之上形成刻蚀停止层304。在一些实施例中,金属化结构112包括设置在层间介电(ILD)结构116中的内连结构118。在其他实施例中,内连结构118的最上部导电元件119(例如,最上部金属线)具有与层间介电结构116的上表面实质上共面的上表面。
在一些实施例中,用于形成刻蚀停止层304的工艺包括在层间介电结构116及最上部导电元件119上沉积刻蚀停止层304。在其他实施例中,可例如通过化学气相沉积(chemical vapor deposition,CVD)、物理气相沉积(physical vapor deposition,PVD)、原子层沉积(atomic layer deposition,ALD)、溅射、一些其他沉积工艺或前述工艺的组合来沉积刻蚀停止层304。
如图4中所示,在刻蚀停止层304之上形成第一介电层402。在一些实施例中,第一介电层402可包含例如氧化物(例如,SiO2)、氮化物(例如,SiN)、氮氧化物(例如,SiOXNY)、一些其他介电材料或前述材料的组合。在其他实施例中,第一介电层402与刻蚀停止层304包含不同的介电材料。
在一些实施例中,用于形成第一介电层402的工艺包括在刻蚀停止层304上沉积第一介电层402。在其他实施例中,可例如通过CVD、PVD、ALD、溅射、一些其他沉积工艺或前述工艺的组合来沉积第一介电层402。
如图5中所示,在刻蚀停止层304之上形成钝化层120。在一些实施例中,用于形成钝化层120的工艺包括在第一介电层402(例如,参见图4)中形成第一开口502。在其他实施例中,第一开口502是由钝化层120的多个第一内侧壁120s与刻蚀停止层304的上表面界定。在另外的一些实施例中,第一开口502的相对侧以小于或等于约3微米间隔开。
在一些实施例中,用于形成钝化层120的工艺包括在第一介电层402上沉积掩模层(未示出)(例如,正性光刻胶/负性光刻胶)。此后,通过在适当位置处的所述掩模层来在第一介电层402中执行第一刻蚀504(例如,湿式刻蚀/干式刻蚀)。在一些实施例中,第一刻蚀504是干式刻蚀(例如,反应性离子刻蚀(Reactive-Ion Etching,RIE))。第一刻蚀504通过移除第一介电层402的未被掩蔽部分在第一介电层402中形成第一开口502,借此形成钝化层120。随后,在一些实施例中,剥离掩模层。
如图6中所示,在钝化层120及刻蚀停止层304之上形成第二介电层602。在一些实施例中,第二介电层602是形成作为第一开口502及钝化层120的上表面加衬的共形层。在其他实施例中,第二介电层602可包含例如氧化物(例如,SiO2)、氮化物(例如,SiN)、氮氧化物(例如,SiOXNY)、一些其他介电材料或前述材料的组合。在其他实施例中,第二介电层602可与刻蚀停止层304及/或钝化层120包含不同的介电材料。在其他实施例中,第二介电层602可与钝化层120包含相同的介电材料。
在一些实施例中,用于形成第二介电层602的工艺包括在钝化层120的上表面、第一内侧壁120s及刻蚀停止层304的上表面上沉积第二介电层602。在其他实施例中,可通过例如CVD、PVD、ALD、溅射、一些其他沉积工艺或前述工艺的组合来沉积第二介电层602。
如图7中所示,在刻蚀停止层304上且沿着第一内侧壁120s形成侧壁间隔件122。在一些实施例中,侧壁间隔件122形成有多个经圆化的侧壁122s。在其他实施例中,用于形成侧壁间隔件122的工艺包括在第二介电层602(例如,参见图6)中执行第二刻蚀702(例如,湿式刻蚀/干式刻蚀)。在一些实施例中,第二刻蚀702是干式刻蚀(例如,RIE)。在其他实施例中,第二刻蚀702移除第二介电层602的水平区段但不移除第二介电层602的垂直区段,借此形成侧壁间隔件122。
如图8中所示,在最上部导电元件119之上形成第二开口804。在一些实施例中,第二开口804是由侧壁间隔件122的经圆化的侧壁122s、刻蚀停止层304的多个第二内侧壁304s、最上部导电元件119的多个第三内侧壁119s及最上部导电元件119的上表面119u界定。
在一些实施例中,用于形成第二开口804的工艺包括在钝化层120及侧壁间隔件122上沉积第二掩模层(未示出)(例如,正性光刻胶/负性光刻胶)。此后,通过在适当位置处的第二掩模层在刻蚀停止层304中执行第三刻蚀802(例如,湿式刻蚀/干式刻蚀)。在一些实施例中,第三刻蚀802是干式刻蚀(例如,RIE)。第三刻蚀802移除刻蚀停止层304的未被掩蔽部分,借此形成第二开口804。随后,在一些实施例中,剥离第二掩模层。在其他实施例中,可在不形成第二掩模层的情况下执行第三刻蚀802。在此种其他实施例中,第三刻蚀802可以比移除侧壁间隔件122及/或钝化层120的暴露部分还要高的速率来选择性地移除刻蚀停止层304的暴露部分。
如图9中所示,在最上部导电元件119、刻蚀停止层304、侧壁间隔件122及钝化层120之上形成导电层902。在一些实施例中,导电层902是形成作为第二开口804及钝化层120的上表面加衬的共形层。在其他实施例中,导电层902可形成有小于或等于约300纳米的厚度(例如,导电层902的上表面与底表面之间的距离)。在其他实施例中,导电层902可包含例如铝、铜、铝铜、一些其他导电材料或前述材料的组合。在其他实施例中,导电层902与内连结构118包含不同的导电材料。在另外的一些实施例中,导电层902可包含内连结构118并不包含的导电材料。
在一些实施例中,用于形成导电层902的工艺包括在最上部导电元件119的上表面119u、第三内侧壁119s、第二内侧壁304s、侧壁间隔件122的经圆化的侧壁122s及钝化层120的上表面上沉积导电层902。在其他实施例中,可通过例如CVD、PVD、ALD、溅射、电化学镀覆(electrochemical plating)、无电镀覆(electroless plating)、一些其他沉积工艺或前述工艺的组合来沉积导电层902。
如图10中所示,在最上部导电元件119、刻蚀停止层304、侧壁间隔件122及钝化层120之上形成接垫124。在一些实施例中,用于形成接垫124的工艺包括在导电层902(例如,参见图9)上形成掩模层1002。在一些实施例中,用于形成掩模层1002的工艺包括在导电层902上沉积(例如,经由旋转涂布工艺)光刻胶层(未示出)。此后,将光刻胶层选择性地暴露于辐射(radiation)。随后,将光刻胶层暴露于显影剂以移除光刻胶层的暴露(或未暴露)于辐射的部分,借此形成掩模层1002。
在一些实施例中,通过位于适当位置处的掩模层1002在导电层902中执行第四刻蚀1004(例如,湿式刻蚀/干式刻蚀)。在一些实施例中,第四刻蚀1004是干式刻蚀(例如,反应性离子刻蚀(RIE))。第四刻蚀1004移除导电层902的未被掩蔽部分,借此形成接垫124。
如图11中所示,从接垫124移除掩模层1002(例如,参见图10)。在一些实施例中,用于移除掩模层1002的工艺包括将掩模层1002暴露于剥离剂1102。在其他实施例中,剥离剂1102是溶剂型剥离剂(solvent-based stripping agent)。在其他实施例中,通过将半导体衬底102(且因此将掩模层1002)浸没在剥离剂1102中来将掩模层1002暴露于剥离剂1102。在另外的一些实施例中,在从接垫124移除掩模层1002之后,完成接垫124的形成。
在一些实施例中,剥离剂1102包含有机化合物(例如,儿茶酚(catechol,C6H6O2))。在其他实施例中,剥离剂1102可包含胺(amine)。在其他实施例中,剥离剂1102以比移除接垫124的导电材料快的速率移除内连结构118的导电材料。举例来说,剥离剂1102可以大于或等于剥离剂移除接垫124的导电材料的速率的十倍的速率来移除内连结构的导电材料。
由于侧壁间隔件122沿着第一内侧壁120s设置且由于侧壁间隔件122具有经圆化的侧壁122s,因此沿着侧壁间隔件122的经圆化的侧壁122s延伸的接垫124的一部分的厚度变化可得以减小。因此,侧壁间隔件122可减小接垫颈缩。因此,接垫124可防止内连结构118暴露于剥离剂1102,借此防止剥离剂1102损坏内连结构118(例如,不期望地移除内连结构118的一些部分)。
如图12中所示,在接垫124之上形成输入/输出(I/O)结构206。在一些实施例中,在接垫124之上形成输入/输出结构206会将输入/输出结构206经由接垫124电耦合到内连结构118。在一些实施例中,用于形成输入/输出结构206的工艺包括在接垫124上沉积导电结构(未示出)。在其他实施例中,导电结构可包含例如金(Au)、焊料(solder)、一些其他导电材料或前述材料的组合。在其他实施例中,可通过例如CVD、PVD、ALD、溅射、电化学镀覆、无电镀覆、一些其他沉积工艺或前述工艺的组合来沉积导电结构。
此后,可对导电结构执行回焊(reflow)工艺(例如,回焊焊接),借此形成输入/输出结构206。应了解,在一些实施例中,可利用其他工艺(例如,打线接合)来形成输入/输出结构206。在另外的一些实施例中,在形成输入/输出结构206之后,完成集成电路100的形成。
如图13中所示出,提供形成集成电路(IC)的方法的一些实施例的流程图1300,所述集成电路具有减小接垫颈缩的侧壁间隔件。应了解,在一些实施例中,流程图1300中所提供的方法可实质上类似于形成具有减小重布线层(RDL)颈缩的侧壁间隔件的集成电路(IC)的方法。虽然图13的流程图1300在本文中被说明且阐述为一系列的动作或事件,但应了解,不应在限制意义上解释这些动作或事件的所说明排序。举例来说,除本文中所说明及/或所述的动作或事件之外,一些动作还可以不同的次序发生及/或与其他动作或事件同时发生。此外,并非所有的所说明动作皆可被需要来实施本文中所说明的一个或多个方面或实施例,且可在一个或多个单独的动作及/或阶段中实施本文中所绘示的动作中的一者或多者。
在动作1302处,在金属化结构之上形成第一开口,其中所述金属化结构包括设置在层间介电(ILD)结构中的内连结构。所述第一开口是由钝化层的多个内侧壁及刻蚀停止层的上表面界定。图4到图5示出与动作1302对应的一些实施例的一系列剖视图。
在动作1304处,在刻蚀停止层上且沿着钝化层的内侧壁形成侧壁间隔件,其中侧壁间隔件具有多个经圆化的侧壁。图6到图7示出与动作1304对应的一些实施例的一系列剖视图。
在动作1306处,在金属化结构之上形成第二开口,其中第二开口是由侧壁间隔件的经圆化的侧壁、刻蚀停止层的多个内侧壁及内连结构的上表面界定。图8示出与动作1306对应的一些实施例的剖视图。
在动作1308处,在金属化结构之上形成接垫并将所述接垫电耦合到内连结构,其中接垫形成在内连结构的上表面、刻蚀停止层的内侧壁、侧壁间隔件的经圆化的侧壁及所述钝化层的上表面上。图9到图11示出与动作1308对应的一些实施例的一系列剖视图。
在动作1310处,在接垫之上形成输入/输出(I/O)结构,其中I/O结构经由接垫电耦合到内连结构。图12示出与动作1310对应的一些实施例的剖视图。
在一些实施例中,本公开提供一种集成芯片(IC)。所述集成芯片包括半导体衬底。金属化结构设置在所述半导体衬底之上,其中所述金属化结构包括设置在层间介电(ILD)结构中的内连结构。钝化层设置在所述金属化结构之上,其中所述内连结构的上表面至少部分地设置在所述钝化层的相对的内侧壁之间。侧壁间隔件沿着所述钝化层的所述相对的内侧壁设置,其中所述侧壁间隔件具有多个经圆化的侧壁。导电结构设置在所述钝化层、所述侧壁间隔件的所述多个经圆化的侧壁及所述内连结构的所述上表面上,其中所述导电结构是接垫及/或重布线层(RDL)。
根据一些实施例,在所述的集成芯片中,所述侧壁间隔件的所述多个经圆化的侧壁面向彼此。根据一些实施例,在所述的集成芯片中,所述钝化层的所述相对的内侧壁实质上垂直。根据一些实施例,在所述的集成芯片中,所述导电结构的第一上表面设置在所述钝化层的所述相对的内侧壁之间且设置在所述钝化层的上表面之下。根据一些实施例,在所述的集成芯片中,所述导电结构包括经圆化的侧壁,所述侧壁从所述导电结构的所述第一上表面延伸到所述导电结构的第二上表面,且其中所述导电结构的所述第二上表面设置在所述钝化层的所述上表面之上且横向延伸超过所述钝化层的所述相对的内侧壁中的一者。根据一些实施例,所述的集成芯片还包括:刻蚀停止层,设置在所述钝化层与所述金属化结构之间,其中所述导电结构设置在所述刻蚀停止层的相对的内侧壁上。根据一些实施例,在所述的集成芯片中,所述刻蚀停止层包含第一介电材料;且所述钝化层包含与所述第一介电材料不同的第二介电材料。根据一些实施例,在所述的集成芯片中,所述钝化层的所述相对的内侧壁与所述刻蚀停止层的所述相对的内侧壁远远间隔开。根据一些实施例,在所述的集成芯片中,其中所述刻蚀停止层的所述相对的内侧壁被磨圆。根据一些实施例,在所述的集成芯片中,所述刻蚀停止层的所述经圆化的相对的内侧壁及所述侧壁间隔件的所述多个经圆化的侧壁分别界定多个共同的经圆化的侧壁。根据一些实施例,在所述的集成芯片中,所述刻蚀停止层与所述侧壁间隔件、所述钝化层、所述内连结构及所述层间介电结构接触。
在其他实施例中,本公开提供一种集成芯片(IC)。所述集成芯片包括半导体衬底。金属化结构设置在所述半导体衬底之上,其中所述金属化结构包括设置在层间介电(ILD)结构中的内连结构。刻蚀停止层设置在所述金属化结构上,其中所述内连结构包括至少部分地设置在所述刻蚀停止层的相对的内侧壁之间的最上部导电元件。钝化层设置在所述刻蚀停止层上,其中所述钝化层包括相对的内侧壁,所述相对的内侧壁从所述刻蚀停止层的上表面延伸到所述钝化层的上表面。侧壁间隔件设置在所述刻蚀停止层上且沿着所述钝化层的所述相对的内侧壁设置,其中所述侧壁间隔件具有面向彼此的多个经圆化的侧壁。导电结构设置在所述最上部导电元件、所述刻蚀停止层的所述相对的内侧壁、所述侧壁间隔件的所述多个经圆化的侧壁及所述钝化层的所述上表面上。
根据一些实施例,在所述的集成芯片中,所述内连结构包含第一导电材料;且所述导电结构包含与所述第一导电材料不同的第二导电材料。根据一些实施例,在所述的集成芯片中,所述侧壁间隔件的厚度是所述钝化层的高度的至少约40%。根据一些实施例,在所述的集成芯片还包括半导体装置,设置在所述半导体衬底上,其中所述内连结构将所述半导体装置电耦合到所述导电结构;以及输入/输出结构,设置在所述导电结构上,其中所述输入/输出结构被配置成将所述导电结构电耦合到外部电路系统。根据一些实施例,在所述的集成芯片中,所述最上部导电元件包括:相对的内侧壁,从所述最上部导电元件的第一上表面延伸到所述最上部导电元件的第二上表面,其中所述导电结构设置在所述最上部导电元件的所述相对的内侧壁上。根据一些实施例,在所述的集成芯片中,所述侧壁间隔件的所述多个经圆化的侧壁、所述刻蚀停止层的相对的内侧壁及所述最上部导电元件的所述相对的内侧壁分别界定多个共同的相对的侧壁。
在又一些其他实施例中,本公开提供一种形成集成芯片(IC)的方法。所述方法包括:在半导体衬底之上形成金属化结构且在所述半导体衬底上形成半导体装置,其中所述金属化结构包括设置在层间介电(ILD)结构中的内连结构。在所述金属化结构之上形成刻蚀停止层。在所述刻蚀停止层上形成介电层。移除所述介电层的一部分以形成钝化层,其中所述钝化层的相对的内侧壁界定第一开口。在所述刻蚀停止层上且沿着所述钝化层的所述相对的内侧壁形成侧壁间隔件,其中所述侧壁间隔件形成有多个经圆化的侧壁。移除所述刻蚀停止层的一部分以形成暴露出所述内连结构的第二开口。形成接垫或重布线层,所述接垫或重布线层与所述多个经圆化的侧壁、所述钝化层的上表面及所述内连结构接触。
根据一些实施例,所述的方法中,形成所述接垫包括:在所述钝化层上形成导电层且为所述第二开口加衬;在所述导电层上形成掩模层;在所述掩模层设置在所述导电层上的情况下,刻蚀所述导电层以形成所述接垫;以及将所述掩模层暴露于剥离剂以从所述接垫移除所述掩模层。根据一些实施例,所述的方法中,所述第二开口是由所述刻蚀停止层的相对的内侧壁及所述侧壁间隔件的所述多个经圆化的侧壁界定;且所述刻蚀停止层的所述相对的内侧壁设置在所述钝化层的所述相对的内侧壁之间。
上述内容概述了数个实施例的特征,以使所属领域的技术人员可更好地理解本公开的各方面。所属领域的技术人员应了解,其可容易地使用本公开作为设计或修改其他工艺及结构以实现与本文中所介绍的实施例相同的目的及/或达成相同的优势的基础。所属领域的技术人员还应意识到这些等效构造并不背离本公开的精神及范围,且其可在不背离本公开的精神及范围的情况下在本文中做出各种变化、代替及变动。
Claims (10)
1.一种集成芯片,包括:
半导体衬底;
金属化结构,设置在所述半导体衬底之上,所述金属化结构包括设置在层间介电结构中的内连结构;
钝化层,设置在所述金属化结构之上,其中所述内连结构的上表面至少部分地设置在所述钝化层的相对的内侧壁之间;
侧壁间隔件,沿着所述钝化层的所述相对的内侧壁设置,所述侧壁间隔件具有多个经圆化的侧壁;以及
导电结构,设置在所述钝化层、所述侧壁间隔件的所述多个经圆化的侧壁及所述内连结构的所述上表面上,其中所述导电结构是接垫及/或重布线层。
2.根据权利要求1所述的集成芯片,其中所述导电结构的第一上表面设置在所述钝化层的所述相对的内侧壁之间且设置在所述钝化层的上表面之下。
3.根据权利要求2所述的集成芯片,其中所述导电结构包括经圆化的侧壁,所述侧壁从所述导电结构的所述第一上表面延伸到所述导电结构的第二上表面,且其中所述导电结构的所述第二上表面设置在所述钝化层的所述上表面之上且横向延伸超过所述钝化层的所述相对的内侧壁中的一者。
4.根据权利要求1所述的集成芯片,还包括:
刻蚀停止层,设置在所述钝化层与所述金属化结构之间,其中所述导电结构设置在所述刻蚀停止层的相对的内侧壁上。
5.一种集成芯片,包括:
半导体衬底;
金属化结构,设置在所述半导体衬底之上,所述金属化结构包括设置在层间介电结构中的内连结构;
刻蚀停止层,设置在所述金属化结构上,其中所述内连结构包括最上部导电元件,所述最上部导电元件至少部分地设置在所述刻蚀停止层的相对的内侧壁之间;
钝化层,设置在所述刻蚀停止层上,所述钝化层包括相对的内侧壁,所述相对的内侧壁从所述刻蚀停止层的上表面延伸到所述钝化层的上表面;
侧壁间隔件,设置在所述刻蚀停止层上且沿着所述钝化层的所述相对的内侧壁设置,其中所述侧壁间隔件具有面向彼此的多个经圆化的侧壁;以及
导电结构,设置在所述最上部导电元件、所述刻蚀停止层的所述相对的内侧壁、所述侧壁间隔件的所述多个经圆化的侧壁及所述钝化层的所述上表面上。
6.根据权利要求5所述的集成芯片,其中:
所述内连结构包含第一导电材料;且
所述导电结构包含与所述第一导电材料不同的第二导电材料。
7.根据权利要求5所述的集成芯片,其中:
所述侧壁间隔件的厚度是所述钝化层的高度的至少约40%。
8.根据权利要求5所述的集成芯片,还包括:
半导体装置,设置在所述半导体衬底上,其中所述内连结构将所述半导体装置电耦合到所述导电结构;以及
输入/输出结构,设置在所述导电结构上,其中所述输入/输出结构被配置成将所述导电结构电耦合到外部电路系统。
9.一种形成集成芯片的方法,包括:
在半导体衬底之上形成金属化结构且在所述半导体衬底上形成半导体装置,所述金属化结构包括设置在层间介电结构中的内连结构;
在所述金属化结构之上形成刻蚀停止层;
在所述刻蚀停止层上形成介电层;
移除所述介电层的一部分以形成钝化层,其中所述钝化层的相对的内侧壁界定第一开口;
在所述刻蚀停止层上且沿着所述钝化层的所述相对的内侧壁形成侧壁间隔件,其中所述侧壁间隔件形成有多个经圆化的侧壁;
移除所述刻蚀停止层的一部分以形成暴露出所述内连结构的第二开口;以及
形成接垫或重布线层,所述接垫或所述重布线层与所述多个经圆化的侧壁、所述钝化层的上表面及所述内连结构接触。
10.根据权利要求9所述的方法,其中形成所述接垫包括:
在所述钝化层上形成导电层且为所述第二开口加衬;
在所述导电层上形成掩模层;
在所述掩模层设置在所述导电层上的情况下,刻蚀所述导电层以形成所述接垫;以及
将所述掩模层暴露于剥离剂以从所述接垫移除所述掩模层。
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6303423B1 (en) * | 1998-12-21 | 2001-10-16 | Megic Corporation | Method for forming high performance system-on-chip using post passivation process |
TW530381B (en) * | 2001-12-03 | 2003-05-01 | United Microelectronics Corp | Method for producing metal damascene |
US6590295B1 (en) * | 2002-06-11 | 2003-07-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Microelectronic device with a spacer redistribution layer via and method of making the same |
US6683002B1 (en) * | 2000-08-10 | 2004-01-27 | Chartered Semiconductor Manufacturing Ltd. | Method to create a copper diffusion deterrent interface |
US20090206479A1 (en) * | 2008-02-15 | 2009-08-20 | Timothy Harrison Daubenspeck | Solder interconnect pads with current spreading layers |
US20120028458A1 (en) * | 2008-03-21 | 2012-02-02 | Cabral Jr Cyril | Alpha particle blocking wire structure and method fabricating same |
CN106252323A (zh) * | 2015-06-12 | 2016-12-21 | 台湾积体电路制造股份有限公司 | 用于集成互补金属氧化物半导体(cmos)图像传感器工艺的平坦焊盘结构 |
CN106816369A (zh) * | 2015-11-30 | 2017-06-09 | 台湾积体电路制造股份有限公司 | 间隔件结构及其制造方法 |
TW201724596A (zh) * | 2015-11-02 | 2017-07-01 | Globalfoundries Sg Pte Ltd | 用於磁阻記憶體之間隔層 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6040243A (en) * | 1999-09-20 | 2000-03-21 | Chartered Semiconductor Manufacturing Ltd. | Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion |
US11476214B2 (en) * | 2018-10-31 | 2022-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sidewall spacer to reduce bond pad necking and/or redistribution layer necking |
US10879200B2 (en) * | 2018-10-31 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sidewall spacer to reduce bond pad necking and/or redistribution layer necking |
-
2019
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Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6303423B1 (en) * | 1998-12-21 | 2001-10-16 | Megic Corporation | Method for forming high performance system-on-chip using post passivation process |
US6683002B1 (en) * | 2000-08-10 | 2004-01-27 | Chartered Semiconductor Manufacturing Ltd. | Method to create a copper diffusion deterrent interface |
TW530381B (en) * | 2001-12-03 | 2003-05-01 | United Microelectronics Corp | Method for producing metal damascene |
US6590295B1 (en) * | 2002-06-11 | 2003-07-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Microelectronic device with a spacer redistribution layer via and method of making the same |
US20090206479A1 (en) * | 2008-02-15 | 2009-08-20 | Timothy Harrison Daubenspeck | Solder interconnect pads with current spreading layers |
US20120028458A1 (en) * | 2008-03-21 | 2012-02-02 | Cabral Jr Cyril | Alpha particle blocking wire structure and method fabricating same |
CN106252323A (zh) * | 2015-06-12 | 2016-12-21 | 台湾积体电路制造股份有限公司 | 用于集成互补金属氧化物半导体(cmos)图像传感器工艺的平坦焊盘结构 |
TW201724596A (zh) * | 2015-11-02 | 2017-07-01 | Globalfoundries Sg Pte Ltd | 用於磁阻記憶體之間隔層 |
CN106816369A (zh) * | 2015-11-30 | 2017-06-09 | 台湾积体电路制造股份有限公司 | 间隔件结构及其制造方法 |
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