CN111115555B - Silicon groove structure for MEMS wafer-level eutectic bonding packaging and preparation method - Google Patents
Silicon groove structure for MEMS wafer-level eutectic bonding packaging and preparation method Download PDFInfo
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- CN111115555B CN111115555B CN201911329252.8A CN201911329252A CN111115555B CN 111115555 B CN111115555 B CN 111115555B CN 201911329252 A CN201911329252 A CN 201911329252A CN 111115555 B CN111115555 B CN 111115555B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
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Abstract
The invention relates to a silicon groove structure for MEMS wafer level eutectic bonding packaging and a preparation method thereof, wherein annular silicon grooves distributed on the inner side and the outer side of a bonding ring on the front surface of a silicon cover plate are anti-overflow silicon grooves, and the width w of the silicon grooves is equal to that of the silicon grooves 1 Width w of bond ring 2 The ratio of R is that R is more than or equal to 1/20 and less than or equal to 1/10; square silicon grooves distributed in the bonding ring are storage silicon grooves, the side length of the square silicon grooves is L, the square silicon grooves are distributed on the bonding ring at equal intervals in the transverse direction and the longitudinal direction, and the distance d and the side length L are 20 mu m less than or equal to d=L less than or equal to w 2 10; the silicon groove structure is filled with overflowed alloy melt in the eutectic bonding process, and a wedge-shaped bonding layer structure is formed after solidification. According to the invention, a deep reactive ion etching technology is adopted, silicon groove structures with isosceles inverted trapezoids are directly etched on two sides and the inside of a bonding ring on the front surface of a silicon cover plate, alloy melt overflowed in the eutectic bonding process is contained through the groove structures, and bonding strength and sealing effect are improved through a wedge-shaped bonding layer structure formed after the alloy melt is solidified.
Description
Technical Field
The invention belongs to the technical field of micro-electromechanical system (MEMS) micromachining, and relates to a silicon groove structure for MEMS wafer-level eutectic bonding packaging and a preparation method thereof.
Background
The essential purpose of a MEMS device package is to serve a set of components with specific functions with minimum size and weight, minimum price and as simple a structure as possible. The MEMS wafer level packaging technology refers to a technology for realizing mechanical and electrical connection among different layers of MEMS chips by taking a silicon wafer as a unit and adopting wafer bonding, film deposition and other technical approaches before separating the single MEMS chips, and realizing independent sealing of the microstructure of each MEMS chip on the wafer. Compared with the device-level packaging, the wafer-level packaging ensures that the movable structure on the chip is not influenced by subsequent procedures such as scribing and the like, improves the yield of the device, and can greatly save the packaging cost and reduce the packaging size. Currently, MEMS wafer level packaging technology has become the dominant packaging technology for MEMS devices.
The wafer level eutectic bonding process has low requirements on the morphology of the bonding surface, good sealing performance and high bonding strength, can form firm bonding on a smaller bonding area, is very suitable for packaging MEMS devices processed by the multi-step process, and has become one of key technologies for realizing high-reliability wafer level airtight packaging. Because the liquid phase alloy of metal-silicon has certain fluidity in the eutectic bonding process, under the action of bonding pressure, the alloy melt can flow into the packaging cavity, and the failure of the electrical connection and mechanical movable parts of the MEMS chip can be caused after solidification, thereby influencing the yield and reliability of the device. In addition, how to ensure that a sufficient bonding strength and good air tightness are achieved with a smaller bonding area budget is also an important challenge for MEMS wafer level eutectic bonding packaging.
Considering the problem of overflow of local alloy melt on a bonding ring in the eutectic bonding process, great influence of high structural liquid-solid interfacial tension on the verticality of the side wall of a silicon groove on the flow of the alloy melt, the mechanical strength of the bonding ring caused by a deep groove structure on the bonding ring and difficulties brought to uniform coating of a mask layer in a subsequent processing link, the silicon groove structure or the preparation method in the prior art is not suitable for MEMS wafer-level eutectic bonding packaging.
Disclosure of Invention
The invention solves the technical problems that: in order to solve the problems that the bonding strength is difficult to be large enough and the good sealing effect is difficult to be realized under the limited bonding area, the silicon groove structure for MEMS wafer-level eutectic bonding packaging and the preparation method are provided, the silicon groove structure with isosceles trapezoid cross sections is directly etched on two sides and the inside of a bonding ring of a device layer, so that the alloy melt overflowed in the eutectic bonding process is contained, and a wedge-shaped bonding layer is formed after the alloy melt is solidified, so that the bonding strength and the sealing effect are improved.
The solution of the invention is as follows: the silicon groove structure with the cross section of isosceles inverted trapezoid is etched on two sides and the inside of a bonding ring on the front face of a silicon cover plate sheet so as to contain alloy melt overflowed in the eutectic bonding process, and the bonding strength and the sealing effect are improved through a wedge-shaped bonding layer structure formed after the alloy melt is solidified.
Compared with the prior art, the invention has the beneficial effects that:
(1) The liquid phase alloy liquid formed in the eutectic bonding process has certain fluidity, and under the action of bonding pressure, the alloy liquid can be filled into the annular anti-overflow silicon grooves at the inner side and the outer side of the bonding ring and the square silicon containing grooves in the bonding ring, so that the device failure caused by the overflow of the reaction liquid into the chamber is avoided;
(2) The wedge-shaped bonding layer formed by solidifying the alloy liquid filled in the silicon groove can effectively improve bonding strength and sealing effect;
(3) The non-vertical silicon groove side wall structure reduces the surface liquid/solid phase interfacial tension of the silicon groove structure with high depth-to-width ratio, promotes the fluidity of photoresist and alloy melt, avoids the phenomena of bubble and uneven thickness of photoresist coating in the subsequent device structure processing process, and avoids the bonding layer cavity caused by uneven coverage of alloy melt in the bonding process.
Drawings
FIG. 1 is a top view of a silicon cover plate with an array of silicon trench structured bonding rings in accordance with the present invention;
FIG. 2 is a flow chart of the etching process of the silicon trench structure of the invention;
FIG. 3 is a diagram of an etch mask for a silicon trench structure on a bond ring in accordance with the present invention;
FIG. 4 is a schematic cross-sectional view of a silicon trench structure on a bond ring in accordance with the present invention;
FIG. 5 is a schematic cross-sectional view of a wedge-shaped bonding layer structure according to the present invention.
Detailed Description
The invention is further illustrated below with reference to examples.
The invention provides a silicon groove structure for MEMS wafer-level eutectic bonding encapsulation and a preparation method thereof, wherein the bonding encapsulation structure comprises the following components: a silicon cover sheet and a silicon substrate sheet; the front surface of the silicon cover plate sheet comprises a bonding ring structure, and the front surface of the silicon substrate sheet comprises a metal solder ring structure; when in bonding, the metal solder ring on the silicon substrate sheet falls onto the bonding ring on the cover sheet, and the two silicon wafers are bonded together through metal and Si eutectic bonding. Silicon groove structures with isosceles inverted trapezoids are etched on two sides and the inside of the bonding ring on the front surface of the silicon cover plate, the silicon groove structures distributed on two sides of the bonding ring are annular, and the silicon groove structures distributed inside the bonding ring are square. A top view of a silicon cover plate with an array of silicon trench structured bond rings is shown in fig. 1.
The depth h of the silicon groove structure is more than or equal to 1.5 mu m and less than or equal to 2.5 mu m, and the included angle theta between the side wall of the silicon groove and the vertical direction is more than or equal to 5 degrees and less than or equal to 20 degrees;
the annular silicon grooves distributed on the inner side and the outer side of the bonding ring on the front surface of the silicon cover plate are anti-overflow silicon grooves, and the width w of the silicon grooves 1 Width w of bond ring 2 The ratio of R is that R is more than or equal to 1/20 and less than or equal to 1/10; square silicon grooves distributed in the bonding ring are storage silicon grooves, the side length of the square silicon grooves is L, the square silicon grooves are distributed on the bonding ring at equal intervals in the transverse direction and the longitudinal direction, and the distance d and the side length L are 20 mu m less than or equal to d=L less than or equal to w 2 /10；
The specific processing steps of the silicon groove structure are shown in fig. 2, and include:
(1) Placing the silicon cover plate into SC-1, SC-2 and SC-3 solutions respectively for standard cleaning;
solution SC-1 for standard cleaning of silicon cover plate: NH with volume ratio of 1:1:5 4 OH、H 2 O 2 、H 2 Soaking the mixed solution of O at 70-85 ℃ for 10-30min, taking out, and putting into a cleaning tank for 15-25 times with deionized water;
SC-2: HCl, H in a volume ratio of 1:1:5 2 O 2 、H 2 Soaking the mixed solution of O at 70-85 ℃ for 10-30min, taking out, putting into a cleaning tank, and cleaning with deionized water for 15-25 times;
SC-3H at a volume ratio of 5:1 2 SO 4 、H 2 O 2 Heating to 135-150deg.C, soaking for 10-30min, taking out, cleaning with deionized water for 15-25 times, and spin-drying with a spin dryer.
(2) Processing an etching mask layer on the front surface of the cleaned silicon cover plate piece and patterning the etching mask layer to form an etching window; the etching window comprises an annular anti-overflow silicon groove pattern on the inner side and the outer side of the bonding ring and a square storage silicon groove pattern in the bonding ring. The etching mask is one of photoresist, a dielectric film or a metal film;
if the photoresist is used as a mask, the thickness of the photoresist is 1.5-1.7 mu m;
if the dielectric film is used as a mask, controlling the thickness of the dielectric film to be 0.3-0.6 mu m, spin-coating photoresist of 1.5-1.7 mu m on the dielectric film, patterning the photoresist and processing the dielectric film by dry etching;
if the metal film is used as a mask, a magnetron sputtering system or an electron beam evaporation device is used for steaming the aluminum film, the thickness of the aluminum film is 0.2-0.4 mu m, photoresist with the thickness of 1.5-1.7 mu m is coated on the aluminum film in a spin mode, the photoresist is patterned, and dry etching is used for processing the aluminum film.
(3) Placing the silicon cover plate sheet subjected to mask layer processing in a deep reaction ion etching machine for silicon groove etching, and processing to the depth required to be etched with the right side facing upwards;
(4) Performing in-situ oxygen cleaning on the silicon cover plate sheet subjected to silicon groove etching to remove passivation layers formed on the side wall and the bottom surface of the silicon groove in the etching process;
(5) Taking out the silicon cover plate piece subjected to oxygen cleaning from the etching machine, removing the residual mask layer on the front surface of the silicon cover plate piece, carrying out standard cleaning on the silicon cover plate piece, and removing the mask layer by using an organic solvent if the mask layer is photoresist; if the mask layer is a dielectric film, HF and NH with volume ratio of 1:6 are utilized 4 F, removing the mixed solution; if the mask layer is a metal film, the metal film layer is removed by using corresponding metal corrosive liquid.
Firstly, the etching mask layer on the front surface of the silicon cover plate can be photoresist, and can also be a dielectric film, a metal film or a composite film layer, and the thickness of the mask layer is determined according to the etching depth and the etching selection ratio of the silicon groove.
The etching mask pattern of the silicon groove structure on the bonding ring is shown in figure 3, and the etching window on the pattern comprises an annular anti-overflow silicon groove pattern on the inner side and the outer side of the bonding ring and a square storage silicon groove pattern in the bonding ring; width w of "annular" anti-overflow silicon trench pattern 1 Width w of bond ring 2 The ratio of R is that R is more than or equal to 1/20 and less than or equal to 1/10; the side length of the square silicon groove containing pattern is L, the square silicon groove containing pattern is transversely and longitudinally distributed on the bonding ring at equal intervals, and the intervals d and L are smaller than or equal to 20 mu m and smaller than or equal to d=L and smaller than or equal to w 2 /10。
Thirdly, the etching process of the silicon groove adopts one-step deep reactive ion etching, etching/passivation is carried out simultaneously, and the control of etching depth is realized by adjusting etching time; maintaining etching gas SF 6 By adjusting the passivation gas C at a constant flow rate 4 F 8 Flow, realizing control of an included angle theta between the side wall of the silicon groove and the vertical direction; the etching depth is controlled to be less than or equal to 1.5 mu m and less than or equal to 2.5 mu m, the included angle theta between the side wall of the silicon groove and the vertical direction is controlled to be less than or equal to 5 degrees and less than or equal to 20 degrees, and the silicon groove structure with the isosceles inverted trapezoid cross section is formed, as shown in figure 4.
Fourth, when the mask layer is photoresist, removing by using an organic solvent; when the mask layer is a dielectric film, removing by using a dielectric film corrosive liquid; when the mask layer is a metal film, the corresponding metal corrosive liquid is adopted for removal.
Fifthly, the etched silicon groove structure is filled with overflowed alloy melt in the eutectic bonding process, and a wedge-shaped bonding layer structure is formed after solidification, as shown in fig. 5.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.
Claims (5)
1. A preparation method of a silicon groove structure for MEMS wafer-level eutectic bonding encapsulation is characterized in that the bonding encapsulation structure comprises the following steps: the front surface of the silicon cover plate comprises a bonding ring structure, and the front surface of the silicon substrate comprises a metal solder ring structure; when in bonding, a metal solder ring on the silicon substrate sheet falls into a bonding ring on the silicon cover sheet, and two silicon wafers are bonded together through metal and Si eutectic bonding;
etching silicon groove structures with isosceles inverted trapezoids in cross section on two sides and inside of a bonding ring on the front surface of a silicon cover plate, wherein the silicon groove structures distributed on two sides of the bonding ring are annular, and the silicon groove structures distributed inside the bonding ring are square;
depth of the silicon groove structurehSatisfy 1.5μm≤hThe included angle between the side wall of the silicon groove and the vertical direction is less than or equal to 2.5 mu mθMeets the condition of less than or equal to 5 percentθ≤20˚；
The annular silicon grooves distributed on the inner side and the outer side of the bonding ring on the front surface of the silicon cover plate are anti-overflow silicon grooves, and the width of the silicon grooves is equal to that of the silicon groovesw 1 Width of bond ringw 2 The ratio is thatRMeets 1/20 or lessRNot more than 1/10; the square silicon grooves distributed in the bonding ring are silicon containing grooves, and the side length of the square silicon grooves isLAre distributed on the bonding ring at equal intervals in the transverse and longitudinal directions, the interval is thatdAnd side lengthLSatisfy 20μm≤d=L≤w 2 /10；
The silicon groove structure is filled with overflowed alloy melt in the eutectic bonding process, and a wedge-shaped bonding layer structure is formed after solidification;
the method comprises the following specific steps:
(1) Placing the silicon cover plate into SC-1, SC-2 and SC-3 solutions respectively for standard cleaning;
(2) Processing an etching mask layer on the front surface of the cleaned silicon cover plate and patterning to form an etching window;
(3) Placing the silicon cover plate sheet subjected to mask layer processing in a deep reaction ion etching machine for silicon groove etching, and processing to the depth required to be etched with the right side facing upwards;
(4) Performing in-situ oxygen cleaning on the silicon cover plate sheet subjected to silicon groove etching to remove passivation layers formed on the side wall and the bottom surface of the silicon groove in the etching process;
(5) Taking out the silicon cover plate sheet after oxygen cleaning from the etching machine, removing the residual mask layer on the front surface of the silicon cover plate sheet, and carrying out standard cleaning on the silicon cover plate sheet;
in step (1), solution SC-1 for standard cleaning of silicon cover plate sheet: NH with volume ratio of 1:1:5 4 OH、H 2 O 2 、H 2 Soaking the mixed solution of O at 70-85 ℃ for 10-30min, taking out, and putting into a cleaning tank for 15-25 times with deionized water;
SC-2: HCl, H in a volume ratio of 1:1:5 2 O 2 、H 2 Soaking the mixed solution of O at 70-85 ℃ for 10-30min, taking out, putting into a cleaning tank, and cleaning with deionized water for 15-25 times;
SC-3H at a volume ratio of 5:1 2 SO 4 、H 2 O 2 Heating to 135-150deg.C, soaking for 10-30min, taking out, cleaning with deionized water for 15-25 times, and spin-drying with a spin dryer;
in the step (2), the etching window comprises an annular anti-overflow silicon groove pattern at the inner side and the outer side of the bonding ring and a square storage silicon groove pattern in the bonding ring;
width of annular anti-overflow silicon groove patternw 1 Width of bond ringw 2 The ratio is thatRMeets 1/20 or lessR≤1/10；
The side length of the square storage silicon groove pattern isLWhich are transversely and longitudinally arranged on the bonding ring at equal intervalsdThe arrangement is carried out,dandLmeets the requirement of 20 mu m or lessd=L≤w 2 /10。
2. The method for preparing a silicon trench structure for MEMS wafer level eutectic bonding encapsulation of claim 1, wherein the method comprises the steps of: in the step (2), the etching mask is one of photoresist, a dielectric film or a metal film.
3. The method for preparing the silicon groove structure for the MEMS wafer-level eutectic bonding package according to claim 2, wherein the method comprises the following steps:
if the photoresist is used as a mask, the thickness of the photoresist is 1.5-1.7 mu m;
if the dielectric film is used as a mask, controlling the thickness of the dielectric film to be 0.3-0.6 mu m, spin-coating photoresist of 1.5-1.7 mu m on the dielectric film, patterning the photoresist and processing the dielectric film by dry etching;
if the metal film is used as a mask, a magnetron sputtering system or an electron beam evaporation device is used for steaming the aluminum film, the thickness of the aluminum film is 0.2-0.4 mu m, photoresist with the thickness of 1.5-1.7 mu m is coated on the aluminum film in a spin mode, the photoresist is patterned, and dry etching is used for processing the aluminum film.
4. A according to claim 1The preparation method of the silicon groove structure for MEMS wafer-level eutectic bonding encapsulation is characterized by comprising the following steps: in the step (3), the deep reactive ion etcher etches the silicon groove in one step, the etching time is 30-60s, and the etching gas SF 6 With passivation gas C 4 F 8 The flow ratio is 4:1-3:2; silicon groove depthhSatisfy 1.5μm≤h≤2.5μm, included angle between side wall of silicon groove and vertical directionθMeets the condition of less than or equal to 5 percentθ≤20˚。
5. The method for preparing a silicon trench structure for MEMS wafer level eutectic bonding encapsulation of claim 1, wherein the method comprises the steps of: in the step (5), after the silicon groove is etched, if the mask layer is photoresist, removing the photoresist by using an organic solvent; if the mask layer is a dielectric film, HF and NH with volume ratio of 1:6 are utilized 4 F, removing the mixed solution; if the mask layer is a metal film, the metal film layer is removed by using corresponding metal corrosive liquid.
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