CN111092124A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN111092124A CN111092124A CN201811233288.1A CN201811233288A CN111092124A CN 111092124 A CN111092124 A CN 111092124A CN 201811233288 A CN201811233288 A CN 201811233288A CN 111092124 A CN111092124 A CN 111092124A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 230000001678 irradiating effect Effects 0.000 claims abstract description 16
- 238000002425 crystallisation Methods 0.000 claims description 18
- 230000008025 crystallization Effects 0.000 claims description 18
- 239000013078 crystal Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 5
- 238000005224 laser annealing Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
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- 238000005286 illumination Methods 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
A semiconductor device and a method of manufacturing the same are disclosed, wherein the semiconductor device includes a semiconductor island region and a semiconductor element. The semiconductor island is located on the first surface of the substrate and includes a crystalline portion formed by irradiating the semiconductor island with a flash lamp through a light-transmitting region of the mask. The semiconductor islands are amorphous or microcrystalline. The channel of the semiconductor element is located within the crystalline portion. By matching the pattern design of the semiconductor island region with the pattern design of the photomask and/or the light modulation layer and irradiating the semiconductor with a flash lamp to crystallize the semiconductor, the uniformity of the crystalline strength can be effectively improved.
Description
Technical Field
The present disclosure relates to manufacturing techniques, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
In order to crystallize a semiconductor, generally, an Excimer Laser Annealing (ELA) process is a technique which is commonly used at present in consideration of an internal temperature of a substrate. However, excimer laser annealing by line scanning (Linear scanning) is limited in the size of laser spot and cannot process a large area at a time, and causes a problem of spot (Mura) generation due to poor uniformity due to unstable power of each laser spot. Therefore, the productivity and the substrate area are difficult to be increased, the production cost is high, and the crystal quality and the grain size are not desirable.
In addition, if a device is to be fabricated by using a semiconductor crystal portion, it is necessary to adjust the adopted process to combine the crystal position and the device position and determine the crystal direction according to the position of the finally fabricated device. This method often causes the crystallization of the device to be difficult to control and the uniformity of the crystal strength is not high.
Disclosure of Invention
In order to improve the uniformity of the crystalline strength of a crystalline portion for fabricating a semiconductor element, the present disclosure provides a semiconductor device including a semiconductor island region and a semiconductor element. The semiconductor island region is located on the first surface of the substrate and includes a crystalline portion formed by irradiating the semiconductor island region with a Flash lamp (Flash lamp) through a light-transmitting (Transparent) region of a mask, wherein the semiconductor island region is in an Amorphous state (Amorphous) or a Micro-crystalline state (Micro-crystal). The channel of the semiconductor element is located within the crystalline portion.
In one embodiment of the present disclosure, wherein the semiconductor island region comprises a first portion and a second portion. The second portion is located within the projection area of the light transmissive area, and the first portion is adjacent to the second portion. The crystallization portion is formed by irradiating the second portion from the first surface through the light-transmitting region by a flash lamp and starting crystallization from a junction of the second portion and the first portion.
In an embodiment of the present disclosure, the light modulation layer and the insulating layer are further included. The light modulation layer is arranged on the first surface of the substrate and is positioned between the substrate and the semiconductor island region. The insulating layer covers the first surface of the substrate and the light adjusting layer, wherein the semiconductor island region is formed on the surface of the insulating layer. The semiconductor island region is located in the projection region of the light transmission region and includes a third portion and a fourth portion. The light adjusting layer corresponds to a third portion adjacent to the fourth portion. The crystalline portion is formed by irradiating a fourth portion from a second surface of the substrate opposite to the first surface through the light-transmitting region by a flash lamp and crystallizing from a junction of the fourth portion and the third portion.
In one embodiment of the present disclosure, the mask further comprises Opaque (Opaque) regions or partially transparent (Semi-transparent) regions.
Another aspect of the present disclosure is to provide a method of manufacturing a semiconductor device, including: a semiconductor island region on a first surface of a substrate is irradiated with a flash lamp and a mask to form a crystalline portion, wherein the semiconductor island region is in an amorphous state or a microcrystalline state, and the crystalline portion corresponds to a light-transmitting region of the mask. The semiconductor element is formed using a crystalline portion, wherein a channel of the semiconductor element is located within the crystalline portion.
In an embodiment of the present disclosure, the method further includes: and irradiating a semiconductor island region from the first surface by using a flash lamp and a photomask, wherein the semiconductor island region comprises a first part and a second part, the second part is positioned in the projection region of the light-transmitting region, and the first part is adjacent to the second part. The second portion is crystallized from a junction of the second portion and the first portion to form a crystallized portion.
In an embodiment of the present disclosure, the method further includes: arranging a light adjusting layer on the first surface of the substrate so as to be positioned between the semiconductor island region and the substrate; an insulating layer is arranged to cover the first surface of the substrate and the light adjusting layer, wherein the semiconductor island region is formed on the surface of the insulating layer; the semiconductor island is irradiated from a second surface of the substrate opposite to the first surface by using the flash lamp and the mask, the semiconductor island is positioned in a projection area of the light-transmitting area and comprises a third part and a fourth part, the light adjusting layer corresponds to the third part, and the third part is adjacent to the fourth part. The fourth portion is crystallized from a junction of the fourth portion and the third portion to form a crystallized portion.
In one embodiment of the present disclosure, the mask further includes an opaque region or a partially transparent region.
In summary, the present disclosure utilizes the pattern design of the semiconductor island region and the pattern design of the mask and/or the light modulation layer, and irradiates with the flash lamp to perform the crystallization of the semiconductor, so as to design the crystallization position and the crystallization direction of the semiconductor device, and effectively improve the uniformity of the crystal strength, and the formed crystal grain size is larger (e.g. micrometer (μm) grade).
The above description will be described in detail by embodiments, and further explanation will be provided for the technical solution of the present disclosure.
Drawings
The foregoing and other objects, features, advantages and embodiments of the disclosure will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 2A is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 2B is a schematic cross-sectional view illustrating a semiconductor device according to one embodiment of the present disclosure;
FIG. 2C is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 3 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present disclosure;
FIG. 5 is a schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 6 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 7A is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 7B is a cross-sectional schematic view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 7C is a cross-sectional schematic view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 8 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present disclosure; and
FIG. 10 is a flow chart illustrating a method of manufacturing according to one embodiment of the present disclosure.
Detailed Description
For a more complete and complete description of the present disclosure, reference is made to the accompanying drawings and the various embodiments described below. The examples provided are not intended to limit the scope of the invention; neither is the order of execution presented to limit the scope of the invention, and any device that results in a similar effect, if any, from a combination of the two or more steps is within the scope of the invention.
In the description and claims, the terms "a" and "an" can refer broadly to the singular or the plural, unless the context specifically states the article. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and similar language, when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term "about", "about" or "approximately about" generally means within about twenty percent, preferably within about ten percent, and more preferably within about five percent of the error or range of the numerical value. Unless otherwise indicated, all numbers recited herein are to be interpreted as approximations, as indicated by the error or range of values expressed as "about," about, "or" approximately about.
Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," are used herein to describe one element's relationship to another element as illustrated in the figures. Relative terms are used to describe different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in a drawing is turned over, elements will be described as being on the "lower" side of other elements as being oriented on "upper" sides of the other elements. The exemplary word "lower" may encompass both an orientation of "lower" and "upper" depending on the particular orientation of the figure.
Fig. 1 is a top view diagram illustrating a semiconductor device 100 according to an embodiment of the disclosure. The semiconductor device 100 includes semiconductor islands (islands) 110, 120, 130 and semiconductor devices (not shown). As shown in fig. 1, the semiconductor islands 110 and 120 are partially located in the projected area 140 of the Transparent (Transparent) area of the mask on the substrate 170, and partially located in the projected area of the Opaque (Opaque) area of the mask on the substrate 170 (the area outside the projected area 140); and the semiconductor island 130 is located entirely within the projected area 140 of the light-transmissive region on the substrate 170. In one embodiment, the semiconductor islands 110, 120, 130 are Amorphous (Amorphous) or Micro-crystalline (Micro-crystalline) formed by Deposition (Deposition) and Patterning (Patterning) processes. The Deposition process includes, but is not limited to, Chemical Vapor Deposition (CVD), sputtering (Sputter), or solution based (solution based) methods.
To illustrate the crystallization process, please refer to fig. 2A-2C, which are schematic cross-sectional views along line AA' of fig. 1. As shown in fig. 2A, the light emitting region of the flash 160 is larger than the light transmissive region 152 of the mask, and the semiconductor island 110 is located on the first surface S1 of the substrate 170 and includes a first portion 111 and a second portion 112, wherein the second portion 112 is located in the projection region 140 of the light transmissive region 152 of the mask on the substrate 170. When a Flash lamp (Flash lamp)160 irradiates the semiconductor device 100 through the mask, light may irradiate the second portion 112 of the semiconductor island 110 through the light-transmitting region 152 of the mask, and thus the second portion 112 becomes molten (Fusion).
In one embodiment, first portion 111 of semiconductor island 110 corresponds to opaque region 151 of the mask, such that first portion 111 is blocked from flash lamp 160 illumination by opaque region 151, while remaining in its original state (i.e., amorphous or microcrystalline). In another embodiment, the opaque region 151 of the mask may be designed as a partially transparent (Semi-transparent) region, and the first portion 111 of the semiconductor island 110 corresponds to the partially transparent region of the mask, so that upon receiving the attenuated flash lamp 160, the lattice of the first portion 111 can be rearranged to have a higher Mobility than the original state. It should be noted that the substrate 170 may also comprise other films or structures of the same or different materials, i.e. the semiconductor islands 110, 120, 130 may be formed on other films or structures of other materials of the substrate, and the present disclosure is not limited to the semiconductor islands 110, 120, 130 being formed directly on the substrate.
As shown in fig. 2B, the flash lamp 160 stops irradiating, and the second portion 112 in a molten state starts crystallizing from the junction J1 of the second portion 112 and the first portion 111 (as indicated by the dotted arrow inside the second portion 112 in fig. 2B), to form the crystallized portion 113 shown in fig. 2C. In one embodiment, the crystalline portion 113 has a Lateral crystallization (Lateral crystallization) characteristic.
After the processes shown in fig. 2A to 2C, a top view of the semiconductor device 100 is shown in fig. 3. Portions of the semiconductor islands corresponding to the projected areas 140 of the light-transmitting areas 152 of the mask are irradiated with a flash lamp 160 and crystallized, thereby forming crystallized portions 113, 123, 133. In one embodiment, since the first portions 111 and 121 of the semiconductor islands 110 and 120 are outside the projection region 140 and are not irradiated to maintain the original state, the second portion 112, which is irradiated by the flash lamp 160 to become molten, is crystallized from the junctions J1 and J2 to form the crystalline portions 113 and 123, respectively, and the crystalline portions 113 and 123 have lateral crystalline characteristics. In another embodiment, since the semiconductor island region 130 is entirely located within the projection region 140, the semiconductor island region 130 is crystallized to form the crystalline portion 133 after being irradiated with the flash lamp 160 to become molten state, and the crystalline portion 133 has a micro-crystalline characteristic.
The crystalline portion produced by the above embodiments may be used to form a semiconductor device. For example, as shown in FIG. 4, the crystallized portion 213 is formed by the crystallization of the second portion (at the same location as the crystallized portion 213) into a molten state from the junction J3 between the second portion and the first portion 211. A channel of a semiconductor element such as a Thin-Film Transistor (TFT) is located in the crystalline portion 213 and between the source electrode 221 and the drain electrode 222. When the semiconductor device is operating, current flows from the source 221 to the drain 222, i.e., in the current direction I. In one embodiment, the current direction I is perpendicular to junction J3. In another embodiment, the semiconductor device may be designed such that the current direction I and the junction J3 are at an angle other than a right angle.
In order to cope with different kinds of semiconductor device designs, the shape of the crystal portion may have different shapes by the pattern design of the semiconductor island and the pattern design of the mask. In one embodiment, as shown in fig. 5, semiconductor island 310 is circular in shape, including a first portion 311 and a second portion 312. The first portion 311 is not irradiated by the flash lamp 160 and remains in its original state (i.e., amorphous or microcrystalline). The second portion 312 is located in the projection region of the light-transmitting region of the mask, and thus is irradiated by the flash lamp 160 and crystallized to form a ring-shaped (doughmut shape) crystal portion.
In this way, the present disclosure utilizes a mask in accordance with the pattern design of the semiconductor island, and performs crystallization of the semiconductor island by flash lamp irradiation. The present disclosure can achieve high uniformity of crystallization compared to excimer laser annealing techniques, thereby improving uniformity of crystalline strength and resulting larger grain sizes (e.g., micrometer (μm) scale). In addition, semiconductor islands can be classified as being completely within the illuminated region (e.g., semiconductor island 130 of fig. 1), partially within the illuminated region (e.g., semiconductor islands 110, 120 of fig. 1), and completely outside the non-illuminated region due to the mask design. Therefore, the crystal characteristics can be judged according to the above classification. For example, as shown in fig. 3, the crystalline region 133 of the semiconductor island region 130 has a microcrystalline characteristic, and the crystalline regions 113 and 123 of the semiconductor island regions 110 and 120 have a lateral crystalline characteristic.
In another embodiment, the flash lamp may also irradiate the semiconductor island region from the back surface of the substrate (i.e., the second surface S2) for crystallization. Fig. 6 is a top view schematic diagram illustrating a semiconductor device 400 according to an embodiment of the present disclosure. The semiconductor device 400 includes semiconductor islands 410, 420, a light adjusting layer 430, and semiconductor elements (not shown). As shown in fig. 6, the semiconductor island 410 is only partially located in the projected area 440 of the light-transmissive region 152 of the mask on the semiconductor device 400, and the semiconductor island 420 is completely located in the projected area 440 of the light-transmissive region 152. In one embodiment, the semiconductor islands 410, 420 are amorphous or microcrystalline and are formed by a deposition process and a patterning process.
For explaining the crystallization process, please refer to fig. 7A to 7C, which are schematic cross-sectional views along the line BB' of fig. 6. As shown in fig. 7A, the flash 160 is irradiated from the second face S2 of the substrate 470, and the light emitting region of the flash 160 is larger than the light transmitting region 152 of the reticle. The light adjusting layer 430 is disposed on the first surface S1 of the substrate 470, the insulating layer 480 covers the first surface S1 of the substrate 470 and the light adjusting layer 430, and the semiconductor island 420 is formed on the surface of the insulating layer 480 and includes a third portion 421 and a fourth portion 422. When the flash 160 irradiates the semiconductor device 400 through the mask from the second side S2 opposite to the first side S1 of the substrate 470, light may irradiate the light adjusting layer 430 and the semiconductor island 420 through the light-transmitting region 152 of the mask. Since the light adjusting layer 430 functions as a light reflecting layer, a light absorbing layer or a light attenuating layer, the light adjusting layer 430 can completely block the flash lamp 160 from irradiating the third portion 421 of the semiconductor island region 420, and the third portion 421 can maintain its original state (i.e., an amorphous state or a microcrystalline state). The fourth portion 422, which is not blocked by the light adjusting layer 430, becomes molten due to the irradiation of the flash lamp 160. In another embodiment, the light conditioning layer 430 attenuates the radiation of the third portion 421 from the flash lamp 160, so that the lattice of the third portion 421 can be rearranged to have a higher mobility than the original state.
As shown in fig. 7B, the flash lamp 160 stops irradiating, and the fourth portion 422 in a molten state starts crystallizing from a junction J4 between the fourth portion 422 and the third portion 421 (as indicated by a dotted arrow in the fourth portion 422 in fig. 7B), to form a crystallized portion 423 shown in fig. 7C. In one embodiment, the crystalline portion 423 has a lateral crystalline characteristic.
After the processes shown in fig. 7A to 7C, a top view of the semiconductor device 400 is shown in fig. 8. Portions of the semiconductor island region corresponding to the projection region 440 of the light-transmitting region 152 of the mask and not blocked by the light modulation layer 430 are irradiated with the flash lamp 160 and crystallized, thereby forming the crystalline portions 413, 423. In one embodiment, since the first portion 411 of the semiconductor island region 410 is located outside the projection region 440 and the third portion 421 of the semiconductor island region 430 is blocked by the photo-adjusting layer 430 and is not irradiated by the flash lamp 160 to maintain the original state, the second portions 412 and 422 irradiated by the flash lamp 160 to become molten state are crystallized from the junctions J4 and J5 to form the crystalline portions 413 and 423, respectively, and the crystalline portions 413 and 423 have lateral crystalline characteristics.
The crystal portion 423 manufactured by the above embodiment can be used to form a semiconductor element. For example, as shown in fig. 9, channels of semiconductor devices (e.g., thin film transistor inverters (inverters)) are located in the crystalline portion 423 and between the source 521 and the drain 522, and between the drain 522 and the source 523, respectively. When the semiconductor device is operating, a current flows from the source 521 to the other source 523 through the drain 522, i.e., the current direction I. In one embodiment, the current direction I is perpendicular to junction J4. In another embodiment, the semiconductor device may be designed such that the current direction I and the junction J4 are at an angle other than a right angle.
As such, the semiconductor device 400 of the present disclosure may utilize the design of the light adjusting layer 421 to block the flash lamp from irradiating a portion (e.g., the third portion 421) of the semiconductor island from the second side S2 of the substrate, while the other portion (e.g., the fourth portion 422) not blocked by the light adjusting layer 421 is irradiated by the flash lamp to become molten state, and starts crystallization from the molten state portion and the junction J4 not changed to the molten state to form the crystalline portion 423.
In another embodiment, the semiconductor islands 110-130, 410, 420 may be crystallized covered with an insulating layer (not shown) according to the actual design requirements.
FIG. 10 is a flow chart illustrating a method 1000 of manufacturing in accordance with one embodiment of the present disclosure. The manufacturing method 1000 has a plurality of steps S1002 to S1004, and is applicable to the semiconductor devices 100 and 400 described in fig. 1 to 3 and 6 to 8. It should be understood by those skilled in the art that the steps mentioned in the present embodiment, except for those specifically mentioned in the sequence, can be performed in any order, even simultaneously or partially simultaneously, according to the actual requirement. The specific implementation is as disclosed above, and will not be repeated here.
In step S1002, a semiconductor island region on the first surface of the substrate is irradiated with a flash lamp and a mask to form a crystalline portion, wherein the semiconductor island region is in an amorphous state or a microcrystalline state, and the crystalline portion corresponds to a light-transmitting region of the mask.
In step S1004, a semiconductor device is formed using the crystalline portion, wherein a channel of the semiconductor device is located in the crystalline portion.
Through the embodiments, the present disclosure can design the crystallization position and the crystallization direction of the semiconductor device by using the pattern design of the semiconductor island region and the pattern design of the mask and/or the light modulation layer and irradiating the semiconductor with the flash lamp to crystallize the semiconductor, thereby effectively improving the uniformity of the crystal strength and forming the crystal grains with larger sizes (e.g., micrometer (μm) grade).
Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure, and therefore the scope of the present disclosure should be limited only by the terms of the appended claims.
Claims (8)
1. A method of manufacturing a semiconductor device, comprising:
irradiating a semiconductor island region on a first surface of a substrate with a flash lamp and a photomask to form a crystalline portion, wherein the semiconductor island region is in an amorphous state or a microcrystalline state, and the crystalline portion corresponds to a light-transmitting region of the photomask; and
a semiconductor device is formed using the crystalline portion, wherein a channel of the semiconductor device is located within the crystalline portion.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising:
irradiating the semiconductor island region from the first surface by using the flash lamp and the mask, wherein the semiconductor island region comprises a first portion and a second portion, the second portion is located in a projection region of the light-transmitting region, and the first portion is adjacent to the second portion; and
the second portion is crystallized from a junction of the second portion and the first portion to form the crystallized portion.
3. The method for manufacturing a semiconductor device according to claim 1, further comprising:
disposing a light-adjusting layer on the first surface of the substrate so as to be located between the semiconductor island and the substrate;
an insulating layer is arranged to cover the first surface of the substrate and the light adjusting layer, wherein the semiconductor island region is formed on the surface of the insulating layer;
irradiating the semiconductor island region from a second surface of the substrate opposite to the first surface by using the flash lamp and the photomask, wherein the semiconductor island region is positioned in a projection region of the light-transmitting region and comprises a third part and a fourth part, the light adjusting layer corresponds to the third part, and the third part is adjacent to the fourth part; and
the fourth portion is crystallized from a junction of the fourth portion and the third portion to form the crystallized portion.
4. The method of claim 1, wherein the mask further comprises an opaque region or a portion of a transparent region.
5. A semiconductor device, comprising:
a semiconductor island region on a first surface of a substrate and including a crystalline portion formed by irradiating the semiconductor island region with a flash lamp through a light-transmitting region of a mask, wherein the semiconductor island region is in an amorphous state or a microcrystalline state; and
a semiconductor device, wherein a channel of the semiconductor device is located in the crystalline portion.
6. The semiconductor device according to claim 5, wherein the semiconductor island region comprises a first portion and a second portion, the second portion being located within a projected area of the light-transmitting region, the first portion being adjacent to the second portion; the crystallization part is formed by irradiating the second part from the first surface through the transparent region by the flash lamp, and crystallizing the second part from a junction of the second part and the first part.
7. The semiconductor device according to claim 5, further comprising:
a light adjusting layer disposed on the first surface of the substrate and located between the substrate and the semiconductor island; and
an insulating layer covering the first surface of the substrate and the light adjusting layer, wherein the semiconductor island region is formed on the surface of the insulating layer;
wherein the semiconductor island region is located in a projection region of the light-transmitting region and comprises a third portion and a fourth portion; the light adjusting layer corresponds to the third portion, the third portion being adjacent to the fourth portion; the fourth portion is irradiated from a second surface of the substrate opposite to the first surface through the transparent region by the flash lamp, and is crystallized from a junction between the fourth portion and the third portion.
8. The semiconductor device of claim 5, wherein the mask further comprises an opaque region or a partially transparent region.
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| CN201811233288.1A CN111092124A (en) | 2018-10-23 | 2018-10-23 | Semiconductor device and method for manufacturing the same |
| TW108207258U TWM585988U (en) | 2018-10-23 | 2019-06-06 | Semiconductor device |
| TW108119782A TWI704697B (en) | 2018-10-23 | 2019-06-06 | Semiconductor device and manufacturing method for the same |
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| CN111092124A (en) * | 2018-10-23 | 2020-05-01 | 宸鸿光电科技股份有限公司 | Semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003168646A (en) * | 2001-12-04 | 2003-06-13 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
| CN1728334A (en) * | 2004-07-28 | 2006-02-01 | 株式会社液晶先端技术开发中心 | Method of manufacturing semiconductor device |
| US20060186415A1 (en) * | 2005-02-24 | 2006-08-24 | Akihiko Asano | Thin film semiconductor device, method of manufacturing the same, and display |
| CN106898540A (en) * | 2015-12-17 | 2017-06-27 | 宸鸿光电科技股份有限公司 | Semiconductor making method and semiconductor layer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005029547A2 (en) * | 2003-09-16 | 2005-03-31 | The Trustees Of Columbia University In The City Of New York | Enhancing the width of polycrystalline grains with mask |
| WO2009111340A2 (en) * | 2008-02-29 | 2009-09-11 | The Trustees Of Columbia University In The City Of New York | Flash lamp annealing crystallization for large area thin films |
| CN111092124A (en) * | 2018-10-23 | 2020-05-01 | 宸鸿光电科技股份有限公司 | Semiconductor device and method for manufacturing the same |
-
2018
- 2018-10-23 CN CN201811233288.1A patent/CN111092124A/en not_active Withdrawn
-
2019
- 2019-06-06 TW TW108119782A patent/TWI704697B/en active
- 2019-06-06 TW TW108207258U patent/TWM585988U/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003168646A (en) * | 2001-12-04 | 2003-06-13 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
| CN1728334A (en) * | 2004-07-28 | 2006-02-01 | 株式会社液晶先端技术开发中心 | Method of manufacturing semiconductor device |
| US20060186415A1 (en) * | 2005-02-24 | 2006-08-24 | Akihiko Asano | Thin film semiconductor device, method of manufacturing the same, and display |
| CN106898540A (en) * | 2015-12-17 | 2017-06-27 | 宸鸿光电科技股份有限公司 | Semiconductor making method and semiconductor layer |
Also Published As
| Publication number | Publication date |
|---|---|
| TWM585988U (en) | 2019-11-01 |
| TW202017202A (en) | 2020-05-01 |
| TWI704697B (en) | 2020-09-11 |
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