TWM585988U - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWM585988U
TWM585988U TW108207258U TW108207258U TWM585988U TW M585988 U TWM585988 U TW M585988U TW 108207258 U TW108207258 U TW 108207258U TW 108207258 U TW108207258 U TW 108207258U TW M585988 U TWM585988 U TW M585988U
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Taiwan
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semiconductor
light
semiconductor device
area
semiconductor island
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TW108207258U
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Chinese (zh)
Inventor
林建宏
劉振宇
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宸鴻光電科技股份有限公司
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Publication of TWM585988U publication Critical patent/TWM585988U/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor device is disclosed herein, in which the semiconductor device includes a semiconductor island and a semiconductor component. The semiconductor island is located on a first side of a substrate, and includes a crystal part. The crystal part is formed from the semiconductor island that is irradiated by a flash lamp through a transparent region of a mask. The semiconductor island is in amorphous state or micro-crystal state. A channel of the semiconductor component is located in the crystal part.

Description

半導體裝置 Semiconductor device

本揭示內容是關於一種電子裝置,且特別是關於一種半導體裝置。 The present disclosure relates to an electronic device, and more particularly to a semiconductor device.

為了結晶化半導體,一般而言考慮到基板的內受溫度,準分子雷射退火(Excimer Laser Annealing,ELA)的製程是目前較常採用的技術。然而,線掃描(Linear scanning)的準分子雷射退火受限於雷射光點的尺寸而無法一次處理大面積的區域,並且由於每一個雷射光點的功率不穩定,造成均勻性不佳而容易產生斑(Mura)的問題。因此,產能與基板的面積難以提高,生產成本居高不下之外,結晶品質與晶粒尺寸亦不理想。 In order to crystallize a semiconductor, in general, considering the internal temperature of the substrate, an Excimer Laser Annealing (ELA) process is a more commonly used technology at present. However, linear scanning excimer laser annealing is limited by the size of the laser light spot and cannot handle a large area at one time, and because the power of each laser light spot is unstable, the uniformity is poor and easy. The problem of mura is generated. Therefore, it is difficult to increase the production capacity and the area of the substrate. Besides the high production cost, the crystal quality and grain size are also not ideal.

此外,若欲利用半導體結晶部分製作元件,則需要根據最終製作完成的元件的位置,調整所採用的製程以結合結晶位置與元件位置,並決定結晶方向。此種方式常造成元件結晶化情形難以掌握,以及結晶強度一致性不高的現象。 In addition, if a semiconductor crystal portion is to be used to fabricate an element, the process used to adjust the combination of the crystal position and the element position and determine the crystal direction need to be adjusted according to the position of the final fabricated element. This method often makes it difficult to grasp the crystallization situation of the device, and the phenomenon of low consistency in crystallization strength.

為了提高用於製作半導體元件的結晶部分的結晶強度一致性,本揭示內容是提供一種半導體裝置,其包含半導體島區與半導體元件。半導體島區位於基板之第一面上,並包含結晶部分,其係由閃光燈(Flash lamp)透過光罩之透光(Transparent)區域照射半導體島區所形成,其中半導體島區為非晶態(Amorphous)或微結晶態(Micro-crystal)。半導體元件之通道位於結晶部分內。 In order to improve the consistency of the crystalline strength of the crystalline portion used to fabricate a semiconductor device, the present disclosure is to provide a semiconductor device including a semiconductor island region and a semiconductor device. The semiconductor island region is located on the first surface of the substrate and includes a crystalline portion. The semiconductor island region is formed by a flash lamp illuminating the semiconductor island region through the transparent region of the photomask. Amorphous) or Micro-crystal. The channel of the semiconductor element is located in the crystalline portion.

於本揭示內容之一實施例中,其中半導體島區包含第一部分與第二部分。第二部分位於透光區域之投影區域內,第一部分鄰近第二部分。結晶部分係由閃光燈從第一面透過透光區域照射第二部分,並從第二部分與第一部分之接面開始結晶化所形成。 In one embodiment of the present disclosure, the semiconductor island region includes a first portion and a second portion. The second part is located in the projection area of the light transmitting area, and the first part is adjacent to the second part. The crystalline part is formed by the flash lamp illuminating the second part through the light-transmitting area from the first side, and crystallization starts from the interface between the second part and the first part.

於本揭示內容之一實施例中,更包含光調節層以及絕緣層。光調節層設置於基板的第一面,以位於基板與半導體島區之間。絕緣層覆蓋於基板的第一面及光調節層,其中半導體島區形成於絕緣層的表面上。半導體島區位於透光區域之投影區域內,並包含第三部分與第四部分。光調節層對應於第三部分,第三部分鄰近第四部分。結晶部分係由閃光燈從基板之相對於第一面的第二面透過透光區域照射第四部分,並從第四部份與第三部分之接面開始結晶化所形成。 In one embodiment of the present disclosure, it further includes a light adjustment layer and an insulating layer. The light adjustment layer is disposed on the first surface of the substrate so as to be located between the substrate and the semiconductor island region. The insulating layer covers the first surface of the substrate and the light adjustment layer, and a semiconductor island region is formed on a surface of the insulating layer. The semiconductor island region is located in a projection region of the light transmitting region, and includes a third part and a fourth part. The light-regulating layer corresponds to the third portion, and the third portion is adjacent to the fourth portion. The crystalline part is formed by the flash unit illuminating the fourth part through the light-transmitting area from the second side of the substrate opposite to the first side, and starting to crystallize from the interface between the fourth part and the third part.

於本揭示內容之一實施例中,其中光罩更包含不透光(Opaque)區域或部分透光(Semi-transparent)區域。 In one embodiment of the present disclosure, the photomask further includes an opaque area or a semi-transparent area.

綜上所述,本揭示內容係利用半導體島區的圖案設計配合光罩且/或光調節層的圖案設計,並以閃光燈照射以進行半導體的結晶化,可設計半導體元件的結晶位置與結晶方向,亦有效地提高結晶強度的一致性,並且所形成的晶粒尺寸較大(例如微米(μm)等級)。 In summary, the present disclosure uses the pattern design of the semiconductor island area in combination with the pattern design of the photomask and / or the light adjustment layer, and irradiates with a flash to crystallize the semiconductor. The crystal position and direction of the semiconductor element can be designed. It also effectively improves the consistency of crystalline strength, and the formed crystal grain size is large (such as micrometer (μm) grade).

以下將以實施方式對上述之說明作詳細的描述,並對本揭示內容之技術方案提供更進一步的解釋。 The above description will be described in detail in the following embodiments, and the technical solution of the present disclosure will be further explained.

為讓本揭示內容之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附符號之說明如下: In order to make the above and other objects, features, advantages, and embodiments of the present disclosure more comprehensible, the description of the attached symbols is as follows:

100、400‧‧‧半導體裝置 100, 400‧‧‧ semiconductor devices

110、120、130、310、410、420‧‧‧半導體島區 110, 120, 130, 310, 410, 420‧‧‧ Semiconductor Island

111、121、211、311‧‧‧第一部分 111, 121, 211, 311‧‧‧ Part I

112、312‧‧‧第二部分 112, 312‧‧‧ Part II

113、123、133、213‧‧‧結晶部分 113, 123, 133, 213‧‧‧ Crystallized part

140、440‧‧‧投影區域 140, 440‧‧‧ projection area

151‧‧‧光罩的不透光區域 151‧‧‧ Opaque area of the mask

152‧‧‧光罩的透光區域 152‧‧‧ Translucent area of the mask

AA’、BB’‧‧‧線段 AA ’, BB’‧‧‧ line segments

170、470‧‧‧基板 170, 470‧‧‧ substrate

S1‧‧‧第一面 S1‧‧‧First side

J1、J2、J3、J4、J5‧‧‧接面 J1, J2, J3, J4, J5 ‧‧‧ meet

I‧‧‧電流方向 I‧‧‧ Current direction

221、521、523‧‧‧源極 221, 521, 523‧‧‧ source

222、522‧‧‧汲極 222, 522‧‧‧ Drain

411、421‧‧‧第三部分 411, 421‧‧‧ Part III

422‧‧‧第四部份 422‧‧‧Part 4

413、423‧‧‧結晶部分 413, 423‧‧‧‧Crystalline part

430‧‧‧光調節層 430‧‧‧light adjustment layer

480‧‧‧絕緣層 480‧‧‧ Insulation

S2‧‧‧第二面 S2‧‧‧Second Side

1000‧‧‧製造方法 1000‧‧‧Manufacturing method

S1002~S1004‧‧‧步驟 S1002 ~ S1004‧‧‧step

為讓本揭示內容之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖示之說明如下:第1圖係說明本揭示內容一實施例之半導體裝置之上視示意圖;第2A圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第2B圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第2C圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第3圖係說明本揭示內容一實施例之半導體裝置之上視示意圖;第4圖係說明本揭示內容一實施例之半導體元件示意圖; 第5圖係說明本揭示內容一實施例之半導體元件示意圖;第6圖係說明本揭示內容一實施例之半導體裝置之上視示意圖;第7A圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第7B圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第7C圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第8圖係說明本揭示內容一實施例之半導體裝置之上視示意圖;第9圖係說明本揭示內容一實施例之半導體元件示意圖;以及第10圖係說明本揭示內容一實施例之製造方法流程圖。 In order to make the above and other objects, features, advantages, and embodiments of the present disclosure more comprehensible, the accompanying drawings are described as follows: FIG. 1 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure; FIG. 2A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure; FIG. 2B is a cross-sectional schematic view of a semiconductor device according to an embodiment of the present disclosure; FIG. 2C is a semiconductor device illustrating an embodiment of the present disclosure; 3 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure; FIG. 4 is a schematic view illustrating a semiconductor device according to an embodiment of the present disclosure; FIG. 5 is a schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure; FIG. 6 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure; FIG. 7A is a schematic view illustrating a semiconductor device according to an embodiment of the present disclosure; 7B is a schematic cross-sectional view of a semiconductor device illustrating an embodiment of the present disclosure; FIG. 7C is a schematic cross-sectional view of a semiconductor device illustrating an embodiment of the present disclosure; FIG. 8 is a schematic view illustrating an embodiment of the present disclosure FIG. 9 is a schematic top view of a semiconductor device; FIG. 9 is a schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure; and FIG. 10 is a flowchart illustrating a manufacturing method of an embodiment of the present disclosure.

為了使本揭示內容之敘述更加詳盡與完備,可參照附圖及以下所述之各種實施例。但所提供之實施例並非用以限制本新型所涵蓋的範圍;步驟的描述亦非用以限制其執行之順序,任何由重新組合,所產生具有均等功效的裝置,皆為本新型所涵蓋的範圍。 In order to make the description of this disclosure more detailed and complete, reference may be made to the drawings and various embodiments described below. However, the examples provided are not used to limit the scope covered by the new model; the description of the steps is not used to limit the order of its implementation. Any device that is recombined to have an equal effect is covered by the new model. range.

於實施方式與申請專利範圍中,除非內文中對 於冠詞有所特別限定,否則「一」與「該」可泛指單一個或複數個。將進一步理解的是,本文中所使用之「包含」、「包括」、「具有」及相似詞彙,指明其所記載的特徵、區域、整數、步驟、操作、元件與/或組件,但不排除其所述或額外的其一個或多個其它特徵、區域、整數、步驟、操作、元件、組件,與/或其中之群組。 Within the scope of the embodiments and patent applications, There is a special limitation on the article, otherwise "a" and "the" can refer to a single or plural. It will be further understood that the terms "including", "including", "having" and similar terms used in this document indicate the features, regions, integers, steps, operations, elements and / or components recorded therein, but do not exclude It describes or additionally one or more of its other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

關於本文中所使用之「約」、「大約」或「大致約」一般通常係指數值之誤差或範圍約百分之二十以內,較好地是約百分之十以內,而更佳地則是約百分五之以內。文中若無明確說明,其所提及的數值皆視作為近似值,即如「約」、「大約」或「大致約」所表示的誤差或範圍。 About "about", "approximately" or "approximately about" as used herein is generally an error or range of the index value within about 20%, preferably within about 10%, and more preferably It is within about five percent. Unless explicitly stated in the text, the numerical values mentioned are regarded as approximate values, that is, errors or ranges indicated by "about", "about" or "approximately about".

此外,相對詞彙,如「下」或「底部」與「上」或「頂部」,用來描述文中在附圖中所示的一元件與另一元件之關係。相對詞彙是用來描述裝置在附圖中所描述之外的不同方位是可以被理解的。例如,如果一附圖中的裝置被翻轉,元件將會被描述原為位於其它元件之「下」側將被定向為位於其他元件之「上」側。例示性的詞彙「下」,根據附圖的特定方位可以包含「下」和「上」兩種方位。 In addition, relative terms such as "lower" or "bottom" and "upper" or "top" are used to describe the relationship between one element and another element shown in the drawings in the text. Relative vocabulary is used to describe different orientations of the device beyond those described in the drawings. It is understandable. For example, if the device in a figure is turned over, the elements would be described as being on the "lower" side of other elements and would be oriented on the "upper" side of the other elements. The exemplary word "down" may include two directions "down" and "up" according to the specific orientation of the drawing.

第1圖係說明本揭示內容一實施例之半導體裝置100之上視示意圖。半導體裝置100包含半導體島區(Island)110、120、130與半導體元件(未繪示)。如第1圖所示,半導體島區110、120是有一部分位於光罩的透光(Transparent)區域在基板170上的投影區域140內,而有另一部分是位於光罩的不透光(Opaque)區域在基板 170上的投影區域(投影區域140以外的區域);而半導體島區130是完全位於透光區域在基板170上的投影區域140內。於一實施例中,半導體島區110、120、130為未結晶態(Amorphous)或微結晶態(Micro-crystal),其係經過沉積(Deposition)製程與圖案化(Patterning)製程而形成。沉積製程包含但不限於化學氣相沉積(Chemical Vapor Deposition,CVD)、濺鍍(Sputter)或應用溶液(Solution based)的方法。 FIG. 1 is a schematic top view illustrating a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes semiconductor islands 110, 120, and 130 and a semiconductor device (not shown). As shown in FIG. 1, the semiconductor island regions 110 and 120 are partially located in the projection area 140 of the transparent area of the photomask on the substrate 170, and another part is located in the light-opaque (Opaque The area is on the substrate The projection area on the 170 (the area other than the projection area 140); and the semiconductor island area 130 is completely located in the projection area 140 of the transparent area on the substrate 170. In one embodiment, the semiconductor islands 110, 120, and 130 are in an amorphous or micro-crystal state, which are formed through a deposition process and a patterning process. The deposition process includes, but is not limited to, chemical vapor deposition (CVD), sputtering, or solution based methods.

為了說明結晶化過程,請參考第2A~2C圖,其係依據第1圖之線段AA’方向的截面示意圖。如第2A圖所示,閃光燈160的發光區域大於光罩的透光區域152,半導體島區110位於基板170的第一面S1上,並且包含第一部分111與第二部分112,其中第二部分112對應位於光罩的透光區域152在基板170上的投影區域140內。當閃光燈(Flash lamp)160透過光罩照射半導體裝置100時,光線可穿過光罩的透光區域152而照射半導體島區110的第二部分112,第二部分112因此變為熔融態(Fusion)。 In order to explain the crystallization process, please refer to FIGS. 2A to 2C, which are schematic cross-sectional views according to the line segment AA ′ direction of FIG. 1. As shown in FIG. 2A, the light emitting area of the flash 160 is larger than the light transmitting area 152 of the mask. The semiconductor island area 110 is located on the first surface S1 of the substrate 170 and includes a first portion 111 and a second portion 112. The second portion 112 corresponds to the projection area 140 of the light-transmitting area 152 of the photomask on the substrate 170. When a flash lamp 160 illuminates the semiconductor device 100 through the photomask, light can pass through the light-transmitting area 152 of the photomask to illuminate the second portion 112 of the semiconductor island region 110, and the second portion 112 thus becomes molten (Fusion ).

於一實施例中,半導體島區110的第一部分111對應到光罩的不透光區域151,因此第一部分111被不透光區域151阻擋而不會受到閃光燈160的照射,而維持其原先狀態(亦即未結晶態或微結晶態)。於另一實施例中,上述光罩的不透光區域151亦可設計為部分透光(Semi-transparent)區域,半導體島區110的第一部分111對應到光罩的部分透光區域,因此接收到衰減後的閃光 燈160照射,第一部分111的晶格可重新排列以具有較原先狀態高的遷移率(Mobility)。應注意到,基板170亦可包含其他相同或不同材料的薄膜或結構,亦即半導體島區110、120、130可形成在基板的其他材料的薄膜或結構上,本揭示內容並非限制半導體島區110、120、130直接形成在基板上。 In an embodiment, the first portion 111 of the semiconductor island region 110 corresponds to the opaque area 151 of the photomask. Therefore, the first portion 111 is blocked by the opaque area 151 without being illuminated by the flash 160 and maintains its original state. (I.e., non-crystalline or microcrystalline). In another embodiment, the opaque area 151 of the photomask can also be designed as a semi-transparent area. The first portion 111 of the semiconductor island region 110 corresponds to a partially translucent area of the photomask. To decaying flash When the lamp 160 is illuminated, the lattice of the first portion 111 may be rearranged to have a higher mobility than the original state. It should be noted that the substrate 170 may also include other films or structures of the same or different materials, that is, the semiconductor islands 110, 120, 130 may be formed on the films or structures of other materials of the substrate, and the present disclosure is not limited to the semiconductor islands. 110, 120, 130 are formed directly on the substrate.

如第2B圖所示,閃光燈160停止照射,熔融態的第二部分112從第二部分112與第一部分111的接面J1開始結晶化(如第2B圖第二部分112內的虛線箭頭所示),以形成第2C圖所示的結晶部分113。於一實施例中,結晶部分113具有側向結晶(Lateral crystallization)特性。 As shown in FIG. 2B, the flash 160 is stopped, and the molten second portion 112 starts to crystallize from the junction J1 between the second portion 112 and the first portion 111 (as shown by the dotted arrow in the second portion 112 in FIG. 2B). ) To form the crystalline portion 113 shown in FIG. 2C. In one embodiment, the crystalline portion 113 has a characteristic of lateral crystallization.

經過如第2A~2C圖所示的製程後,半導體裝置100的上視示意圖如第3圖所示。對應光罩的透光區域152的投影區域140的半導體島區的部分均經過閃光燈160照射與結晶化過程,因此形成結晶部分113、123、133。於一實施例中,由於半導體島區110、120的第一部分111、121位於投影區域140之外,未受到照射而維持原先狀態,因此受到閃光燈160照射而變為熔融態的第二部分112係分別從接面J1、J2開始結晶化而形成結晶部分113(123),而結晶部分113、123具有側向結晶特性。於另一實施例中,由於半導體島區130完全位於投影區域140內,當受到閃光燈160照射變為熔融態之後,半導體島區130結晶化形成結晶部分133,而結晶部分133具有微結晶特性。 After the processes shown in FIGS. 2A to 2C, the top view of the semiconductor device 100 is shown in FIG. 3. Portions of the semiconductor island region corresponding to the projection region 140 of the light-transmitting region 152 of the reticle all undergo the irradiation and crystallization process of the flash lamp 160, so crystal portions 113, 123, and 133 are formed. In an embodiment, since the first portions 111 and 121 of the semiconductor island regions 110 and 120 are located outside the projection area 140 and remain in the original state without being irradiated, the second portion 112 which is irradiated by the flashlight 160 and becomes molten. Crystallization starts from the junctions J1 and J2 to form crystalline portions 113 (123), and the crystalline portions 113 and 123 have lateral crystalline characteristics. In another embodiment, since the semiconductor island region 130 is completely located in the projection region 140, when the semiconductor island region 130 is irradiated into the molten state by irradiation with the flash lamp 160, the semiconductor island region 130 crystallizes to form a crystalline portion 133, and the crystalline portion 133 has microcrystalline characteristics.

由上述實施例製作出的結晶部分可用以形成半 導體元件。舉例而言,如第4圖所示,結晶部分213係進入熔融態的第二部分(與結晶部分213相同位置)從第二部分與第一部分211之間接面J3開始結晶化所形成。半導體元件(例如薄膜電晶體(Thin-Film Transistor,TFT))的通道位於結晶部分213內,並且位於源極221與汲極222之間。當半導體元件運作時,電流由源極221流向汲極222,亦即電流方向I。於一實施例中,電流方向I垂直於接面J3。於另一實施例中,半導體元件亦可設計為其電流方向I與接面J3呈現除了直角以外的其他角度。 The crystalline portion produced by the above embodiment can be used to form a half Conductor element. For example, as shown in FIG. 4, the crystalline portion 213 is formed by melting the second portion (the same position as the crystalline portion 213) in a molten state from the junction J3 between the second portion and the first portion 211. A channel of a semiconductor element (such as a thin-film transistor (TFT)) is located in the crystal portion 213 and is located between the source electrode 221 and the drain electrode 222. When the semiconductor device is operating, a current flows from the source 221 to the drain 222, that is, the current direction I. In one embodiment, the current direction I is perpendicular to the junction J3. In another embodiment, the semiconductor device may also be designed such that the current direction I and the junction J3 present other angles than the right angle.

為了因應不同種類的半導體元件設計,結晶部分的形狀可透過半導體島區的圖案設計與光罩的圖案設計,而具有不同的形狀。於一實施例中,如第5圖所示,半導體島區310為圓形,其包含第一部分311與第二部分312。第一部分311未受到閃光燈160照射,而維持其原先狀態(亦即未結晶態或微結晶態)。第二部分312位於光罩的透光區域的投影區域內,因此受到閃光燈160照射並結晶化而形成環狀(Doughnut shape)的結晶部分。 In order to respond to the design of different kinds of semiconductor elements, the shape of the crystalline part can have different shapes through the design of the pattern of the semiconductor island and the pattern of the photomask. In an embodiment, as shown in FIG. 5, the semiconductor island region 310 is circular and includes a first portion 311 and a second portion 312. The first part 311 is not irradiated by the flash 160 and maintains its original state (that is, an uncrystallized state or a microcrystalline state). The second portion 312 is located in a projection area of the light-transmitting area of the mask, and is therefore irradiated by the flash 160 and crystallized to form a crystalline portion in a doughnut shape.

如此一來,本揭示內容利用光罩配合半導體島區的圖案設計,以閃光燈照射並且進行半導體島區的結晶。相較於準分子雷射退火技術,本揭示內容可達到高均勻度的結晶,因而提高結晶強度的一致性,並且所形成的晶粒尺寸較大(例如微米(μm)等級)。此外,由於光罩設計可將半導體島區分類為完全位於照光區域內(如第1圖半導體島區130)、部分位於照光區域內(如第1圖半導體島區110、 120)以及完全位於未照光區域之外。因此,結晶特性亦可依上述分類判斷得知。舉例而言,如第3圖所示,半導體島區130的結晶區域133為微結晶特性,半導體島區110、120的結晶區域113、123為側向結晶特性。 In this way, the present disclosure utilizes a photomask to cooperate with the pattern design of the semiconductor island area, irradiates it with a flash, and crystallizes the semiconductor island area. Compared with excimer laser annealing technology, the present disclosure can achieve high uniformity of crystallization, thereby improving the consistency of crystalline strength, and the formed grain size is larger (for example, micrometer (μm) grade). In addition, due to the reticle design, the semiconductor islands can be classified as completely located in the illuminated area (such as the semiconductor island 130 in Figure 1), and partially in the illuminated area (such as the semiconductor island 110 in Figure 1, 120) and completely outside the unlit area. Therefore, the crystal characteristics can also be determined according to the above classification. For example, as shown in FIG. 3, the crystal region 133 of the semiconductor island region 130 has microcrystalline characteristics, and the crystal regions 113 and 123 of the semiconductor island regions 110 and 120 have lateral crystal characteristics.

於另一實施例中,閃光燈也可以從基板的背面(亦即第二面S2)照射半導體島區以進行結晶。第6圖係說明本揭示內容一實施例之半導體裝置400之上視示意圖。半導體裝置400包含半導體島區410、420、光調節層430與半導體元件(未繪示)。如第6圖所示,半導體島區410是僅有部分位於光罩的透光區域152在半導體裝置400上的投影區域440內,而半導體島區420完全位於透光區域152的投影區域440內。於一實施例中,半導體島區410、420為未結晶態或微結晶態,其係經過沉積製程與圖案化製程而形成。 In another embodiment, the flash lamp may also irradiate the semiconductor island region from the back surface of the substrate (that is, the second surface S2) to perform crystallization. FIG. 6 is a schematic top view illustrating a semiconductor device 400 according to an embodiment of the present disclosure. The semiconductor device 400 includes semiconductor island regions 410 and 420, a light adjustment layer 430, and a semiconductor element (not shown). As shown in FIG. 6, the semiconductor island region 410 is only partially located in the projection region 440 of the light transmitting region 152 on the semiconductor device 400, and the semiconductor island region 420 is completely located in the projection region 440 of the light transmitting region 152. . In an embodiment, the semiconductor island regions 410 and 420 are in an amorphous state or a microcrystalline state, and are formed through a deposition process and a patterning process.

為了說明結晶化過程,請參考第7A~7C圖,其係依據第6圖線段BB’方向的截面示意圖。如第7A圖所示,閃光燈160從基板470的第二面S2進行照射,並且閃光燈160的發光區域大於光罩的透光區域152。基板470的第一面S1上有光調節層430,並且絕緣層480覆蓋於基板470的第一面S1及光調節層430,半導體島區420形成於絕緣層480的表面上,並且包含第三部分421與第四部分422。當閃光燈160透過光罩從基板470的第一面S1相對的第二面S2照射半導體裝置400時,光線可穿過光罩的透光區域152而照射光調節層430與半導體島區420。由於光調節層430 係作為反光層、光吸收層或是光衰減層的功能,因此光調節層430可完全阻擋閃光燈160照射半導體島區420的第三部分421,而使第三部分421維持其原先狀態(亦即未結晶態或微結晶態)。未受到光調節層430阻擋的第四部分422由於閃光燈160照射而變為熔融態。於另一實施例中,光調節層430可衰減閃光燈160對第三部分421的照射量,因此第三部分421的晶格可重新排列以具有較原先狀態高的遷移率。 In order to explain the crystallization process, please refer to FIGS. 7A to 7C, which are schematic cross-sectional views according to the line segment BB ′ direction of FIG. 6. As shown in FIG. 7A, the flash 160 is irradiated from the second surface S2 of the substrate 470, and the light emitting area of the flash 160 is larger than the light transmitting area 152 of the mask. The first surface S1 of the substrate 470 has a light adjustment layer 430, and the insulating layer 480 covers the first surface S1 and the light adjustment layer 430 of the substrate 470. The semiconductor island region 420 is formed on the surface of the insulating layer 480 and includes a third Part 421 and fourth part 422. When the flash 160 irradiates the semiconductor device 400 from the second surface S2 opposite to the first surface S1 of the substrate 470 through the mask, light can pass through the light-transmitting region 152 of the mask to illuminate the light adjustment layer 430 and the semiconductor island region 420. Thanks to the light regulating layer 430 It functions as a reflective layer, a light absorbing layer, or a light attenuation layer. Therefore, the light adjustment layer 430 can completely block the flash 160 from illuminating the third portion 421 of the semiconductor island 420, and maintain the third portion 421 in its original state (that is, (Uncrystalline or slightly crystalline). The fourth portion 422 that is not blocked by the light adjustment layer 430 is changed into a molten state by the flash 160. In another embodiment, the light adjustment layer 430 can attenuate the exposure of the flash 160 to the third portion 421, so the lattice of the third portion 421 can be rearranged to have a higher mobility than the original state.

如第7B圖所示,閃光燈160停止照射,熔融態的第四部分422從第四部分422與第三部分421的接面J4開始結晶化(如第7B圖第四部分422內的虛線箭頭所示),以形成第7C圖所示的結晶部分423。於一實施例中,結晶部分423具有側向結晶特性。 As shown in FIG. 7B, the flash 160 is stopped, and the fourth portion 422 in the molten state starts to crystallize from the junction J4 between the fourth portion 422 and the third portion 421 (as indicated by the dotted arrow in the fourth portion 422 in FIG. 7B). (Shown) to form the crystal portion 423 shown in FIG. 7C. In one embodiment, the crystalline portion 423 has lateral crystalline characteristics.

經過如第7A~7C圖所示的製程後,半導體裝置400的上視示意圖如第8圖所示。對應光罩的透光區域152的投影區域440的半導體島區並且沒有被光調節層430阻擋的部分均經過閃光燈160照射與結晶化過程,因此形成結晶部分413、423。於一實施例中,由於半導體島區410的第一部分411位於投影區域440之外,以及半導體島區430的第三部分421受到光調節層430的阻擋,未受到閃光燈160照射而維持原先狀態,因此受到閃光燈160照射而變為熔融態的第二部分412、422係分別從接面J4、J5開始結晶化而形成結晶部分413、423,而結晶部分413、423具有側向結晶特性。 After the processes shown in FIGS. 7A to 7C, the top view of the semiconductor device 400 is shown in FIG. 8. The semiconductor island region corresponding to the projection region 440 of the light-transmitting region 152 of the reticle and not blocked by the light adjustment layer 430 has been subjected to the flash 160 irradiation and crystallization process, and thus crystal portions 413 and 423 are formed. In an embodiment, since the first portion 411 of the semiconductor island 410 is located outside the projection area 440 and the third portion 421 of the semiconductor island 430 is blocked by the light adjustment layer 430 and is not irradiated by the flash 160 to maintain the original state, Therefore, the second portions 412 and 422 which are irradiated by the flash 160 and become molten are crystallized from the junctions J4 and J5 to form crystalline portions 413 and 423, respectively. The crystalline portions 413 and 423 have lateral crystalline characteristics.

由上述實施例製作出的結晶部分423可用以形成半導體元件。舉例而言,如第9圖所示,半導體元件(例如薄膜電晶體反相器(Inverter))的通道位於結晶部分423內,並且分別位於源極521與汲極522之間,以及汲極522與源極523之間。當半導體元件運作時,電流由源極521經過汲極522流向另一源極523,亦即電流方向I。於一實施例中,電流方向I垂直於接面J4。於另一實施例中,半導體元件亦可設計為其電流方向I與接面J4呈現除了直角以外的其他角度。 The crystalline portion 423 made in the above embodiment can be used to form a semiconductor device. For example, as shown in FIG. 9, the channels of the semiconductor element (such as a thin film transistor inverter) are located in the crystal portion 423, and are respectively located between the source 521 and the drain 522, and the drain 522 And source 523. When the semiconductor device is operating, a current flows from the source 521 through the drain 522 to another source 523, that is, the current direction I. In one embodiment, the current direction I is perpendicular to the junction J4. In another embodiment, the semiconductor device may also be designed such that the current direction I and the junction J4 present other angles than the right angle.

如此一來,本揭示內容的半導體裝置400可利用光調節層421的設計以阻擋閃光燈從基板第二面S2照射一部分(例如第三部分421)的半導體島區,而未被光調節層421阻擋的其他部分(例如第四部份422)則受到閃光燈照射而變為熔融態,並且從熔融態部分與未變為熔融態的接面J4開始結晶化以形成結晶部分423。 In this way, the semiconductor device 400 of the present disclosure can use the design of the light adjustment layer 421 to block the flash from illuminating a part of the semiconductor island region (for example, the third portion 421) from the second surface S2 of the substrate without being blocked by the light adjustment layer 421. The other parts (for example, the fourth part 422) are irradiated by the flash light and become molten, and the crystalline part starts to crystallize from the molten part and the junction J4 that has not changed to the molten state to form a crystalline part 423.

於另一實施例中,依實際設計需求,半導體島區110~130、410、420上亦可在覆蓋絕緣層(未繪示)的情況下進行結晶化。 In another embodiment, according to actual design requirements, the semiconductor islands 110 to 130, 410, and 420 can also be crystallized with an insulating layer (not shown).

第10圖係說明本揭示內容一實施例之製造方法1000流程圖。製造方法1000具有多個步驟S1002~S1004,其可應用於如第1~3圖、第6~8圖所述的半導體裝置100、400。然熟習本案之技藝者應瞭解到,在本實施例中所提及的步驟,除特別敘明其順序者外,均可依實際需要調整其前後順序,甚至可同時或部分同時執行。具體實作 方式如前揭示,此處不再重複敘述之。 FIG. 10 is a flowchart illustrating a manufacturing method 1000 according to an embodiment of the present disclosure. The manufacturing method 1000 includes a plurality of steps S1002 to S1004, which can be applied to the semiconductor devices 100 and 400 described in FIGS. 1 to 3 and FIGS. 6 to 8. Of course, those skilled in this case should understand that the steps mentioned in this embodiment can be adjusted according to actual needs, except for those who specify the sequence, and can even be performed simultaneously or partially. Concrete implementation The method is disclosed as before, and will not be repeated here.

於步驟S1002,利用閃光燈與光罩,照射基板之第一面上之半導體島區以形成結晶部分,其中半導體島區為非晶態或微結晶態,結晶部分對應光罩之透光區域。 In step S1002, a semiconductor island region on the first surface of the substrate is irradiated with a flash lamp and a photomask to form a crystalline portion, wherein the semiconductor island region is amorphous or microcrystalline, and the crystalline portion corresponds to a light-transmitting region of the photomask.

於步驟S1004,利用結晶部分形成半導體元件,其中半導體元件之通道位於結晶部分內。 In step S1004, a semiconductor element is formed by using a crystalline portion, wherein a channel of the semiconductor element is located in the crystalline portion.

本揭示內容得以透過上述實施例,利用半導體島區的圖案設計配合光罩且/或光調節層的圖案設計,並以閃光燈照射以進行半導體的結晶化,可設計半導體元件的結晶位置與結晶方向,亦有效地提高結晶強度的一致性,並且所形成的晶粒尺寸較大(例如微米(μm)等級)。 Through the above embodiments, the present disclosure can use the pattern design of the semiconductor island area in combination with the pattern design of the photomask and / or the light adjustment layer, and irradiate with a flash to crystallize the semiconductor. The crystal position and crystal direction of the semiconductor element can be designed It also effectively improves the consistency of crystalline strength, and the formed crystal grain size is large (such as micrometer (μm) grade).

雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本新型,任何熟習此技藝者,在不脫離本揭示內容之精神和範圍內,當可作各種之更動與潤飾,因此本新型之保護範圍當視申請專利範圍所界定者為準。 Although the present disclosure has been disclosed above in the form of implementation, it is not intended to limit the new model. Any person skilled in this art can make various changes and retouches without departing from the spirit and scope of the present disclosure. The scope of protection shall be determined by the scope of the patent application.

Claims (4)

一種半導體裝置,包含:一半導體島區,位於一基板之一第一面上,並包含一結晶部分,其係由一閃光燈透過一光罩之一透光區域照射該半導體島區所形成,其中該半導體島區為非晶態或微結晶態;以及一半導體元件,其中該半導體元件之一通道位於該結晶部分內。A semiconductor device includes: a semiconductor island region, which is located on a first surface of a substrate, and includes a crystalline portion, which is formed by a flash lamp illuminating the semiconductor island region through a light transmitting region of a photomask, wherein The semiconductor island region is amorphous or microcrystalline; and a semiconductor element, wherein a channel of the semiconductor element is located in the crystalline portion. 如請求項1所述之半導體裝置,其中該半導體島區包含一第一部分與一第二部分,該第二部分位於該透光區域之一投影區域內,該第一部分鄰近該第二部分;該結晶部分係由該閃光燈從該第一面透過該透光區域照射該第二部分,並且該第二部分從該第二部分與該第一部分之一接面開始結晶化所形成。The semiconductor device according to claim 1, wherein the semiconductor island region includes a first part and a second part, the second part is located in a projection area of the light transmitting area, and the first part is adjacent to the second part; The crystalline part is formed by the flash light illuminating the second part through the light transmitting area from the first side, and the second part starts to crystallize from the interface between the second part and one of the first parts. 如請求項1所述之半導體裝置,更包含:一光調節層,設置於該基板的該第一面,以位於該基板與該半導體島區之間;及一絕緣層,覆蓋於該基板的該第一面及該光調節層,其中該半導體島區形成於該絕緣層的表面上;其中該半導體島區位於該透光區域之一投影區域內,並包含一第三部分與一第四部分;該光調節層對應於該第三部分,該第三部分鄰近該第四部分;該結晶部分係由該閃光燈從該基板之相對於該第一面的一第二面透過該透光區域照射該第四部分,並且該第四部分從該第四部份與該第三部分之一接面開始結晶化所形成。The semiconductor device according to claim 1, further comprising: a light adjustment layer disposed on the first side of the substrate so as to be located between the substrate and the semiconductor island region; and an insulating layer covering the substrate. The first surface and the light adjustment layer, wherein the semiconductor island region is formed on a surface of the insulating layer; wherein the semiconductor island region is located in a projection region of the light transmitting region, and includes a third portion and a fourth The light-adjusting layer corresponds to the third portion, and the third portion is adjacent to the fourth portion; the crystalline portion is transmitted by the flash light from the second surface of the substrate opposite to the first surface through the light-transmitting area The fourth part is irradiated, and the fourth part is formed by crystallization from the interface between the fourth part and the third part. 如請求項1所述之半導體裝置,其中該光罩更包含一不透光區域或一部分透光區域。The semiconductor device according to claim 1, wherein the photomask further includes an opaque area or a part of the opaque area.
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