TWI704697B - Semiconductor device and manufacturing method for the same - Google Patents
Semiconductor device and manufacturing method for the same Download PDFInfo
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- TWI704697B TWI704697B TW108119782A TW108119782A TWI704697B TW I704697 B TWI704697 B TW I704697B TW 108119782 A TW108119782 A TW 108119782A TW 108119782 A TW108119782 A TW 108119782A TW I704697 B TWI704697 B TW I704697B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims description 13
- 238000002425 crystallisation Methods 0.000 claims description 10
- 230000008025 crystallization Effects 0.000 claims description 10
- 230000001678 irradiating effect Effects 0.000 claims description 6
- 239000013078 crystal Substances 0.000 abstract description 23
- 239000013081 microcrystal Substances 0.000 abstract description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
Description
本揭示內容是關於一種製造技術,且特別是關於一種半導體裝置及其製造方法。 The present disclosure relates to a manufacturing technology, and particularly to a semiconductor device and a manufacturing method thereof.
為了結晶化半導體,一般而言考慮到基板的內受溫度,準分子雷射退火(Excimer Laser Annealing,ELA)的製程是目前較常採用的技術。然而,線掃描(Linear scanning)的準分子雷射退火受限於雷射光點的尺寸而無法一次處理大面積的區域,並且由於每一個雷射光點的功率不穩定,造成均勻性不佳而容易產生斑(Mura)的問題。因此,產能與基板的面積難以提高,生產成本居高不下之外,結晶品質與晶粒尺寸亦不理想。 In order to crystallize semiconductors, generally speaking, considering the internal temperature of the substrate, the Excimer Laser Annealing (ELA) process is currently a more commonly used technology. However, linear scanning (Linear scanning) excimer laser annealing is limited by the size of the laser spot and cannot handle a large area at one time, and because the power of each laser spot is unstable, the uniformity is not good and easy There is a problem of mura. Therefore, it is difficult to increase the production capacity and the area of the substrate, the production cost remains high, and the crystal quality and grain size are not ideal.
此外,若欲利用半導體結晶部分製作元件,則需要根據最終製作完成的元件的位置,調整所採用的製程以結合結晶位置與元件位置,並決定結晶方向。此種方式常造成元件結晶化情形難以掌握,以及結晶強度一致性不高的現象。 In addition, if you want to use the semiconductor crystal part to make a device, you need to adjust the process used to combine the crystal position and the device position according to the final position of the finished device, and determine the crystal direction. This method often results in the difficulty of grasping the crystallization status of the device and the inconsistent crystal strength.
為了提高用於製作半導體元件的結晶部分的結晶強度一致性,本揭示內容是提供一種半導體裝置,其包含半導體島區與半導體元件。半導體島區位於基板之第一面上,並包含結晶部分,其係由閃光燈(Flash lamp)透過光罩之透光(Transparent)區域照射半導體島區所形成,其中半導體島區為非晶態(Amorphous)或微結晶態(Micro-crystal)。半導體元件之通道位於結晶部分內。 In order to improve the consistency of the crystal strength of the crystal part used for manufacturing the semiconductor device, the present disclosure provides a semiconductor device including a semiconductor island region and a semiconductor device. The semiconductor island region is located on the first surface of the substrate and contains a crystalline part, which is formed by illuminating the semiconductor island region with a flash lamp through the transparent region of the photomask, and the semiconductor island region is amorphous ( Amorphous) or Micro-crystal. The channel of the semiconductor element is located in the crystalline part.
於本揭示內容之一實施例中,其中半導體島區包含第一部分與第二部分。第二部分位於透光區域之投影區域內,第一部分鄰近第二部分。結晶部分係由閃光燈從第一面透過透光區域照射第二部分,並從第二部分與第一部分之接面開始結晶化所形成。 In an embodiment of the present disclosure, the semiconductor island region includes a first part and a second part. The second part is located in the projection area of the transparent area, and the first part is adjacent to the second part. The crystalline part is formed by the flash lamp illuminating the second part from the first surface through the light-transmitting area, and crystallizes from the interface between the second part and the first part.
於本揭示內容之一實施例中,更包含光調節層以及絕緣層。光調節層設置於基板的第一面,以位於基板與半導體島區之間。絕緣層覆蓋於基板的第一面及光調節層,其中半導體島區形成於絕緣層的表面上。半導體島區位於透光區域之投影區域內,並包含第三部分與第四部分。光調節層對應於第三部分,第三部分鄰近第四部分。結晶部分係由閃光燈從基板之相對於第一面的第二面透過透光區域照射第四部分,並從第四部份與第三部分之接面開始結晶化所形成。 In an embodiment of the present disclosure, it further includes a light adjustment layer and an insulating layer. The light adjustment layer is arranged on the first surface of the substrate so as to be located between the substrate and the semiconductor island region. The insulating layer covers the first surface of the substrate and the light adjustment layer, and the semiconductor island region is formed on the surface of the insulating layer. The semiconductor island area is located in the projection area of the light-transmitting area, and includes a third part and a fourth part. The light adjustment layer corresponds to the third part, and the third part is adjacent to the fourth part. The crystalline part is formed by the flash lamp illuminates the fourth part from the second surface of the substrate opposite to the first surface through the light-transmitting area, and crystallizes from the interface between the fourth part and the third part.
於本揭示內容之一實施例中,其中光罩更包含不透光(Opaque)區域或部分透光(Semi-transparent) 區域。 In an embodiment of the present disclosure, the photomask further includes Opaque regions or semi-transparent regions area.
本揭示內容的另一態樣是提供一種半導體裝置的製造方法,包含:利用閃光燈與光罩,照射基板之第一面上之半導體島區以形成結晶部分,其中半導體島區為非晶態或微結晶態,結晶部分對應該光罩之透光區域。利用結晶部分形成半導體元件,其中半導體元件之通道位於結晶部分內。 Another aspect of the present disclosure is to provide a method for manufacturing a semiconductor device, which includes: irradiating a semiconductor island region on the first surface of a substrate with a flash lamp and a photomask to form a crystalline portion, wherein the semiconductor island region is amorphous or Microcrystalline state, the crystalline part corresponds to the light-transmitting area of the mask. The crystalline part is used to form a semiconductor element, wherein the channel of the semiconductor element is located in the crystalline part.
於本揭示內容之一實施例中,更包含:利用閃光燈與光罩,由第一面照射半導體島區,其中半導體島區包含第一部分與第二部分,第二部分位於透光區域之投影區域內,第一部分鄰近第二部分。第二部分從第二部分與第一部分之接面開始結晶化,以形成結晶部分。 In an embodiment of the present disclosure, it further includes: using a flash lamp and a photomask to illuminate the semiconductor island area from the first side, wherein the semiconductor island area includes a first part and a second part, and the second part is located in the projection area of the light-transmitting area Inside, the first part is adjacent to the second part. The second part crystallizes from the junction of the second part and the first part to form a crystalline part.
於本揭示內容之一實施例中,更包含:設置一光調節層於基板的第一面,以位於半導體島區和基板之間;設置一絕緣層,以覆蓋於基板的第一面及光調節層,其中半導體島區形成於絕緣層的表面上;利用閃光燈與光罩,由基板之相對於第一面的一第二面照射半導體島區,半導體島區位於透光區域之一投影區域內,並包含一第三部分與一第四部分,光調節層對應於第三部分,第三部分鄰近第四部分。第四部分從第四部分與該第三部分之一接面開始結晶化,以形成結晶部分。 In an embodiment of the present disclosure, it further includes: disposing a light adjustment layer on the first surface of the substrate so as to be located between the semiconductor island area and the substrate; disposing an insulating layer to cover the first surface of the substrate and the light The adjustment layer, in which the semiconductor island region is formed on the surface of the insulating layer; using a flash lamp and a photomask, the semiconductor island region is illuminated by a second side of the substrate opposite to the first side, and the semiconductor island region is located in a projection area of the transparent region And includes a third part and a fourth part. The light adjustment layer corresponds to the third part, and the third part is adjacent to the fourth part. The fourth part starts to crystallize from the junction of the fourth part and the third part to form a crystalline part.
於本揭示內容之一實施例中,其中光罩更包含不透光區域或部分透光區域。 In an embodiment of the present disclosure, the photomask further includes an opaque area or a partially transparent area.
綜上所述,本揭示內容係利用半導體島區的圖 案設計配合光罩且/或光調節層的圖案設計,並以閃光燈照射以進行半導體的結晶化,可設計半導體元件的結晶位置與結晶方向,亦有效地提高結晶強度的一致性,並且所形成的晶粒尺寸較大(例如微米(μm)等級)。 In summary, the present disclosure uses the map of the semiconductor island The design of the case is matched with the pattern design of the photomask and/or the light adjustment layer, and the flash lamp is used to crystallize the semiconductor. The crystal position and crystal direction of the semiconductor element can be designed, and the consistency of the crystal strength is also effectively improved. The grain size is relatively large (for example, micrometer (μm) level).
以下將以實施方式對上述之說明作詳細的描述,並對本揭示內容之技術方案提供更進一步的解釋。 Hereinafter, the above description will be described in detail by way of implementation, and a further explanation will be provided for the technical solution of the present disclosure.
為讓本揭示內容之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附符號之說明如下: In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more comprehensible, the description of the attached symbols is as follows:
100、400:半導體裝置 100, 400: semiconductor device
110、120、130、310、410、420:半導體島區 110, 120, 130, 310, 410, 420: semiconductor island area
111、121、211、311:第一部分 111, 121, 211, 311: Part One
112、312:第二部分 112, 312: Part Two
113、123、133、213:結晶部分 113, 123, 133, 213: crystalline part
140、440:投影區域 140, 440: projection area
151:光罩的不透光區域 151: The opaque area of the photomask
152:光罩的透光區域 152: Transmissive area of the photomask
AA’、BB’:線段 AA’, BB’: Line segment
170、470:基板 170, 470: substrate
S1:第一面 S1: First side
J1、J2、J3、J4、J5:接面 J1, J2, J3, J4, J5: junction
I:電流方向 I: Current direction
221、521、523:源極 221, 521, 523: Source
222、522:汲極 222, 522: Drain
411、421:第三部分 411, 421: Part Three
422:第四部份 422: Part Four
413、423:結晶部分 413, 423: Crystalline part
430:光調節層 430: light adjustment layer
480:絕緣層 480: insulating layer
S2:第二面 S2: Second side
1000:製造方法 1000: Manufacturing method
S1002~S1004:步驟 S1002~S1004: steps
為讓本揭示內容之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖示之說明如下:第1圖係說明本揭示內容一實施例之半導體裝置之上視示意圖;第2A圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第2B圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第2C圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第3圖係說明本揭示內容一實施例之半導體裝置之上視示意圖;第4圖係說明本揭示內容一實施例之半導體元件示意圖;第5圖係說明本揭示內容一實施例之半導體元件示意圖; 第6圖係說明本揭示內容一實施例之半導體裝置之上視示意圖;第7A圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第7B圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第7C圖係說明本揭示內容一實施例之半導體裝置之截面示意圖;第8圖係說明本揭示內容一實施例之半導體裝置之上視示意圖;第9圖係說明本揭示內容一實施例之半導體元件示意圖;以及第10圖係說明本揭示內容一實施例之製造方法流程圖。 In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more comprehensible, the description of the accompanying drawings is as follows: Figure 1 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure; Fig. 2A is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure; Fig. 2B is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure; Fig. 2C illustrates a semiconductor device according to an embodiment of the present disclosure Fig. 3 is a schematic top view of a semiconductor device illustrating an embodiment of the present disclosure; Fig. 4 is a schematic diagram illustrating a semiconductor device of an embodiment of the present disclosure; Fig. 5 illustrates an embodiment of the present disclosure Schematic diagram of semiconductor components; Fig. 6 is a schematic top view of a semiconductor device illustrating an embodiment of the present disclosure; Fig. 7A is a schematic cross-sectional view illustrating a semiconductor device of an embodiment of the present disclosure; Fig. 7B illustrates a semiconductor device of an embodiment of the present disclosure A schematic cross-sectional view of the device; Figure 7C is a schematic cross-sectional view of a semiconductor device illustrating an embodiment of the present disclosure; Figure 8 is a schematic top view illustrating a semiconductor device of an embodiment of the present disclosure; Figure 9 illustrates the present disclosure A schematic diagram of a semiconductor device of an embodiment; and FIG. 10 is a flowchart illustrating a manufacturing method of an embodiment of the present disclosure.
為了使本揭示內容之敘述更加詳盡與完備,可參照附圖及以下所述之各種實施例。但所提供之實施例並非用以限制本發明所涵蓋的範圍;步驟的描述亦非用以限制其執行之順序,任何由重新組合,所產生具有均等功效的裝置,皆為本發明所涵蓋的範圍。 In order to make the description of the present disclosure more detailed and complete, please refer to the drawings and various embodiments described below. However, the examples provided are not intended to limit the scope of the present invention; the description of the steps is not intended to limit the order of their execution. Any device with equal effects produced by recombination is all covered by the present invention. range.
於實施方式與申請專利範圍中,除非內文中對於冠詞有所特別限定,否則「一」與「該」可泛指單一個或複數個。將進一步理解的是,本文中所使用之「包含」、「包 括」、「具有」及相似詞彙,指明其所記載的特徵、區域、整數、步驟、操作、元件與/或組件,但不排除其所述或額外的其一個或多個其它特徵、區域、整數、步驟、操作、元件、組件,與/或其中之群組。 In the implementation mode and the scope of the patent application, unless the article is specifically limited in the context, "a" and "the" can generally refer to a single or plural. It will be further understood that the "include", "package" used in this article "Enclosed", "have" and similar words indicate the recorded features, regions, integers, steps, operations, elements and/or components, but do not exclude the mentioned or additional one or more other features, regions, Integers, steps, operations, elements, components, and/or groups thereof.
關於本文中所使用之「約」、「大約」或「大致約」一般通常係指數值之誤差或範圍約百分之二十以內,較好地是約百分之十以內,而更佳地則是約百分五之以內。文中若無明確說明,其所提及的數值皆視作為近似值,即如「約」、「大約」或「大致約」所表示的誤差或範圍。 Regarding the "about", "approximately" or "approximately" used in this article, the error or range of the index value is generally within about 20%, preferably within about 10%, and more preferably It is within about five percent. If there is no clear description in the text, the values mentioned are regarded as approximate values, that is, the error or range represented by "about", "approximately" or "approximately".
此外,相對詞彙,如「下」或「底部」與「上」或「頂部」,用來描述文中在附圖中所示的一元件與另一元件之關係。相對詞彙是用來描述裝置在附圖中所描述之外的不同方位是可以被理解的。例如,如果一附圖中的裝置被翻轉,元件將會被描述原為位於其它元件之「下」側將被定向為位於其他元件之「上」側。例示性的詞彙「下」,根據附圖的特定方位可以包含「下」和「上」兩種方位。 In addition, relative terms, such as "under" or "bottom" and "up" or "top", are used to describe the relationship between one element and another element shown in the drawings in the text. It is understandable that the relative vocabulary is used to describe different orientations of the device other than those described in the drawings. For example, if the device in one figure is turned over, the components will be described as being on the "lower" side of other components and will be oriented on the "upper" side of the other components. The exemplified word "down" can include two directions of "down" and "up" according to the specific orientation of the drawing.
第1圖係說明本揭示內容一實施例之半導體裝置100之上視示意圖。半導體裝置100包含半導體島區(Island)110、120、130與半導體元件(未繪示)。如第1圖所示,半導體島區110、120是有一部分位於光罩的透光(Transparent)區域在基板170上的投影區域140內,而有另一部分是位於光罩的不透光(Opaque)區域在基板170上的投影區域(投影區域140以外的區域);而半導體島區130是完全位於透光區域在基板170上的投影區域140
內。於一實施例中,半導體島區110、120、130為未結晶態(Amorphous)或微結晶態(Micro-crystal),其係經過沉積(Deposition)製程與圖案化(Patterning)製程而形成。沉積製程包含但不限於化學氣相沉積(Chemical Vapor Deposition,CVD)、濺鍍(Sputter)或應用溶液(Solution based)的方法。
FIG. 1 is a schematic top view illustrating a
為了說明結晶化過程,請參考第2A~2C圖,其係依據第1圖之線段AA’方向的截面示意圖。如第2A圖所示,閃光燈160的發光區域大於光罩的透光區域152,半導體島區110位於基板170的第一面S1上,並且包含第一部分111與第二部分112,其中第二部分112對應位於光罩的透光區域152在基板170上的投影區域140內。當閃光燈(Flash lamp)160透過光罩照射半導體裝置100時,光線可穿過光罩的透光區域152而照射半導體島區110的第二部分112,第二部分112因此變為熔融態(Fusion)。
In order to illustrate the crystallization process, please refer to Figures 2A~2C, which is a schematic cross-sectional view along the line AA' in Figure 1. As shown in Figure 2A, the light-emitting area of the
於一實施例中,半導體島區110的第一部分111對應到光罩的不透光區域151,因此第一部分111被不透光區域151阻擋而不會受到閃光燈160的照射,而維持其原先狀態(亦即未結晶態或微結晶態)。於另一實施例中,上述光罩的不透光區域151亦可設計為部分透光(Semi-transparent)區域,半導體島區110的第一部分111對應到光罩的部分透光區域,因此接收到衰減後的閃光燈160照射,第一部分111的晶格可重新排列以具有較原先狀態高的遷移率(Mobility)。應注意到,基板170亦可包
含其他相同或不同材料的薄膜或結構,亦即半導體島區110、120、130可形成在基板的其他材料的薄膜或結構上,本揭示內容並非限制半導體島區110、120、130直接形成在基板上。
In one embodiment, the
如第2B圖所示,閃光燈160停止照射,熔融態的第二部分112從第二部分112與第一部分111的接面J1開始結晶化(如第2B圖第二部分112內的虛線箭頭所示),以形成第2C圖所示的結晶部分113。於一實施例中,結晶部分113具有側向結晶(Lateral crystallization)特性。
As shown in Figure 2B, the
經過如第2A~2C圖所示的製程後,半導體裝置100的上視示意圖如第3圖所示。對應光罩的透光區域152的投影區域140的半導體島區的部分均經過閃光燈160照射與結晶化過程,因此形成結晶部分113、123、133。於一實施例中,由於半導體島區110、120的第一部分111、121位於投影區域140之外,未受到照射而維持原先狀態,因此受到閃光燈160照射而變為熔融態的第二部分112係分別從接面J1、J2開始結晶化而形成結晶部分113(123),而結晶部分113、123具有側向結晶特性。於另一實施例中,由於半導體島區130完全位於投影區域140內,當受到閃光燈160照射變為熔融態之後,半導體島區130結晶化形成結晶部分133,而結晶部分133具有微結晶特性。
After the manufacturing process shown in FIGS. 2A to 2C, a schematic top view of the
由上述實施例製作出的結晶部分可用以形成半導體元件。舉例而言,如第4圖所示,結晶部分213係進入熔融態的第二部分(與結晶部分213相同位置)從第二部分
與第一部分211之間接面J3開始結晶化所形成。半導體元件(例如薄膜電晶體(Thin-Film Transistor,TFT))的通道位於結晶部分213內,並且位於源極221與汲極222之間。當半導體元件運作時,電流由源極221流向汲極222,亦即電流方向I。於一實施例中,電流方向I垂直於接面J3。於另一實施例中,半導體元件亦可設計為其電流方向I與接面J3呈現除了直角以外的其他角度。
The crystalline part produced by the above embodiments can be used to form a semiconductor device. For example, as shown in Figure 4, the
為了因應不同種類的半導體元件設計,結晶部分的形狀可透過半導體島區的圖案設計與光罩的圖案設計,而具有不同的形狀。於一實施例中,如第5圖所示,半導體島區310為圓形,其包含第一部分311與第二部分312。第一部分311未受到閃光燈160照射,而維持其原先狀態(亦即未結晶態或微結晶態)。第二部分312位於光罩的透光區域的投影區域內,因此受到閃光燈160照射並結晶化而形成環狀(Doughnut shape)的結晶部分。
In order to respond to different types of semiconductor device designs, the shape of the crystalline part can have different shapes through the pattern design of the semiconductor island region and the pattern design of the photomask. In one embodiment, as shown in FIG. 5, the
如此一來,本揭示內容利用光罩配合半導體島區的圖案設計,以閃光燈照射並且進行半導體島區的結晶。相較於準分子雷射退火技術,本揭示內容可達到高均勻度的結晶,因而提高結晶強度的一致性,並且所形成的晶粒尺寸較大(例如微米(μm)等級)。此外,由於光罩設計可將半導體島區分類為完全位於照光區域內(如第1圖半導體島區130)、部分位於照光區域內(如第1圖半導體島區110、120)以及完全位於未照光區域之外。因此,結晶特性亦可依上述分類判斷得知。舉例而言,如第3圖所示,半導體島
區130的結晶區域133為微結晶特性,半導體島區110、120的結晶區域113、123為側向結晶特性。
In this way, the present disclosure utilizes the photomask to match the pattern design of the semiconductor island region, and illuminates the semiconductor island region with a flash lamp to crystallize the semiconductor island region. Compared with the excimer laser annealing technology, the present disclosure can achieve high uniformity of crystallization, thereby improving the consistency of crystal strength, and the formed crystal grain size is larger (for example, micrometer (μm) level). In addition, due to the photomask design, the semiconductor island regions can be classified as completely located in the illuminated region (such as the
於另一實施例中,閃光燈也可以從基板的背面(亦即第二面S2)照射半導體島區以進行結晶。第6圖係說明本揭示內容一實施例之半導體裝置400之上視示意圖。半導體裝置400包含半導體島區410、420、光調節層430與半導體元件(未繪示)。如第6圖所示,半導體島區410是僅有部分位於光罩的透光區域152在半導體裝置400上的投影區域440內,而半導體島區420完全位於透光區域152的投影區域440內。於一實施例中,半導體島區410、420為未結晶態或微結晶態,其係經過沉積製程與圖案化製程而形成。
In another embodiment, the flash lamp can also illuminate the semiconductor island region from the back side of the substrate (ie, the second surface S2) for crystallization. FIG. 6 is a schematic top view illustrating a
為了說明結晶化過程,請參考第7A~7C圖,其係依據第6圖線段BB’方向的截面示意圖。如第7A圖所示,閃光燈160從基板470的第二面S2進行照射,並且閃光燈160的發光區域大於光罩的透光區域152。基板470的第一面S1上有光調節層430,並且絕緣層480覆蓋於基板470的第一面S1及光調節層430,半導體島區420形成於絕緣層480的表面上,並且包含第三部分421與第四部分422。當閃光燈160透過光罩從基板470的第一面S1相對的第二面S2照射半導體裝置400時,光線可穿過光罩的透光區域152而照射光調節層430與半導體島區420。由於光調節層430係作為反光層、光吸收層或是光衰減層的功能,因此光調節層430可完全阻擋閃光燈160照射半導體島區420的第三部
分421,而使第三部分421維持其原先狀態(亦即未結晶態或微結晶態)。未受到光調節層430阻擋的第四部分422由於閃光燈160照射而變為熔融態。於另一實施例中,光調節層430可衰減閃光燈160對第三部分421的照射量,因此第三部分421的晶格可重新排列以具有較原先狀態高的遷移率。
In order to illustrate the crystallization process, please refer to Figures 7A to 7C, which is a schematic cross-sectional view along the line BB' in Figure 6. As shown in FIG. 7A, the
如第7B圖所示,閃光燈160停止照射,熔融態的第四部分422從第四部分422與第三部分421的接面J4開始結晶化(如第7B圖第四部分422內的虛線箭頭所示),以形成第7C圖所示的結晶部分423。於一實施例中,結晶部分423具有側向結晶特性。
As shown in Fig. 7B, the
經過如第7A~7C圖所示的製程後,半導體裝置400的上視示意圖如第8圖所示。對應光罩的透光區域152的投影區域440的半導體島區並且沒有被光調節層430阻擋的部分均經過閃光燈160照射與結晶化過程,因此形成結晶部分413、423。於一實施例中,由於半導體島區410的第一部分411位於投影區域440之外,以及半導體島區430的第三部分421受到光調節層430的阻擋,未受到閃光燈160照射而維持原先狀態,因此受到閃光燈160照射而變為熔融態的第二部分412、422係分別從接面J4、J5開始結晶化而形成結晶部分413、423,而結晶部分413、423具有側向結晶特性。
After the manufacturing process shown in FIGS. 7A to 7C, the top schematic view of the
由上述實施例製作出的結晶部分423可用以形成半導體元件。舉例而言,如第9圖所示,半導體元件(例
如薄膜電晶體反相器(Inverter))的通道位於結晶部分423內,並且分別位於源極521與汲極522之間,以及汲極522與源極523之間。當半導體元件運作時,電流由源極521經過汲極522流向另一源極523,亦即電流方向I。於一實施例中,電流方向I垂直於接面J4。於另一實施例中,半導體元件亦可設計為其電流方向I與接面J4呈現除了直角以外的其他角度。
The
如此一來,本揭示內容的半導體裝置400可利用光調節層421的設計以阻擋閃光燈從基板第二面S2照射一部分(例如第三部分421)的半導體島區,而未被光調節層421阻擋的其他部分(例如第四部份422)則受到閃光燈照射而變為熔融態,並且從熔融態部分與未變為熔融態的接面J4開始結晶化以形成結晶部分423。
In this way, the
於另一實施例中,依實際設計需求,半導體島區110~130、410、420上亦可在覆蓋絕緣層(未繪示)的情況下進行結晶化。 In another embodiment, according to actual design requirements, the semiconductor island regions 110-130, 410, 420 can also be crystallized with an insulating layer (not shown) being covered.
第10圖係說明本揭示內容一實施例之製造方法1000流程圖。製造方法1000具有多個步驟S1002~S1004,其可應用於如第1~3圖、第6~8圖所述的半導體裝置100、400。然熟習本案之技藝者應瞭解到,在本實施例中所提及的步驟,除特別敘明其順序者外,均可依實際需要調整其前後順序,甚至可同時或部分同時執行。具體實作方式如前揭示,此處不再重複敘述之。
FIG. 10 is a flowchart illustrating a
於步驟S1002,利用閃光燈與光罩,照射基板 之第一面上之半導體島區以形成結晶部分,其中半導體島區為非晶態或微結晶態,結晶部分對應光罩之透光區域。 In step S1002, the substrate is illuminated with a flash lamp and a photomask The semiconductor island region on the first surface forms a crystalline part, wherein the semiconductor island region is in an amorphous or microcrystalline state, and the crystalline part corresponds to the light-transmitting region of the photomask.
於步驟S1004,利用結晶部分形成半導體元件,其中半導體元件之通道位於結晶部分內。 In step S1004, a semiconductor element is formed by using the crystallized part, wherein the channel of the semiconductor element is located in the crystallized part.
本揭示內容得以透過上述實施例,利用半導體島區的圖案設計配合光罩且/或光調節層的圖案設計,並以閃光燈照射以進行半導體的結晶化,可設計半導體元件的結晶位置與結晶方向,亦有效地提高結晶強度的一致性,並且所形成的晶粒尺寸較大(例如微米(μm)等級)。 The present disclosure can be achieved through the above-mentioned embodiments, using the pattern design of the semiconductor island region to match the pattern design of the photomask and/or the light adjustment layer, and irradiating with a flash lamp to perform the crystallization of the semiconductor, so that the crystal position and crystal direction of the semiconductor element can be designed , It also effectively improves the consistency of crystal strength, and the formed crystal grain size is larger (for example, micrometer (μm) level).
雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本揭示內容之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視申請專利範圍所界定者為準。 Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone familiar with this technique can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the present invention The scope of protection shall be determined by the scope of the patent application.
100:半導體裝置 100: Semiconductor device
111、121:第一部分 111, 121: Part One
113、123、133:結晶部分 113, 123, 133: crystalline part
140:投影區域 140: Projection area
170:基板 170: substrate
J1、J2:接面 J1, J2: junction
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US7638728B2 (en) * | 2003-09-16 | 2009-12-29 | The Trustees Of Columbia University In The City Of New York | Enhancing the width of polycrystalline grains with mask |
TW201001556A (en) * | 2008-02-29 | 2010-01-01 | Univ Columbia | Flash lamp annealing crystallization for large area thin films |
TW201723239A (en) * | 2015-12-17 | 2017-07-01 | 宸鴻光電科技股份有限公司 | Manufacturing method and semiconductor film |
TWM585988U (en) * | 2018-10-23 | 2019-11-01 | 宸鴻光電科技股份有限公司 | Semiconductor device |
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TW202017202A (en) | 2020-05-01 |
TWM585988U (en) | 2019-11-01 |
CN111092124A (en) | 2020-05-01 |
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