CN111092015A - Semiconductor manufacturing method and semiconductor layer - Google Patents
Semiconductor manufacturing method and semiconductor layer Download PDFInfo
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- CN111092015A CN111092015A CN201811234234.7A CN201811234234A CN111092015A CN 111092015 A CN111092015 A CN 111092015A CN 201811234234 A CN201811234234 A CN 201811234234A CN 111092015 A CN111092015 A CN 111092015A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 230000001678 irradiating effect Effects 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 238000002425 crystallisation Methods 0.000 abstract description 26
- 230000008025 crystallization Effects 0.000 abstract description 23
- 230000008707 rearrangement Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 230000002238 attenuated effect Effects 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 230000004927 fusion Effects 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- Microelectronics & Electronic Packaging (AREA)
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- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Crystallography & Structural Chemistry (AREA)
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- Optics & Photonics (AREA)
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- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
Abstract
A semiconductor manufacturing method and a semiconductor layer. The semiconductor layer includes a first crystalline portion and a second crystalline portion. The first crystallized portion is crystallized from the semi-molten first portion and the second crystallized portion is crystallized from the molten second portion. The semi-molten first portion and the molten second portion are formed by a flash lamp irradiating the first portion and the second portion through a first mask. The first mask comprises a part of light-transmitting area and a light-transmitting area, wherein the part of light-transmitting area corresponds to the first part, and the light-transmitting area corresponds to the second part. The second crystallization portion is formed by starting crystallization of the second portion from the junction of the first portion and the second portion. The first crystalline portion is formed by lattice rearrangement of the first portion. The flash lamp is used in combination with the mask to achieve a larger area of crystallization, and different portions of the semiconductor layer can have different crystallization characteristics.
Description
Technical Field
The present disclosure relates to manufacturing techniques, and more particularly, to semiconductor manufacturing methods and semiconductor layers.
Background
In order to crystallize a semiconductor, generally, an Excimer Laser Annealing (ELA) process is a technique which is commonly used at present in consideration of an internal temperature of a substrate. However, excimer laser annealing by line scanning (Linear scanning) is limited in the size of laser spot and cannot process a large area at a time, and causes a problem of spot (Mura) generation due to poor uniformity due to unstable power of each laser spot. Therefore, the productivity and the substrate area are difficult to be increased, the production cost is high, and the crystal quality and the grain size are not desirable.
Disclosure of Invention
In order to improve the crystalline quality and grain size of crystalline portions used to fabricate semiconductor devices, the present disclosure provides a semiconductor layer comprising a first crystalline portion and a second crystalline portion. The first crystalline fraction is formed by crystallization of the first fraction in a Semi-molten state (Semi-Fusion) and the second crystalline fraction is formed by crystallization of the second fraction in a molten state (Fusion). The semi-molten first portion and the molten second portion are formed by a Flash lamp (Flash lamp) irradiating the first portion and the second portion through a first mask. The first mask includes a partially light-transmissive (Semi-transmissive) region and a light-transmissive region, the partially light-transmissive region corresponding to the first portion, and the light-transmissive region corresponding to the second portion. The first portion is adjacent to the second portion. The second crystallization portion is formed by starting crystallization of the second portion from the junction of the first portion and the second portion. The first crystalline portion is formed by lattice rearrangement of the first portion.
In one embodiment of the present disclosure, the first crystalline portion comprises a Micro-crystalline (Micro crystal) portion.
In one embodiment of the present disclosure, the second crystalline portion includes a lateral crystallization (lateracrystallization) portion.
In an embodiment of the present disclosure, the method further includes: an Amorphous (Amorphous) portion is formed by irradiating the semiconductor layer with a flash lamp through a first mask, wherein the first mask further comprises opaque regions corresponding to the Amorphous portion.
In an embodiment of the present disclosure, the flash lamp irradiates the semiconductor layer through the second mask to change a crystallization condition of the semiconductor layer.
Another aspect of the present disclosure is to provide a method for manufacturing a semiconductor, comprising the following steps. Irradiating the semiconductor layer by using a flash lamp and a first photomask, so that a first part of the semiconductor layer becomes semi-molten state and a second part of the semiconductor layer becomes molten state, wherein the first photomask comprises a partial light-transmitting area and a light-transmitting area. The partially light-transmissive region corresponds to a first portion, the light-transmissive region corresponds to a second portion, and the first portion is adjacent to the second portion. Crystallizing the second portion from the junction of the first portion and the second portion to form a second crystalline portion. The crystal lattice of the first portion is rearranged to form a first crystalline portion.
In one embodiment of the present disclosure, the first crystalline portion includes a microcrystalline portion.
In one embodiment of the present disclosure, the second crystalline portion includes a lateral crystalline portion.
In one embodiment of the present disclosure, the first mask further comprises an opaque region corresponding to an amorphous portion of the semiconductor layer after the semiconductor layer is irradiated with the flash lamp and the first mask.
In an embodiment of the present disclosure, the method further includes: the flash lamp and the second mask are used to irradiate the semiconductor layer to change the crystallization state of the semiconductor layer.
In summary, the present disclosure can achieve a larger area of crystallization by using a flash lamp and a mask for irradiation, and the quality of crystallization is also better. Specifically, the Crystal grains (Crystal grains) in the crystalline portion (e.g., the first crystalline portion, the second crystalline portion) of the semiconductor layer of the present disclosure have a larger size (e.g., micrometer (μm) level) and a more uniform arrangement (e.g., lateral crystallization). In addition, the present disclosure can achieve different crystalline characteristics, such as lateral crystallization and micro-crystallization characteristics, of different portions of the semiconductor layer of the same material by only one irradiation of the flash lamp through the mask.
The above description will be described in detail by embodiments, and further explanation will be provided for the technical solution of the present disclosure.
Drawings
The foregoing and other objects, features, advantages and embodiments of the disclosure will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:
FIG. 1A is a schematic cross-sectional view illustrating a semiconductor layer according to one embodiment of the present disclosure;
FIG. 1B is a schematic cross-sectional view illustrating a semiconductor layer according to one embodiment of the present disclosure;
FIG. 1C is a schematic cross-sectional view illustrating a semiconductor layer according to one embodiment of the present disclosure; and
FIG. 2 is a flow chart illustrating a method of manufacturing an embodiment of the present disclosure.
Detailed Description
For a more complete and complete description of the present disclosure, reference is made to the accompanying drawings and the various embodiments described below. The examples provided are not intended to limit the scope of the invention; neither is the order of execution presented to limit the scope of the invention, and any device that results in a similar effect, if any, from a combination of the two or more steps is within the scope of the invention.
In the description and claims, the terms "a" and "an" can be used broadly to refer to a single or to a plurality of elements, unless the context specifically states the article. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and similar language, when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term "about", "about" or "approximately about" generally means within about twenty percent, preferably within about ten percent, and more preferably within about five percent of the error or range of the numerical value. Unless otherwise indicated, all numbers recited herein are to be interpreted as approximations, as indicated by the error or range of values expressed as "about," about, "or" approximately about.
Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," are used herein to describe one element's relationship to another element as illustrated in the figures. Relative terms are used to describe different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in a drawing is turned over, elements will be described as being on the "lower" side of other elements as being oriented on "upper" sides of the other elements. The exemplary word "lower" may encompass both an orientation of "lower" and "upper" depending on the particular orientation of the figure.
To illustrate the crystallization process, please refer to fig. 1A to 1C, which are schematic cross-sectional views illustrating a semiconductor layer 100 according to an embodiment of the disclosure. As shown in fig. 1A, a semiconductor layer 100 is formed on a substrate 170. In one embodiment, the semiconductor layer 100 of fig. 1A is Amorphous (amophorus). Due to the influence of the partially-transmissive (Semi-transmissive) region 152 of the mask 150, light of the Flash lamp (Flash lamp)160 passing through the partially-transmissive region 152 is attenuated to be irradiated to a portion of the semiconductor layer 100. The region of the mask 150 other than the partially transparent region 152 is a transparent region. The light of the flash lamp 160 passing through the light transmission region is not attenuated and is irradiated to another portion of the semiconductor layer 100.
As shown in fig. 1B, the first portion 110 of the semiconductor layer 100 corresponds to a portion of the light-transmitting region 152 of the mask 150, and is irradiated by the attenuated light from the flash lamp 160, so as to be transformed into a Semi-molten (Semi-fusion) state. The second portion 120 of the semiconductor layer 100, corresponding to the light-transmitting region of the mask 150 (i.e., the region outside the partial light-transmitting region 152), is directly irradiated by the flash lamp 160 and is transformed into a molten (Fusion) state.
As shown in fig. 1C, the flash lamp 160 stops irradiation, and the second portion 120 in a molten state starts crystallization (as indicated by a dotted arrow in fig. 1C) from the junction of the first portion 110 and the second portion 120 to form the second crystalline portion 140. The semi-molten first portion 110 also simultaneously rearranges the crystal lattice to form a first crystalline portion 130. In one embodiment, the first crystalline portion 130 includes a Micro-crystalline (Micro-crystalline) portion and the second crystalline portion 140 includes a lateral crystalline (Lateracrystalization) portion.
Thus, compared to Excimer Laser Annealing (ELA), the present disclosure can achieve larger area crystallization by using flash lamp and mask irradiation, and the crystallization quality is also better. Specifically, the Crystal grains (Crystal grains) in the crystalline portions (e.g., the first crystalline portion 130 and the second crystalline portion 140) of the semiconductor layer 100 of the present disclosure have a large size (e.g., micrometer (μm) level) and a highly uniform arrangement (e.g., lateral crystallization). In addition, the present disclosure can achieve different crystalline characteristics, such as lateral crystallization and micro-crystallization characteristics, of different portions of the semiconductor layer 100 of the same material by only one irradiation of the flash lamp 160 through the mask 150.
In practice, the partially transparent region 152 can be designed to be absorptive to attenuate the intensity of the transmitted light without changing its spectrum. Alternatively, the partially transparent region 152 may be designed to be light-filtering to absorb a specific wavelength band of the transmitted light, so as to change the spectrum of the transmitted light.
In one embodiment, the partial transparent regions 152 of the mask may be changed to Opaque (Opaque) regions according to actual design requirements, so that the corresponding portions of the semiconductor layer 100 remain in an original state (e.g., amorphous state) without being irradiated by the flash lamp 160. In another embodiment, the mask 150 includes transparent regions, partially transparent regions and/or opaque regions, so that crystalline regions can be formed, and specific regions in a micro-crystalline state and/or an amorphous state can also be formed.
For example, a specific region in an amorphous state can be formed through an opaque region of the mask 150, wherein the shortest distance from the center point to any side of the opaque region is greater than 10 micrometers (μm); the specific regions in the micro-crystalline state can be formed through the partially transparent regions of the mask 150, wherein the shortest distance from the center point to any side of the partially transparent regions is greater than 10 micrometers (μm). For another example, the specific region in the micro-crystalline state can also be formed through the transparent region of the mask 150, wherein the shortest distance from the center point to any side of the transparent region is greater than 100 μm.
In practice, the mask 150 may be a light-cutting or reflecting material, device or structure with a specific pattern, which is disposed on the light path from the flash lamp 160 to the semiconductor layer 100. The mask 150 can be applied to a removable exposure machine system used in semiconductor industry or panel industry, but the disclosure is not limited thereto. The shape of the opening of the mask 150 may be a strip, a triangle, a quadrangle or any polygon, and may be adjusted according to the difference in thermal conductivity between the material to be crystallized and the substrate.
In one embodiment, to form the better crystallized regions, the width of the region formed by projecting the portion of the transparent region 152 or the opaque region of the mask 150 onto the semiconductor layer 100 is approximately in the range of 1 micrometer (μm) to 20 micrometers (μm).
In one embodiment, in order to form a better crystalline region, the shortest vertical distance from the center to either side of the open area must be greater than 1 micrometer (μm) and not greater than 100 micrometers (i.e., 1 micrometer (μm) < shortest vertical distance ≦ 100 micrometers (μm)).
As described above, the semiconductor layer 100 is irradiated with the flash lamp 160 through the mask 150 to form a crystalline portion. However, according to actual requirements, the semiconductor layer 100 may be irradiated with the flash lamp 160 for a second time (or more than two times) by using the same mask (e.g., the mask 150) or a different mask and appropriately adjusting the relative positions of the mask and the semiconductor layer 100, so as to further change the crystalline state and uniformity of the semiconductor layer 100.
FIG. 2 is a flow chart illustrating a method 200 of manufacturing in accordance with one embodiment of the present disclosure. The manufacturing method 200 has a plurality of steps S202 to S206, which can be applied to the semiconductor device 100 as illustrated in fig. 1A to 1C. It should be understood by those skilled in the art that the steps mentioned in the present embodiment, except for those specifically mentioned in the sequence, can be performed in any order, even simultaneously or partially simultaneously, according to the actual requirement. The specific implementation is as disclosed above, and will not be repeated here.
In step S202, the semiconductor layer is irradiated with the flash lamp and the first mask such that the first portion of the semiconductor layer becomes semi-molten and the second portion of the semiconductor layer becomes molten. The first mask comprises a part of light-transmitting area and a light-transmitting area, wherein the part of light-transmitting area corresponds to the first part, the light-transmitting area corresponds to the second part, and the first part is adjacent to the second part.
In step S204, the second portion is crystallized from the junction between the first portion and the second portion to form a second crystallized portion.
In step S206, the lattices of the first portion are rearranged to form a first crystalline portion.
The present disclosure can achieve a larger area of crystals by using the flash lamp and the mask irradiation, and the quality of the crystals is also better. Specifically, the Crystal grains (Crystal grains) in the crystalline portions (e.g., the first crystalline portion 130 and the second crystalline portion 140) of the semiconductor layer 100 of the present disclosure have a larger size (e.g., micrometer (μm) level) and a more uniform arrangement (e.g., lateral crystallization). In addition, the present disclosure can achieve different crystalline characteristics, such as lateral crystallization and micro-crystallization characteristics, of different portions of the semiconductor layer 100 of the same material by only one irradiation of the flash lamp 160 through the mask.
Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure, and therefore the scope of the present disclosure should be limited only by the terms of the appended claims.
Claims (10)
1. A method of semiconductor fabrication, the method comprising:
irradiating a semiconductor layer by using a flash lamp and a first photomask to enable a first part of the semiconductor layer to be in a semi-molten state and a second part of the semiconductor layer to be in a molten state, wherein the first photomask comprises a partial transparent area and a transparent area, the partial transparent area corresponds to the first part, the transparent area corresponds to the second part, and the first part is adjacent to the second part;
crystallizing the second portion from a junction of the first portion and the second portion to form a second crystallized portion; and
the crystal lattice of the first portion is rearranged to form a first crystalline portion.
2. The method of claim 1, wherein the first crystalline portion comprises a microcrystalline portion.
3. The semiconductor manufacturing method according to claim 1, wherein the second crystalline portion comprises a lateral crystalline portion.
4. The method of claim 1, wherein the first mask further comprises an opaque region corresponding to an amorphous portion of the semiconductor layer after the flash lamp and the first mask are used to irradiate the semiconductor layer.
5. The semiconductor manufacturing method according to claim 1, further comprising:
irradiating the semiconductor layer with the flash lamp and a second mask to change a crystalline state of the semiconductor layer.
6. A semiconductor layer, comprising:
a first crystallized portion crystallized from a first semi-molten portion; and
a second crystallized portion formed by crystallizing a molten second portion,
wherein the first part in the semi-molten state and the second part in the molten state are formed by irradiating the first part and the second part with a flash lamp through a first mask, the first mask comprises a part of light-transmitting area and a light-transmitting area, the part of light-transmitting area corresponds to the first part, the light-transmitting area corresponds to the second part, and the first part is adjacent to the second part; the second crystal portion is formed by crystallizing the second portion from a junction of the first portion and the second portion, and the first crystal portion is formed by rearranging the crystal lattice of the first portion.
7. The semiconductor layer of claim 6, wherein the first crystalline portion comprises a microcrystalline portion.
8. The semiconductor layer of claim 6, wherein the second crystalline portion comprises a lateral crystalline portion.
9. The semiconductor layer of claim 6, further comprising:
an amorphous portion formed by the flash lamp irradiating the semiconductor layer through the first mask, wherein the first mask further comprises an opaque region corresponding to the amorphous portion.
10. The semiconductor layer of claim 6 wherein the flash lamp irradiates the semiconductor layer through a second mask to change a crystalline state of the semiconductor layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811234234.7A CN111092015A (en) | 2018-10-23 | 2018-10-23 | Semiconductor manufacturing method and semiconductor layer |
| TW108119781A TW202017052A (en) | 2018-10-23 | 2019-06-06 | Semiconductor manufacturing method and semiconductor film |
| TW108207256U TWM585986U (en) | 2018-10-23 | 2019-06-06 | Semiconductor film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811234234.7A CN111092015A (en) | 2018-10-23 | 2018-10-23 | Semiconductor manufacturing method and semiconductor layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111092015A true CN111092015A (en) | 2020-05-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811234234.7A Withdrawn CN111092015A (en) | 2018-10-23 | 2018-10-23 | Semiconductor manufacturing method and semiconductor layer |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111092015A (en) |
| TW (2) | TW202017052A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040161676A1 (en) * | 2002-07-24 | 2004-08-19 | Yukio Taniguchi | Crystallization apparatus, crystallization method, thin film transistor and display apparatus |
| US20050014315A1 (en) * | 2003-06-03 | 2005-01-20 | Yoshitaka Yamamoto | Method and apparatus for forming crystallized semiconductor layer, and method for manufacturing semiconductor apparatus |
| CN1614745A (en) * | 2004-11-25 | 2005-05-11 | 友达光电股份有限公司 | Method for preparing polycrystalline silicon layer and light shield |
| CN205376471U (en) * | 2015-12-17 | 2016-07-06 | 宸鸿光电科技股份有限公司 | Semiconductor layer |
| WO2016106881A1 (en) * | 2014-12-31 | 2016-07-07 | 深圳市华星光电技术有限公司 | Method for manufacturing array substrate |
| CN106898540A (en) * | 2015-12-17 | 2017-06-27 | 宸鸿光电科技股份有限公司 | Semiconductor making method and semiconductor layer |
| CN208954937U (en) * | 2018-10-23 | 2019-06-07 | 宸鸿光电科技股份有限公司 | Semiconductor layer |
-
2018
- 2018-10-23 CN CN201811234234.7A patent/CN111092015A/en not_active Withdrawn
-
2019
- 2019-06-06 TW TW108119781A patent/TW202017052A/en unknown
- 2019-06-06 TW TW108207256U patent/TWM585986U/en unknown
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040161676A1 (en) * | 2002-07-24 | 2004-08-19 | Yukio Taniguchi | Crystallization apparatus, crystallization method, thin film transistor and display apparatus |
| US20050014315A1 (en) * | 2003-06-03 | 2005-01-20 | Yoshitaka Yamamoto | Method and apparatus for forming crystallized semiconductor layer, and method for manufacturing semiconductor apparatus |
| CN1614745A (en) * | 2004-11-25 | 2005-05-11 | 友达光电股份有限公司 | Method for preparing polycrystalline silicon layer and light shield |
| WO2016106881A1 (en) * | 2014-12-31 | 2016-07-07 | 深圳市华星光电技术有限公司 | Method for manufacturing array substrate |
| CN205376471U (en) * | 2015-12-17 | 2016-07-06 | 宸鸿光电科技股份有限公司 | Semiconductor layer |
| CN106898540A (en) * | 2015-12-17 | 2017-06-27 | 宸鸿光电科技股份有限公司 | Semiconductor making method and semiconductor layer |
| CN208954937U (en) * | 2018-10-23 | 2019-06-07 | 宸鸿光电科技股份有限公司 | Semiconductor layer |
Also Published As
| Publication number | Publication date |
|---|---|
| TWM585986U (en) | 2019-11-01 |
| TW202017052A (en) | 2020-05-01 |
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