CN111092019B - 一种指纹识别模块及其制备方法 - Google Patents

一种指纹识别模块及其制备方法 Download PDF

Info

Publication number
CN111092019B
CN111092019B CN201911158131.1A CN201911158131A CN111092019B CN 111092019 B CN111092019 B CN 111092019B CN 201911158131 A CN201911158131 A CN 201911158131A CN 111092019 B CN111092019 B CN 111092019B
Authority
CN
China
Prior art keywords
fingerprint identification
layer
substrate
forming
identification chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911158131.1A
Other languages
English (en)
Other versions
CN111092019A (zh
Inventor
王桥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Heilongjiang Junrong E-commerce Co.,Ltd.
Original Assignee
Suihua Hongjun Intelligent Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suihua Hongjun Intelligent Technology Co ltd filed Critical Suihua Hongjun Intelligent Technology Co ltd
Priority to CN201911158131.1A priority Critical patent/CN111092019B/zh
Publication of CN111092019A publication Critical patent/CN111092019A/zh
Application granted granted Critical
Publication of CN111092019B publication Critical patent/CN111092019B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134—Bonding interfaces of the bump connector
    • H01L2224/81345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Measurement Of The Respiration, Hearing Ability, Form, And Blood Characteristics Of Living Organisms (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)

Abstract

本发明涉及一种指纹识别模块的制备方法，其方法包括：提供具有相对的第一表面以及第二表面衬底；在所述衬底的第一表面上形成第一介质层以及导电布线层；在所述第一介质层中形成一开槽区；在所述导电布线层上形成导电金属柱；提供一载板，在所述载板上设置离型膜以及指纹识别芯片；在所述载板上形成挡墙结构，并在指纹识别功能区上粘结一弹性缓冲层；在所述导电布线层中与所述焊盘对应的区域设置焊球，接着将所述指纹识别芯片设置于所述导电布线层上，使得所述弹性缓冲层嵌入到所述开槽区，并通过回流焊工艺使得焊球融化进而嵌入到相应的所述挡墙结构中；在所述衬底上形成塑封层，自所述衬底的第二表面减薄所述衬底。

Description

一种指纹识别模块及其制备方法
技术领域
本发明涉及半导体封装领域，特别是涉及一种指纹识别模块及其制备方法。
背景技术
在现有的生物识别模块中，通常是在生物识别芯片上形成硬质的封装材料层，然后减薄该封装材料层，然后在减薄后的封装材料层上设置保护盖板。现有的生物识别模块在使用过程中，由于长期多次的按压该生物识别模块，在按压力的作用下容易损坏生物识别芯片的功能区。
发明内容
本发明的目的是克服上述现有技术的不足，提供一种指纹识别模块及其制备方法。
为实现上述目的，本发明采用的技术方案是：
一种指纹识别模块的制备方法，包括以下步骤：1)提供一衬底，所述衬底具有相对的第一表面以及第二表面；2)在所述衬底的第一表面上形成第一介质层，在所述第一介质层上形成导电布线层；3)所述第一介质层中与指纹识别芯片的竖直方向对应区域的介质材料被去除，进而形成一开槽区；4)接着在所述导电布线层上形成光刻胶层，通过光刻工艺去除部分的所述光刻胶层以形成多个贯穿孔，以暴露部分的所述导电布线层，并在所述贯穿孔内形成导电金属柱；5)提供一载板，在所述载板上设置一离型膜，在所述离型膜上设置指纹识别芯片，所述指纹识别芯片的正面设置有指纹识别功能区以及焊盘；6)在所述载板上形成光刻胶层以覆盖所述指纹识别芯片，通过光刻工艺在所述指纹识别芯片的所述焊盘的两侧形成沟槽；7)在所述沟槽中填充金属材料以在所述焊盘的两侧形成挡墙结构，并去除所述光刻胶层，接着在所述指纹识别功能区上粘结一弹性缓冲层；8)在所述导电布线层中与所述焊盘对应的区域设置焊球，接着将所述指纹识别芯片设置于所述导电布线层上，使得所述弹性缓冲层嵌入到所述开槽区，并通过回流焊工艺使得焊球融化进而嵌入到相应的所述挡墙结构中；9)将所述离型膜以及所述载板与所述指纹识别芯片分离，接着在所述衬底上形成塑封层，所述塑封层完全包覆所述指纹识别芯片以及所述导电线路层，并暴露所述导电金属柱；10)自所述衬底的第二表面减薄所述衬底。
进一步的，在所述步骤1)中，所述衬底的材质为玻璃、陶瓷、塑料或者硅。
进一步的，在所述步骤2)中，所述第一介质层的材料为氮化硅、氮氧化硅、氧化硅、碳化硅、氧化铝、氮化铝中的一种或多种，所述导电布线层的材质为金、银、铜、铝、钛、镍、钯中的一种或多种；在所述步骤4)中，导电金属柱的材料为金、银、铜、铝、钛、镍、钯中的一种或多种。
进一步的，在所述步骤7)中，所述挡墙结构的金属材料为金、银、铜、铝、钛、镍、钯中的一种或多种；所述弹性缓冲层的材质为天然橡胶、丁苯橡胶、丁腈橡胶、硅橡胶、热塑性聚氨酯弹性体、苯乙烯系热塑性弹性体、三元乙丙橡胶中的一种，所述弹性缓冲层的厚度为800-1600微米。
进一步的，在所述步骤9)中，所述塑封层的材料为环氧树脂。
进一步的，在所述步骤10)中，减薄后的衬底的厚度为所述100-300微米。
本发明还提出一种指纹识别模块，其采用上述方法制备形成的。
本发明与现有技术相比具有下列优点：
在本发明的指纹识别模块的制备方法中，通过在指纹识别功能区上粘结一弹性缓冲层，进而将所述指纹识别芯片设置在衬底上，使得弹性缓冲层嵌入到开槽区，该指纹识别模块在使用过程中，弹性缓冲层的存在可以确保其在多次按压情况下指纹识别芯片也不会损坏。通过在指纹识别芯片的焊盘两侧形成挡墙结构，进而在回流焊工艺使得焊球融化进而嵌入到相应的所述挡墙结构中，确保了生物识别芯片与衬底精确对位，且有效避免焊料溢出而损坏指纹识别功能区。通过减薄所述衬底，并进一步优化减薄后的衬底的厚度，可以确保该指纹识别模块工作灵敏。
附图说明
图1-图9为本发明的指纹识别模块的制备过程中各步骤的结构示意图。
具体实施方式
如图1-图9所示，一种指纹识别模块的制备方法，包括以下步骤：
如图1所示，在步骤1)中，提供一衬底101，所述衬底具有相对的第一表面以及第二表面；在步骤2)中，在所述衬底101的第一表面上形成第一介质层102，在所述第一介质层102上形成导电布线层103；
所述衬底101的材质为玻璃、陶瓷、塑料或者硅。所述第一介质层102的材料为氮化硅、氮氧化硅、氧化硅、碳化硅、氧化铝、氮化铝中的一种或多种，所述第一介质层102可以为单层或多层结构，所述第一介质层102的制备方法为PECVD法、ALD法或热氧化法，所述导电布线层103的材质为金、银、铜、铝、钛、镍、钯中的一种或多种，所述导电布线层103的制备方法为CVD、热蒸镀、磁控溅射、电镀、化学镀以及电子束蒸镀中的一种。
如图2所示，在步骤3)中，所述第一介质层102中与指纹识别芯片的竖直方向对应区域的介质材料被去除，进而形成一开槽区1021。
如图3所示，在步骤4)中，接着在所述导电布线层103上形成光刻胶层201，通过光刻工艺去除部分的所述光刻胶层以形成多个贯穿孔，以暴露部分的所述导电布线层103，并在所述贯穿孔内形成导电金属柱301。
其中，导电金属柱301的材料为金、银、铜、铝、钛、镍、钯中的一种或多种，所述导电金属柱301的制备方法为CVD、热蒸镀、磁控溅射、电镀、化学镀以及电子束蒸镀中的一种。
如图4所示，在步骤5)中，提供一载板401，在所述载板401上设置一离型膜402，在所述离型膜402上设置指纹识别芯片403，所述指纹识别芯片403的正面设置有指纹识别功能区404以及焊盘405。
其中，所述载板401的材质为玻璃、硅、锗、陶瓷中的一种，所述离型膜402在激光照射下会失去粘性，进而方便生物识别芯片403与载板401的分离。
如图5所示，在步骤6)中，在所述载板401上形成光刻胶层501以覆盖所述指纹识别芯片403，通过光刻工艺在所述指纹识别芯片403的所述焊盘405的两侧形成沟槽502。
如图6所示，在步骤7)中，在所述沟槽502中填充金属材料以在所述焊盘405的两侧形成挡墙结构601，并去除所述光刻胶层，接着在所述指纹识别功能区404上粘结一弹性缓冲层701。
所述挡墙结构601的金属材料为金、银、铜、铝、钛、镍、钯中的一种或多种；所述挡墙结构601的制备方法为CVD、热蒸镀、磁控溅射、电镀、化学镀以及电子束蒸镀中的一种，所述弹性缓冲层701的材质为天然橡胶、丁苯橡胶、丁腈橡胶、硅橡胶、热塑性聚氨酯弹性体、苯乙烯系热塑性弹性体、三元乙丙橡胶中的一种，所述弹性缓冲层701的厚度为800-1600微米。
如图7所示，在步骤8)中，在所述导电布线层103中与所述焊盘405对应的区域设置焊球801，接着将所述指纹识别芯片403设置于所述导电布线层103上，使得所述弹性缓冲层701嵌入到所述开槽区1021，并通过回流焊工艺使得焊球801融化进而嵌入到相应的所述挡墙结构601中.
如图8所示，在步骤9)中，将所述离型膜402以及所述载板401与所述指纹识别芯片403分离，接着在所述衬底101上形成塑封层901，所述塑封层901完全包覆所述指纹识别芯片403以及所述导电线路层103，并暴露所述导电金属柱301。所述塑封层901的材料为环氧树脂。
如图9所示，在步骤10)中，自所述衬底101的第二表面减薄所述衬底101，减薄后的衬底101的厚度为所述100-300微米。
本发明还公开一种利用上述方法制备的指纹识别模块。
如上所述，本发明的指纹识别模块及其制备方法与现有技术相比具有下列优点：
在本发明的指纹识别模块的制备方法中，通过在指纹识别功能区上粘结一弹性缓冲层，进而将所述指纹识别芯片设置在衬底上，使得弹性缓冲层嵌入到开槽区，该指纹识别模块在使用过程中，弹性缓冲层的存在可以确保其在多次按压情况下指纹识别芯片也不会损坏。通过在指纹识别芯片的焊盘两侧形成挡墙结构，进而在回流焊工艺使得焊球融化进而嵌入到相应的所述挡墙结构中，确保了生物识别芯片与衬底精确对位，且有效避免焊料溢出而损坏指纹识别功能区。通过减薄所述衬底，并进一步优化减薄后的衬底的厚度，可以确保该指纹识别模块工作灵敏。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (6)

1.一种指纹识别模块的制备方法，其特征在于：包括以下步骤：
1)提供一衬底，所述衬底具有相对的第一表面以及第二表面；
2)在所述衬底的第一表面上形成第一介质层，在所述第一介质层上形成导电布线层；
3)所述第一介质层中与指纹识别芯片的竖直方向对应区域的介质材料被去除，进而形成一开槽区；
4)接着在所述导电布线层上形成光刻胶层，通过光刻工艺去除部分的所述光刻胶层以形成多个贯穿孔，以暴露部分的所述导电布线层，并在所述贯穿孔内形成导电金属柱；
5)提供一载板，在所述载板上设置一离型膜，在所述离型膜上设置指纹识别芯片，所述指纹识别芯片的正面设置有指纹识别功能区以及焊盘；
6)在所述载板上形成光刻胶层以覆盖所述指纹识别芯片，通过光刻工艺在所述指纹识别芯片的所述焊盘的两侧形成沟槽；
7)在所述沟槽中填充金属材料以在所述焊盘的两侧形成挡墙结构，并去除所述光刻胶层，接着在所述指纹识别功能区上粘结一弹性缓冲层，其中，所述挡墙结构的金属材料为金、银、铜、铝、钛、镍、钯中的一种或多种；所述弹性缓冲层的材质为天然橡胶、丁苯橡胶、丁腈橡胶、硅橡胶、热塑性聚氨酯弹性体、苯乙烯系热塑性弹性体、三元乙丙橡胶中的一种，所述弹性缓冲层的厚度为800-1600微米；
8)在所述导电布线层中与所述焊盘对应的区域设置焊球，接着将所述指纹识别芯片设置于所述导电布线层上，使得所述弹性缓冲层嵌入到所述开槽区，并通过回流焊工艺使得焊球融化进而嵌入到相应的所述挡墙结构中；
9)将所述离型膜以及所述载板与所述指纹识别芯片分离，接着在所述衬底上形成塑封层，所述塑封层完全包覆所述指纹识别芯片以及所述导电线路层，并暴露所述导电金属柱；
10)自所述衬底的第二表面减薄所述衬底。
2.根据权利要求1所述的指纹识别模块的制备方法，其特征在于：在所述步骤1)中，所述衬底的材质为玻璃、陶瓷、塑料或者硅。
3.根据权利要求1所述的指纹识别模块的制备方法，其特征在于：在所述步骤2)中，所述第一介质层的材料为氮化硅、氮氧化硅、氧化硅、碳化硅、氧化铝、氮化铝中的一种或多种，所述导电布线层的材质为金、银、铜、铝、钛、镍、钯中的一种或多种；在所述步骤4)中，导电金属柱的材料为金、银、铜、铝、钛、镍、钯中的一种或多种。
4.根据权利要求1所述的指纹识别模块的制备方法，其特征在于：在所述步骤9)中，所述塑封层的材料为环氧树脂。
5.根据权利要求1所述的指纹识别模块的制备方法，其特征在于：在所述步骤10)中，减薄后的衬底的厚度为所述100-300微米。
6.一种指纹识别模块，其特征在于，采用权利要求1-5任一项所述的方法制备形成的。
CN201911158131.1A 2019-11-22 2019-11-22 一种指纹识别模块及其制备方法 Active CN111092019B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911158131.1A CN111092019B (zh) 2019-11-22 2019-11-22 一种指纹识别模块及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911158131.1A CN111092019B (zh) 2019-11-22 2019-11-22 一种指纹识别模块及其制备方法

Publications (2)

Publication Number Publication Date
CN111092019A CN111092019A (zh) 2020-05-01
CN111092019B true CN111092019B (zh) 2021-11-02

Family

ID=70393480

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911158131.1A Active CN111092019B (zh) 2019-11-22 2019-11-22 一种指纹识别模块及其制备方法

Country Status (1)

Country Link
CN (1) CN111092019B (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007114126A (ja) * 2005-10-21 2007-05-10 Fujitsu Ltd 半導体装置及びその製造方法
CN106816417A (zh) * 2017-01-13 2017-06-09 南京大学 一种高密度封装及其制造方法
CN107146779A (zh) * 2017-06-30 2017-09-08 中芯长电半导体（江阴）有限公司 指纹识别芯片的封装结构及封装方法
CN110164859A (zh) * 2019-06-11 2019-08-23 中芯长电半导体（江阴）有限公司 扇出型指纹识别芯片的封装结构及封装方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101308802A (zh) * 2007-05-15 2008-11-19 矽品精密工业股份有限公司 感测式半导体装置及其制法
CN203895460U (zh) * 2014-05-20 2014-10-22 苏州晶方半导体科技股份有限公司 一种封装结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007114126A (ja) * 2005-10-21 2007-05-10 Fujitsu Ltd 半導体装置及びその製造方法
CN106816417A (zh) * 2017-01-13 2017-06-09 南京大学 一种高密度封装及其制造方法
CN107146779A (zh) * 2017-06-30 2017-09-08 中芯长电半导体（江阴）有限公司 指纹识别芯片的封装结构及封装方法
CN110164859A (zh) * 2019-06-11 2019-08-23 中芯长电半导体（江阴）有限公司 扇出型指纹识别芯片的封装结构及封装方法

Also Published As

Publication number Publication date
CN111092019A (zh) 2020-05-01

Similar Documents

Publication Publication Date Title
US11037819B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
CN210006732U (zh) 芯片封装结构
US7919833B2 (en) Semiconductor package having a crack-propagation preventing unit
CN106206625B (zh) 一种芯片尺寸等级的感测芯片封装体及其制造方法
KR100886717B1 (ko) 적층 반도체 패키지 및 이의 제조 방법
US9984900B2 (en) Semiconductor device including at least one element
TWI575779B (zh) 晶片封裝體及其製造方法
KR20040092435A (ko) 반도체 장치 및 그 제조 방법
US7163846B2 (en) Method for manufacturing circuit devices
US20230245923A1 (en) Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method
US9334158B2 (en) Chip package and method for forming the same
KR100662686B1 (ko) 회로 장치 및 그 제조 방법
CN111029261B (zh) 一种生物识别模块及其制备方法
KR100637819B1 (ko) 혼성 집적 회로 장치 및 그 제조 방법
CN111092019B (zh) 一种指纹识别模块及其制备方法
JP2013211365A (ja) 集積化デバイス
KR101319441B1 (ko) 리드프레임
JP2006237503A (ja) 半導体装置およびその製造方法
KR100381349B1 (ko) 판형체, 리드 프레임 및 반도체 장치의 제조 방법
CN106847788B (zh) 具有边缘保护的晶片级芯片尺寸封装体(wlcsp)
JP2004207278A (ja) 回路装置およびその製造方法
US20180166390A1 (en) Planar package structure and manufacturing method thereof
KR102008803B1 (ko) 칩 패키지용 기판 및 그 제조방법
CN111883439B (zh) 一种芯片封装方法
US20230307268A1 (en) Structures and methods of transferring dies and die bonded structures

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20211014

Address after: 152001 No. 18, Huanghe South Road, Beilin District, Suihua City, Heilongjiang Province (inside Suihua University)

Applicant after: Suihua Hongjun Intelligent Technology Co.,Ltd.

Address before: 221000 room 209, Quanshan science and technology building, National University Science Park, China University of mining and technology, north of Jinshan East Road, Xuzhou City, Jiangsu Province

Applicant before: Xuzhou Shunyi Semiconductor Technology Co.,Ltd.

GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240511

Address after: No. 14, Shangfu, Hongxingyuan South District, Huanghe North Road, Beilin District, Suihua City, Heilongjiang Province, 152000 (2702-006-108)

Patentee after: Heilongjiang Junrong E-commerce Co.,Ltd.

Country or region after: China

Address before: 152001 No. 18, Huanghe South Road, Beilin District, Suihua City, Heilongjiang Province (inside Suihua University)

Patentee before: Suihua Hongjun Intelligent Technology Co.,Ltd.

Country or region before: China