CN110164859A - 扇出型指纹识别芯片的封装结构及封装方法 - Google Patents
扇出型指纹识别芯片的封装结构及封装方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000012545 processing Methods 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 230000008878 coupling Effects 0.000 claims abstract description 13
- 238000010168 coupling process Methods 0.000 claims abstract description 13
- 238000005859 coupling reaction Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 137
- 239000000758 substrate Substances 0.000 claims description 33
- 229910000679 solder Inorganic materials 0.000 claims description 21
- 238000005538 encapsulation Methods 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 17
- 239000003822 epoxy resin Substances 0.000 claims description 13
- 229920000647 polyepoxide Polymers 0.000 claims description 13
- 230000009466 transformation Effects 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000004642 Polyimide Substances 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 7
- 229920001721 polyimide Polymers 0.000 claims description 7
- 239000000741 silica gel Substances 0.000 claims description 7
- 229910002027 silica gel Inorganic materials 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 230000005496 eutectics Effects 0.000 claims description 6
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 6
- 230000006835 compression Effects 0.000 claims description 5
- 238000007906 compression Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 229920000307 polymer substrate Polymers 0.000 claims description 3
- 238000001721 transfer moulding Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000000392 somatic effect Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
-
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
本发明提供一种扇出型指纹识别芯片的封装结构及封装方法,结构包括:重新布线层;指纹采集芯片,接合于重新布线层的第一面,指纹采集芯片的电极与重新布线层连接;封装层,包覆指纹采集芯片的侧面,指纹采集芯片的顶面显露于封装层;指纹处理芯片,接合于重新布线层的第二面,指纹处理芯片通过重新布线层与指纹采集芯片连接;金属凸块,形成于重新布线层的第二面,以通过重新布线层实现指纹处理芯片的电性引出。本发明采用扇出型封装指纹识别芯片,可将指纹采集芯片及指纹处理芯片集成在同一封装结构中,且指纹采集芯片及指纹处理芯片为垂直设置,相比于现有的其它指纹识别芯片封装来说,具有成本低、厚度小、良率高的优点。
Description
技术领域
本发明属于半导体封装领域,特别是涉及一种扇出型指纹识别芯片的封装结构及封装方法。
背景技术
随着集成电路的功能越来越强、性能和集成度越来越高,以及新型的集成电路出现,封装技术在集成电路产品中扮演着越来越重要的角色,在整个电子系统的价值中所占的比例越来越大。同时,随着集成电路特征尺寸达到纳米级,晶体管向更高密度、更高的时钟频率发展,封装也向更高密度的方向发展。
由于扇出晶圆级封装(fowlp)技术由于具有小型化、低成本和高集成度等优点,以及具有更好的性能和更高的能源效率,扇出晶圆级封装(fowlp)技术已成为高要求的移动/无线网络等电子设备的重要的封装方法,是目前最具发展前景的封装技术之一。
指纹识别技术是目前最成熟且价格便宜的生物特征识别技术。目前来说,指纹识别的技术应用最为广泛,不仅在门禁、考勤系统中可以看到指纹识别技术的身影,市场上有了更多指纹识别的应用:如笔记本电脑、手机、汽车、银行支付都可应用指纹识别的技术。
现有的一种指纹识别芯片的封装方法如图1a~图1c所示:
第一步,如图1a所示,在指纹识别芯片101制作深槽,并将其粘合于FPC板102上,然后通过打线工艺制作金属连线103,实现指纹识别芯片101与FP C板102的电连接,其中,FPC是Flexible Printed Circuit的简称,又称软性线路板,其具有配线密度高、重量轻、厚度薄的特点。
第二步,如图1b所示,制作出框架104;
第三步,士1c所示,在所述指纹识别芯片上加盖蓝宝石盖板105,以完成封装。
这种方法具有以下缺点:包括FPC板、指纹识别芯片以及蓝宝石盖板三层结构,封装厚度较厚,金属连线容易因FPC软板拉扯等造成断裂,整体良率较低。
另一种指纹识别芯片的封装方法如图2a~图2c所示:
第一步,如图2a所示,通过硅穿孔TSV技术在指纹识别芯片101中形成通孔电极106;
第二步,如图2b所示,将蓝宝石盖板105、指纹识别芯片101及FPC板102层叠在一起,通过打线工艺制作金属连线103以连接所述指纹识别芯片101及FPC板102;
第三步,如图2c所示,制作出框架104。
这种方法具有以下缺点:需要用蓝宝石盖板封装,厚度较厚,硅穿孔工艺成本较高,金属连线容易因FPC软板拉扯等造成断裂,而且指纹识别芯片的厚度较薄,容易出现裂片现象,整体良率较低。
基于以上所述,提供一种低成本、低厚度以及高封装良率的指纹识别芯片的封装结构及封装方法实属必要。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种扇出型指纹识别芯片的封装结构及封装方法,用于解决现有技术中指纹识别封装厚度较大、封装成本较高的问题。
为实现上述目的及其他相关目的,本发明提供一种扇出型指纹识别芯片的封装结构,所述封装结构包括:重新布线层,所述重新布线层包括第一面以及相对的第二面;指纹采集芯片,接合于重新布线层的第一面,所述指纹采集芯片的电极与所述重新布线层连接;封装层,包覆所述指纹采集芯片的侧面,所述指纹采集芯片的顶面显露于所述封装层;指纹处理芯片,接合于所述重新布线层的第二面,所述指纹处理芯片通过所述重新布线层与所述指纹采集芯片连接;金属凸块,形成于所述重新布线层的第二面,以通过所述重新布线层实现所述指纹处理芯片的电性引出。
可选地,所述指纹采集芯片与所述指纹处理芯片在垂直方向上重合设置。
可选地,所述指纹处理芯片与所述重新布线层之间具有间隙,所述间隙中形成有保护层,所述保护层完全填充所述间隙。
可选地,所述保护层选用为环氧树脂。
可选地,所述封装层包括聚酰亚胺、硅胶以及环氧树脂中的一种。
可选地,所述金属凸块包括锡焊料、银焊料及金锡合金焊料中的一种。
本发明还提供一种扇出型指纹识别芯片的封装方法,包括步骤:1)提供一支撑基底,于所述支撑基底上形成分离层;2)提供指纹采集芯片,将所述指纹采集芯片固定于所述分离层,所述指纹采集芯片的电极朝向所述分离层;3)采用封装层封装所述指纹采集芯片,所述指纹采集芯片的顶面显露于所述封装层;4)基于所述分离层剥离所述指纹采集芯片及所述支撑基底,露出所述封装层及所述指纹采集芯片的电极;5)在所述封装层及所述指纹采集芯片上制作重新布线层,所述重新布线层的第一面与所述指纹采集芯片的电极连接;6)提供一指纹处理芯片,将所述指纹处理芯片接合于所述重新布线层的第二面,所述指纹处理芯片通过所述重新布线层与所述指纹采集芯片连接;7)于所述重新布线层的第二面形成金属凸块,以通过所述重新布线层实现所述指纹处理芯片的电性引出。
可选地,所述指纹采集芯片与所述指纹处理芯片在垂直方向上重合设置。
可选地,所述支撑基底包括玻璃衬底、金属衬底、半导体衬底、聚合物衬底及陶瓷衬底中的一种。
可选地,所述分离层包括光热转换层,步骤4)采用激光照射所述光热转换层,以使所述光热转换层与所述封装层及所述支撑基底分离,进而剥离所述封装层及所述支撑基底。
可选地,步骤6)中,通过金属焊点将所述指纹处理芯片装设于所述重新布线层上后,所述指纹处理芯片与所述重新布线层之间具有间隙,步骤6)还包括于所述间隙中形成保护层的步骤,所述保护层完全填充所述间隙。
可选地,所述保护层选用为环氧树脂,采用点胶或者模压的方式形成于所述指纹处理芯片与所述重新布线层之间的间隙。
可选地,采用封装层封装所述指纹处理芯片的方法包括压缩成型、传递模塑成型、液封成型、真空层压及旋涂中的一种,所述封装层包括聚酰亚胺、硅胶以及环氧树脂中的一种。
可选地,所述金属凸块包括锡焊料、银焊料及金锡合金焊料中的一种。
如上所述,本发明的扇出型指纹识别芯片的封装结构及封装方法,具有以下有益效果:
1)本发明采用扇出型封装(Fan out)指纹识别芯片,可将指纹采集芯片及指纹处理芯片集成在同一封装结构中,且指纹采集芯片及指纹处理芯片为垂直设置,相比于现有的其它指纹识别芯片封装来说,具有成本低、厚度小、良率高的优点。
2)本发明同时不需要打线工艺,也不需要高成本的硅穿孔工艺(TSV),而能实现指纹识别芯片的封装,大大降低了工艺难度及成本。
3)本发明采用扇出封装(Fan out)工艺,芯片的电引出不需要传统的FPC板,可以降低封装的厚度以及电性引出结构的稳定性,提高封装良率。
附图说明
图1a~图1c显示为现有技术中的一种指纹识别芯片的封装方法各步骤所呈现的结构示意图。
图2a~图2c显示为现有技术中的另一种指纹识别芯片的封装方法各步骤所呈现的结构示意图。
图3~图10显示为本发明的扇出型指纹识别芯片的封装方法各步骤所呈现的结构示意图,其中,图10显示为本发明的扇出型指纹识别芯片的封装结构的结构示意图。
元件标号说明
201 支撑基底
202 分离层
203 指纹采集芯片
204 封装层
205 重新布线层
206 指纹处理芯片
207 保护层
208 金属凸块
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
如在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明保护的范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述,此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到,这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外,当一层被称为在两层“之间”时,它可以是所述两层之间仅有的层,或者也可以存在一个或多个介于其间的层。
在本申请的上下文中,所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。
需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。
如图3~图10所示,本实施例提供一种扇出型指纹识别芯片的封装方法,所述封装方法包括步骤:
如图3所示,首先进行步骤1),提供一支撑基底201,于所述支撑基底201上形成分离层202。
作为示例,所述支撑基底201包括玻璃衬底、金属衬底、半导体衬底、聚合物衬底及陶瓷衬底中的一种。在本实施例中,所述支撑基底201选用为玻璃衬底,所述玻璃衬底成本较低,容易在其表面形成分离层202,且能降低后续的剥离工艺的难度。
作为示例,所述分离层202包括光热转换层(LTHC),通过旋涂工艺形成于所述支撑基底201101上后,通过固化工艺使其固化成型。光热转换层(LTHC)性能稳定,表面较光滑,有利于后续获得平坦的,在后续的剥离工艺中,剥离的难度较低。
如图4所示,然后进行步骤2),提供指纹采集芯片203,将所述指纹采集芯片203固定于所述分离层202,所述指纹采集芯片203的电极朝向所述分离层202。
所述指纹采集芯片203用于采用人体指纹,并将采集信号传送至指纹处理芯片206进行处理。
如图5所示,接着进行步骤3),采用封装层204封装所述指纹采集芯片203,所述指纹采集芯片203的顶面显露于所述封装层204。
作为示例,采用封装层204封装所述指纹采集芯片203的方法包括压缩成型、传递模塑成型、液封成型、真空层压及旋涂中的一种,所述封装层204的材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
然后,还包括减薄所述封装层204,将所述指纹采集芯片203显露于所述封装层204的步骤,以提高所述指纹采集芯片203的采集精度。
如图6所示,然后进行步骤4),基于所述分离层202剥离所述指纹采集芯片203及所述支撑基底201,露出所述封装层204及所述指纹采集芯片203的电极。
具体地,所述分离层202为光热转换层,此处采用激光照射所述光热转换层,以使所述光热转换层与所述封装层204、指纹采集芯片203及所述支撑基底201分离,进而剥离指纹采集芯片203及所述支撑基底201,所述指纹采集芯片203的电极显露于剥离面,以利于后续重新布线层205的制作。
如图7所示,接着进行步骤5),在所述封装层204及所述指纹采集芯片203上制作重新布线层205,所述重新布线层205的第一面与所述指纹采集芯片203的电极连接。
所述重新布线层205可以包括若干介质层及若干依据图形需求排布的金属布线层,相邻两金属布线层之间通过导电栓塞连接。所述介质层的材料可以为环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃,含氟玻璃中的一种或两种以上组合。在本实施例中,所述介质层的材料可以为PI(聚酰亚胺),以进一步降低工艺难度以及工艺成本。所述金属布线层的材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。在本实施例中,所述金属布线层的材料为铜。
如图8~图9所示,然后进行步骤6),提供一指纹处理芯片206,将所述指纹处理芯片206接合于所述重新布线层205的第二面,所述指纹处理芯片206通过所述重新布线层205与所述指纹采集芯片203连接。所述指纹处理芯片206用于对所述指纹采集芯片203所采集的指纹信号进行特征提取及特征比对等处理,实现指纹识别功能。
在本实施例中,通过金属焊点将所述指纹处理芯片206装设于所述重新布线层205上后,所述指纹处理芯片206与所述重新布线层205之间具有间隙,本实施例还包括于所述间隙中形成保护层207的步骤,所述保护层207完全填充所述间隙。例如,所述保护层207选用为环氧树脂,可以采用点胶或者模压的方式形成于所述指纹处理芯片206与所述重新布线层205之间的间隙。所述保护层207可有效增加指纹处理芯片206与重新布线层205之间的结合强度和抗压强度。
优选地,将所述指纹处理芯片206接合于所述重新布线层205的第二面后,所述指纹采集芯片203与所述指纹处理芯片206在垂直方向上重合设置,该设置可大大节省封装结构的整体体积。
如图10所示,最后进行步骤7),于所述重新布线层205的第二面形成金属凸块208,以通过所述重新布线层205实现所述指纹处理芯片206的电性引出。
在本实施例中,所述金属凸块208包括锡焊料、银焊料及金锡合金焊料中的一种。
如图10所示,本实施例还提供一种扇出型指纹识别芯片的封装结构,所述封装结构包括:重新布线层205,所述重新布线层205包括第一面以及相对的第二面;指纹采集芯片203,接合于重新布线层205的第一面,所述指纹采集芯片203的电极与所述重新布线层205连接;封装层204,包覆所述指纹采集芯片203的侧面,所述指纹采集芯片203的顶面显露于所述封装层204;指纹处理芯片206,接合于所述重新布线层205的第二面,所述指纹处理芯片206通过所述重新布线层205与所述指纹采集芯片203连接;金属凸块208,形成于所述重新布线层205的第二面,以通过所述重新布线层205实现所述指纹处理芯片206的电性引出。
在本实施例中,所述指纹采集芯片203与所述指纹处理芯片206在垂直方向上重合设置,该设置可大大节省封装结构的整体体积。
所述指纹处理芯片206与所述重新布线层205之间具有间隙,所述间隙中形成有保护层207,所述保护层207完全填充所述间隙。例如,所述保护层207选用为环氧树脂。所述保护层207可有效增加指纹处理芯片206与重新布线层205之间的结合强度和抗压强度。
所述封装层204可以为聚酰亚胺、硅胶以及环氧树脂中的一种。所述金属凸块208可以为锡焊料、银焊料及金锡合金焊料中的一种。
如上所述,本发明的扇出型指纹识别芯片的封装结构及封装方法,具有以下有益效果:
1)本发明采用扇出型封装(Fan out)指纹识别芯片,可将指纹采集芯片203及指纹处理芯片206集成在同一封装结构中,且指纹采集芯片203及指纹处理芯片206为垂直设置,相比于现有的其它指纹识别芯片封装来说,具有成本低、厚度小、良率高的优点。
2)本发明同时不需要打线工艺,也不需要高成本的硅穿孔工艺(TSV),而能实现指纹识别芯片的封装,大大降低了工艺难度及成本。
3)本发明采用扇出封装(Fan out)工艺,芯片的电引出不需要传统的FPC板,可以降低封装的厚度以及电性引出结构的稳定性,提高封装良率。
所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (14)
1.一种扇出型指纹识别芯片的封装结构,其特征在于,所述封装结构包括:
重新布线层,所述重新布线层包括第一面以及相对的第二面;
指纹采集芯片,接合于重新布线层的第一面,所述指纹采集芯片的电极与所述重新布线层连接;
封装层,包覆所述指纹采集芯片的侧面,所述指纹采集芯片的顶面显露于所述封装层;
指纹处理芯片,接合于所述重新布线层的第二面,所述指纹处理芯片通过所述重新布线层与所述指纹采集芯片连接;
金属凸块,形成于所述重新布线层的第二面,以通过所述重新布线层实现所述指纹处理芯片的电性引出。
2.根据权利要求1所述的扇出型指纹识别芯片的封装结构,其特征在于:所述指纹采集芯片与所述指纹处理芯片在垂直方向上重合设置。
3.根据权利要求1所述的扇出型指纹识别芯片的封装结构,其特征在于:所述指纹处理芯片与所述重新布线层之间具有间隙,所述间隙中形成有保护层,所述保护层完全填充所述间隙。
4.根据权利要求3所述的扇出型指纹识别芯片的封装结构,其特征在于:所述保护层选用为环氧树脂。
5.根据权利要求1所述的扇出型指纹识别芯片的封装结构,其特征在于:所述封装层包括聚酰亚胺、硅胶以及环氧树脂中的一种。
6.根据权利要求1所述的扇出型指纹识别芯片的封装结构,其特征在于:所述金属凸块包括锡焊料、银焊料及金锡合金焊料中的一种。
7.一种扇出型指纹识别芯片的封装方法,其特征在于,包括步骤:
1)提供一支撑基底,于所述支撑基底上形成分离层;
2)提供指纹采集芯片,将所述指纹采集芯片固定于所述分离层,所述指纹采集芯片的电极朝向所述分离层;
3)采用封装层封装所述指纹采集芯片,所述指纹采集芯片的顶面显露于所述封装层;
4)基于所述分离层剥离所述指纹采集芯片及所述支撑基底,露出所述封装层及所述指纹采集芯片的电极;
5)在所述封装层及所述指纹采集芯片上制作重新布线层,所述重新布线层的第一面与所述指纹采集芯片的电极连接;
6)提供一指纹处理芯片,将所述指纹处理芯片接合于所述重新布线层的第二面,所述指纹处理芯片通过所述重新布线层与所述指纹采集芯片连接;
7)于所述重新布线层的第二面形成金属凸块,以通过所述重新布线层实现所述指纹处理芯片的电性引出。
8.根据权利要求7所述的扇出型指纹识别芯片的封装方法,其特征在于:所述指纹采集芯片与所述指纹处理芯片在垂直方向上重合设置。
9.根据权利要求7所述的扇出型指纹识别芯片的封装方法,其特征在于:所述支撑基底包括玻璃衬底、金属衬底、半导体衬底、聚合物衬底及陶瓷衬底中的一种。
10.根据权利要求7所述的扇出型指纹识别芯片的封装方法,其特征在于:所述分离层包括光热转换层,步骤4)采用激光照射所述光热转换层,以使所述光热转换层与所述封装层及所述支撑基底分离,进而剥离所述封装层及所述支撑基底。
11.根据权利要求7所述的扇出型指纹识别芯片的封装方法,其特征在于:步骤6)中,通过金属焊点将所述指纹处理芯片装设于所述重新布线层上后,所述指纹处理芯片与所述重新布线层之间具有间隙,步骤6)还包括于所述间隙中形成保护层的步骤,所述保护层完全填充所述间隙。
12.根据权利要求11所述的扇出型指纹识别芯片的封装方法,其特征在于:所述保护层选用为环氧树脂,采用点胶或者模压的方式形成于所述指纹处理芯片与所述重新布线层之间的间隙。
13.根据权利要求7所述的扇出型指纹识别芯片的封装方法,其特征在于:采用封装层封装所述指纹处理芯片的方法包括压缩成型、传递模塑成型、液封成型、真空层压及旋涂中的一种,所述封装层包括聚酰亚胺、硅胶以及环氧树脂中的一种。
14.根据权利要求7所述的扇出型指纹识别芯片的封装方法,其特征在于:所述金属凸块包括锡焊料、银焊料及金锡合金焊料中的一种。
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