CN111092017A - Method for manufacturing thin film element - Google Patents

Method for manufacturing thin film element Download PDF

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Publication number
CN111092017A
CN111092017A CN201811234230.9A CN201811234230A CN111092017A CN 111092017 A CN111092017 A CN 111092017A CN 201811234230 A CN201811234230 A CN 201811234230A CN 111092017 A CN111092017 A CN 111092017A
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China
Prior art keywords
layer
silicon
containing layer
metal layer
source
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CN201811234230.9A
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Chinese (zh)
Inventor
刘振宇
林熙乾
林建宏
刘正平
柯山文
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TPK Touch Solutions Inc
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TPK Touch Solutions Inc
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Priority to CN201811234230.9A priority Critical patent/CN111092017A/en
Priority to TW108119783A priority patent/TWI706466B/en
Publication of CN111092017A publication Critical patent/CN111092017A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H01L21/2686—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation using incoherent radiation

Abstract

A method for manufacturing a thin film element comprises forming a gate metal layer on a substrate, and forming a gate insulating layer on the gate metal layer. Then, at least one silicon-containing layer is formed on the grid insulation layer, then the flash lamp anneals the grid metal layer and the silicon-containing layer, and forms a source metal layer and a drain metal layer on the silicon-containing layer. The flash lamp annealing crystallization can emit high-energy flash light to the film in a large area at one time, and the amorphous silicon layer is crystallized when being subjected to enough light energy. The doped layer of the silicon-containing layer is connected with the source electrode-drain electrode metal layer and has better ohmic contact (ohmic contact) characteristics.

Description

Method for manufacturing thin film element
Technical Field
The present invention relates to a method for manufacturing a thin film device, and more particularly, to a method for manufacturing a back channel etched semiconductor thin film device.
Background
In order to simplify the fabrication of thin film transistors, Back Channel Etch (BCE) structures are currently a common process. In the fabrication of polysilicon transistors, amorphous (amorphous) silicon (a-Si) thin films are first formed and then converted into polycrystalline by laser annealing, and the amorphous silicon is irradiated with laser light to achieve conversion into a crystalline state. Excimer Laser Annealing (ELA), which is a pulsed laser having an ultraviolet wavelength range of 308 nm or shorter, is widely used at present as a laser for laser annealing, and produces granular crystals having a small particle size.
However, excimer laser annealing crystallization techniques are all limited by the length of the beam. For example, excimer laser annealing beams do not provide consistent beam properties across the entire width or length of a large area film. Thus, excimer laser annealing scanning can only be performed in a small block of film area, which must move the substrate in both the x and y directions to successfully process the film. Scanning in both the x and y directions not only increases process time, but it also produces inconsistencies between lower quality films with beam edges and multiple crystal scans, as compared to scanning smaller films.
In the back channel etching process, the gate metal layer is firstly manufactured, the surface of the transistor is fluctuated, and when excimer laser annealing is performed, the heating depth is limited and the uniformity of the coating is poor, so that the back channel etching process is not suitable for forming crystals on the amorphous semiconductor layer by excimer laser annealing. Moreover, the laser source is expensive, and especially the laser tube needs to be replaced regularly, which makes the use of the apparatus more expensive.
Disclosure of Invention
In view of the above problems, there is a need in the art for a method of annealing and crystallizing a transistor uniformly without suffering from surface roughness of the transistor. The invention provides a manufacturing method of a thin film element, which comprises the steps of forming a grid metal layer on a substrate and forming a grid insulating layer on the grid metal layer. Then, at least one silicon-containing layer is formed on the grid insulation layer, then the flash lamp anneals the grid metal layer and the silicon-containing layer, and forms a source metal layer and a drain metal layer on the silicon-containing layer.
According to some embodiments of the invention, the step of flash lamp annealing the silicon-containing layer further comprises: a source-drain insulating layer is formed on the silicon-containing layer and between the silicon-containing layer and the source-drain metal layer.
According to some embodiments of the present invention, the step of forming a silicon-containing layer on the gate insulation layer further comprises: at least one doped layer is formed on the silicon-containing layer.
According to some embodiments of the present invention, the step of forming a silicon-containing layer on the gate dielectric layer further comprises patterning the silicon-containing layer, wherein the step of patterning the silicon-containing layer comprises: forming a photoresist layer on the silicon-containing layer; lithographically etching the silicon-containing layer; and removing the photoresist layer.
According to some embodiments of the present invention, the method further comprises forming a source-drain insulating layer on the source-drain metal layer.
According to some embodiments of the present invention, the temperature ramp rate for flash lamp annealing is between 700 and 1300 ℃/sec.
According to some embodiments of the present invention, a wavelength range for flash lamp annealing is between 400-800 nm.
According to some embodiments of the present invention, a flash lamp annealed silicon-containing layer is formed on a gate insulation layer by chemical vapor deposition.
According to some embodiments of the present invention, the gate metal layer is a material selected from the group consisting of indium gallium zinc oxide, indium gallium zinc oxynitride, zinc oxide, zinc oxynitride, zinc tin oxide, cadmium tin oxide, gallium tin oxide, titanium tin oxide, copper aluminum oxide, strontium copper oxide, lanthanum copper oxysulfide, gallium nitride, indium gallium nitride, aluminum gallium nitride, and indium gallium aluminum nitride.
According to some embodiments of the present invention, the material of the source-drain metal layer is a material selected from the group consisting of copper, gold, silver, aluminum, tungsten, molybdenum, chromium, tantalum, titanium, and alloys or combinations thereof.
By flash lamp annealing the silicon-containing layer, which is originally amorphous silicon, can be better activated to crystallize the silicon-containing layer, and flash lamp annealing can complete the crystallization process in a large area and at one time, which is more efficient than a laser annealing process.
The flash lamp annealing crystallization can emit high-energy flash light to the film in a large area at one time, and the amorphous silicon layer is crystallized when being subjected to enough light energy. The doped layer of the silicon-containing layer is connected with the source electrode-drain electrode metal layer and has better ohmic contact (ohmic contact) characteristics.
Drawings
The foregoing and other aspects and features of the present invention will become more apparent by referring to the following description in conjunction with the accompanying drawings in which:
FIG. 1 is a flow chart of a method of fabricating a thin film element according to some embodiments of the present invention;
FIGS. 2A-2G are schematic cross-sectional views illustrating a method for fabricating a thin-film device according to some embodiments of the present invention;
FIG. 3 is a schematic cross-sectional view of a thin-film element according to some embodiments of the invention;
FIG. 4 is a schematic cross-sectional view of a thin-film element according to some embodiments of the invention;
FIG. 5 is a schematic cross-sectional view of a thin-film element according to some embodiments of the invention.
Detailed Description
In order to make the disclosure more complete and complete, the following description is provided for illustrative purposes of implementing aspects and embodiments of the invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The various embodiments disclosed below may be combined with or substituted for one another where appropriate, and additional embodiments may be added to one embodiment without further recitation or description. In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details.
The invention relates to a method for crystallizing an amorphous semiconductor layer by flash annealing in a thin film transistor manufactured by back channel etching. Please refer to fig. 1. FIG. 1 is a flow chart of a method for fabricating a thin film device according to some embodiments of the present invention. Step S110 is to form a gate metal active layer on a substrate. Please refer to fig. 2A. FIG. 2A is a cross-sectional view of a thin-film device fabrication method according to some embodiments of the present invention. First, a substrate 210 is provided, wherein the substrate 210 may be glass, plastic, or metal. Please refer to fig. 2B. FIG. 2B is a cross-sectional view of a thin-film device fabrication method according to some embodiments of the present invention. The gate metal layer 220 is formed on the upper surface of the substrate 210. The metal layer is typically formed by a physical vapor deposition procedure such as: sputtered) is formed on the substrate 210 and patterned to form a gate metal layer 220.
The gate metal layer 220 may be made of a material selected from the group consisting of indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN).
The element structure of the transistor may be an inverted-staggered (also referred to as a bottom-gate) or a staggered (also referred to as a top-gate) structure depending on the position of the gate electrode. In the top gate structure, the gate electrode is located above the gate insulating layer, and the active layer is formed below the gate insulating layer. In the bottom gate structure, the gate electrode is located below the gate insulating layer, and the active layer is formed above the gate insulating layer. The invention is not limited thereto.
Referring to step S120 of fig. 1 again, a gate insulating layer is formed on the gate metal layer. Please refer to fig. 2C. The gate metal layer 220 completely covers a gate insulating layer 230. In more detail, the gate insulating layer 230 is coated on the gate metal layer 220 in conformity with the profile of the gate metal layer 220, and covers the exposed upper surface area of the substrate 210. The substrate 210 having the patterned gate metal layer 220 may be planarized by coating the gate insulating layer 230 so that the surface of the substrate 210 does not have a raised portion due to the patterned gate metal layer.
Referring back to step S130 of fig. 1, a silicon-containing layer is formed on the gate insulating layer. Please refer to fig. 2D. The silicon-containing layer 240 comprises an amorphous silicon layer (a-Si), the silicon-containing layer 240 is deposited on top of the gate dielectric layer 230 by, for example, Chemical Vapor Deposition (CVD), and the amorphous silicon layer is n + doped to form a doped layer in the amorphous silicon layer and to serve as source and drain (S/D) contacts.
Referring back to step S140 of fig. 1, the flash lamp anneals the silicon-containing layer. The flash lamp anneal 290 crystallizes before the silicon-containing layer 240 has not been patterned to form shaped regions. The flash laser anneal 290 uses a flash lamp to generate white light over a wide wavelength range, such as 400-800 nm. The flash lamp is a gas-filled discharge lamp, such as xenon, which produces a very short duration and intense non-coherent full spectrum white light. Flash lamp annealing is the process of using white light energy to generate radiation on the target surface and also directing the light through a mirror arrangement to focus the light energy onto the target surface. The flash lamp power is supplied by a series of capacitors and inductors, and the discharge light energy density can be as high as 40 joules per square centimeter (J/cm) of 1-20 milliseconds (ms) discharge2Such as (c). The flash lamp anneal 290 allows a single flash to rapidly heat the solid surface of the silicon-containing layer 240.
The variables of the flash lamp that affect the crystalline quality of the silicon-containing layer 240 may include the energy density and duration of the incident light and the shape of the light. Because the flash lamp radiation is a universal radiation process, the flash lamp can radiate a large-area substrate surface by a single pulse, and can process the amorphous silicon film covered on the substrate at one time. Therefore, multi-pulse operation such as scanning of excimer laser annealing is not required. Flash lamp annealing is also less expensive than laser annealing. According to some embodiments of the present invention, the temperature ramp rate for flash lamp annealing is between 700 and 1300 ℃/sec.
After the flash lamp anneal 290, lateral growth of the crystalline structure of the silicon-containing layer 240 begins at the surface of the silicon-containing layer 240 and expands in a direction perpendicular to the arrows of the flash lamp anneal 290 to produce a crystalline material. Silicon crystal grains tend to grow laterally from perpendicular to the interface between the liquid phase and the solid phase silicon. Thus, as some areas of the silicon-containing layer 240 are irradiated and melted while other areas of the silicon-containing layer 240 remain solid, crystalline growth starts from the solid/liquid interface of the silicon-containing layer 240 and proceeds laterally along the silicon-containing layer 240. This form of crystal growth, known as lateral growth, can produce large silicon crystal grains, which is advantageous for device fabrication. Accordingly, elements may be formed in the laterally grown regions of silicon-containing layer 240.
Please refer to fig. 2F. The silicon-containing layer 240 is patterned, and the patterning process includes forming a photoresist layer on the silicon-containing layer 240, performing photolithography on the amorphous silicon layer and the doped layer of the silicon-containing layer 240 to form a silicon-containing layer 240' with a specific shape, leaving only a region (island) with a predetermined shape on the gate insulating layer 230, and removing the photoresist layer. After the photoresist layer is removed, a flash lamp anneal 290 is performed. According to some embodiments of the invention, the flash lamp anneal 290 may be performed before or after the silicon-containing layer 240 is patterned. In fig. 2E, the flash lamp anneal 290 is performed prior to the patterning of the silicon-containing layer 240, and in fig. 2F, the flash lamp anneal 290 is performed after the patterning of the silicon-containing layer 240'. The flash lamp anneal is performed after the silicon-containing layer 240 ' is patterned, and the pattern (up and down) of the gate insulating layer 230 coated on the gate metal layer 220 has less influence on the crystalline characteristics of the silicon-containing layer 240 ' due to the planarization of the surface of the silicon-containing layer 240 '.
Referring to step S150 of fig. 1 again, a source metal layer and a drain metal layer are formed. Please refer to fig. 2G. After patterning the silicon-containing layer 240 ', a second metal layer, i.e., a source-drain metal layer 250, is formed using the doped layer previously formed in the silicon-containing layer 240' as source and drain (S/D) contacts. The material of the source-drain metal layer 250 may be made of a material selected from the group consisting of copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), an alloy thereof, or a combination thereof. A source-drain insulating layer (not shown) is further coated on the source-drain metal layer 250 to complete the manufacturing process of the transistor thin film device.
Please refer to fig. 3. FIG. 3 is a schematic cross-sectional view of a thin-film element according to some embodiments of the invention. In the back channel etching process, the transistor thin film is fabricated by the above method, first forming the gate metal layer 320 on the substrate 310, and coating the gate insulating layer 330 on the gate metal layer 320, in this embodiment, the gate insulating layer 330 only covers the range of the gate metal layer 320 in a flat manner, and does not form a wavy appearance as shown in fig. 2C due to the type of the gate metal layer 310, and the gate insulating layer 330 is not in contact with the substrate 310. Next, a silicon-containing layer 340 is formed on the gate insulating layer 330, the silicon-containing layer 340 includes an amorphous silicon layer and a doped layer, and the silicon-containing layer 340 may be flash annealed before or after patterning. Thereafter, a source-drain metal layer is formed on the flash lamp annealed crystallized silicon-containing layer 340. In the present embodiment, the silicon-containing layer 340 does not completely cover the underlying gate insulation layer 330 after patterning. That is, the profile of the silicon-containing layer 340 is different from that of the gate insulation layer 330 such that a portion of the gate insulation layer 330 is exposed outside the silicon-containing layer 340. A second metal layer, a source-drain metal layer 350, is formed over the silicon-containing layer 340. In the present embodiment, the silicon-containing layer 340 only partially covers the source-drain metal layer 350. The source-drain metal layer 350 may also be omitted entirely in some embodiments of the invention. That is, the source-drain metal layer 350 is not covered above the silicon-containing layer 340. According to some embodiments of the present invention, the process allows the silicon-containing layer to be topographically inconsistent with the gate metal layer and the source-drain metal layer.
Please refer to fig. 4. FIG. 4 is a schematic cross-sectional view of a thin-film element according to some embodiments of the invention. The method of fabricating the thin film transistor of fig. 4 is similar to the above embodiments. However, the gate metal layer 420 and the gate insulation layer 430 do not completely cover the substrate 410, the silicon-containing layer 440 and the gate insulation layer 430 have different shapes, and a portion of the gate insulation layer 430 is not covered by the silicon-containing layer 440. The source-drain metal layer 450 covers only a portion of the silicon-containing layer 440 and contacts the gate insulating layer 430 not covered by the silicon-containing layer 440. The top of the source-drain metal layer 450 may be planarized or may exhibit a topography that depends on the patterning of the underlying devices, such as the silicon-containing layer 440 and the gate insulation layer 450.
Please refer to fig. 5. FIG. 5 is a schematic cross-sectional view of a thin-film element according to some embodiments of the invention. The method of fabricating the thin film transistor of fig. 5 is similar to the above embodiments. The flash lamp anneal crystallization of the silicon-containing layer 240' may be performed before or after patterning. However, after the patterned silicon-containing layer 240 'is formed, a source-drain insulation layer 260 is coated on the silicon-containing layer 240'. The source-drain insulating layer 260 covers the silicon-containing layer 240 'and then the source-drain metal layer 250 is formed such that the source-drain insulating layer 260 is located between the silicon-containing layer 240' and the source-drain metal layer 250. A contact between the source-drain metal layer 250 and the doped layer of the silicon-containing layer 240' is formed through a back channel etch process.
The invention provides a method for manufacturing a thin film transistor, wherein a silicon-containing layer comprises an amorphous silicon layer and a doping layer, before or after the silicon-containing layer is patterned, a flash lamp is used for annealing to form crystals on the amorphous silicon layer, the flash lamp can emit high-energy flash light to the thin film in a large area at one time, and the amorphous silicon layer can be crystallized after receiving enough light energy. The doped layer of the silicon-containing layer is connected with the source electrode-drain electrode metal layer and has better ohmic contact (ohmic contact) characteristics.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. A method of manufacturing a thin film device, comprising the steps of:
forming a grid metal layer on a substrate;
forming a gate insulating layer on the gate metal layer;
forming a silicon-containing layer on the gate insulation layer;
flash lamp annealing the silicon-containing layer; and
a source-drain metal layer is formed on the silicon-containing layer.
2. The method of claim 1, further comprising, after the step of flash lamp annealing the silicon-containing layer:
a source-drain insulating layer is formed on the silicon-containing layer and between the silicon-containing layer and the source-drain metal layer.
3. The method of claim 1, wherein forming the silicon-containing layer on the gate insulating layer further comprises:
forming at least one doped layer on the silicon-containing layer.
4. The method of claim 1, wherein forming the silicon-containing layer on the gate insulating layer further comprises patterning the silicon-containing layer, wherein patterning the silicon-containing layer comprises:
forming a photoresist layer on the silicon-containing layer;
lithographically etching the silicon-containing layer; and
the photoresist layer is removed.
5. The method of manufacturing a thin-film element according to claim 1, further comprising:
forming a source-drain insulating layer on the source-drain metal layer.
6. The method as claimed in claim 1, wherein the flash lamp annealing temperature-raising speed is between 700 ℃ and 1300 ℃/sec.
7. The method as claimed in claim 1, wherein the flash lamp annealing has a wavelength of 400-800 nm.
8. The method of claim 1, wherein said flash lamp annealing said silicon-containing layer is formed on said gate insulation layer by chemical vapor deposition.
9. The method of claim 1, wherein the gate metal layer is a material selected from the group consisting of InGaZn oxide, InGaZn oxynitride, zinc oxide, zinc oxynitride, Zn-Sn oxide, Cd-Sn oxide, Ga-Sn oxide, Ti-Sn oxide, Cu-Al oxide, Sr-Cu oxide, La-Cu oxysulfide, GaN, InGaN nitride, AlGaN nitride, and InGaAl nitride.
10. The method of claim 1, wherein the source-drain metal layer is made of a material selected from the group consisting of copper, gold, silver, aluminum, tungsten, molybdenum, chromium, tantalum, titanium, and alloys or combinations thereof.
CN201811234230.9A 2018-10-23 2018-10-23 Method for manufacturing thin film element Pending CN111092017A (en)

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CN101620991A (en) * 2008-07-02 2010-01-06 中芯国际集成电路制造(上海)有限公司 Growth of atomic layer deposition epitaxial silicon of TFT flash memory cell
US20100117090A1 (en) * 2008-11-07 2010-05-13 Hyung-Gu Roh Array substrate including thin film transistor and method of fabricating the same
CN102160160A (en) * 2008-09-19 2011-08-17 应用材料股份有限公司 Method and apparatus for metal silicide formation
US20120115286A1 (en) * 2009-07-09 2012-05-10 Sharp Kabushiki Kaisha Thin-film transistor producing method
CN102763213A (en) * 2011-02-23 2012-10-31 松下电器产业株式会社 Thin-film transistor device manufacturing method, thin-film transistor device, and display device
CN105280716A (en) * 2015-07-24 2016-01-27 友达光电股份有限公司 Method for manufacturing thin film transistor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1929099A (en) * 2005-09-08 2007-03-14 中华映管股份有限公司 Thin film transistor and method for manufacturing polycrystalline silicon layer of low-temperature polycrystalline silicon thin film transistor
TW201001556A (en) * 2008-02-29 2010-01-01 Univ Columbia Flash lamp annealing crystallization for large area thin films
CN101620991A (en) * 2008-07-02 2010-01-06 中芯国际集成电路制造(上海)有限公司 Growth of atomic layer deposition epitaxial silicon of TFT flash memory cell
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US20100117090A1 (en) * 2008-11-07 2010-05-13 Hyung-Gu Roh Array substrate including thin film transistor and method of fabricating the same
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CN105280716A (en) * 2015-07-24 2016-01-27 友达光电股份有限公司 Method for manufacturing thin film transistor

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