TWI706466B - Method of manufacturing thin film element - Google Patents

Abstract

A method of manufacturing thin film element includes forming a metal gate active layer on a substrate, and a first gate insulation layer is formed on the metal gate active layer. Next, an etch stop layer is formed on the first gate insulation layer. Then, the metal gate active layer and the etch stop layer is treated by flash lamp annealing. A metal source and drain layer is formed on the etch stop layer.

Description

Method for manufacturing thin film element

The invention relates to a method for manufacturing a thin film element, in particular to a method for manufacturing a back channel etching semiconductor thin film element.

In order to simplify the fabrication of thin film transistors, the structure of back channel etch <back channel etch, BCE> is currently a fairly common process method. In the manufacture of polysilicon transistors, an amorphous silicon (a-Si) film is first formed, and then converted into polycrystalline by laser annealing. The amorphous silicon can be transformed into a crystalline state by laser irradiation. Excimer laser annealing <ecimer laser annealing, ELA> is widely used as the laser for laser annealing. Excimer laser is a pulsed oscillating laser with a wavelength in the ultraviolet wavelength range of 308 nm or less, which produces a small particle size. Granular crystals.

However, the excimer laser annealing crystallization technology is limited by the length of the wire beam. For example, the excimer laser annealing beam cannot provide consistent beam properties over the entire width or length of a large-area film. Therefore, the excimer laser annealing scan can only be performed in a small area of the film, and it must move the substrate in both the x and y directions to successfully process the film. Compared with scanning smaller films, scanning in both the x and y directions not only increases the process time, but also And it also creates inconsistencies between lower quality films with beam edges and multiple crystal scans.

The back-channel etching process is because the gate metal layer is first produced, and the surface of the transistor is undulating. When performing excimer laser annealing, the heating depth is limited and the coating uniformity is poor. Therefore, it is not suitable for excimer laser annealing in amorphous semiconductors. The layer forms crystals. Moreover, the laser source is not only expensive, especially the laser tube needs to be replaced regularly, and the cost of using equipment is not expensive.

In view of the above-mentioned problems, there is an urgent need in the art for a method that can be uniformly annealed and crystallized without the surface fluctuation of the transistor. The present invention provides a method for manufacturing a thin film element including forming a gate metal layer on a substrate, and then forming a gate insulating layer on the gate metal layer. Then, at least one silicon-containing layer is formed on the gate insulating layer, and then the flash lamp anneals the gate metal layer and the silicon-containing layer, and a source metal layer and a drain metal layer are formed on the silicon-containing layer.

According to some embodiments of the present invention, after the step of annealing the silicon-containing layer of the flash lamp, the method further includes: forming a source-drain insulating layer on the silicon-containing layer and located between the silicon-containing layer and the source-drain metal layer .

According to some embodiments of the present invention, the step of forming a silicon-containing layer on the gate insulating layer further includes: forming at least one doped layer on the silicon-containing layer.

According to some embodiments of the present invention, the step of forming a silicon-containing layer on the gate insulating layer further includes patterning the silicon-containing layer, wherein the step of patterning the silicon-containing layer includes: forming a photoresist layer on the silicon-containing layer; Shadow etching silicon-containing layer; And remove the photoresist layer.

According to some embodiments of the present invention, the method of manufacturing the thin film device further includes forming a source-drain insulating layer on the source-drain metal layer.

According to some embodiments of the present invention, the heating rate of the flash lamp annealing is between 700-1300°C/sec.

According to some embodiments of the present invention, a wavelength range of the flash lamp annealing is 400-800 nm.

According to some embodiments of the present invention, the flash lamp annealing silicon-containing layer is formed on the gate insulating layer by chemical vapor deposition.

According to some embodiments of the present invention, the gate metal layer is selected from indium gallium zinc oxide, indium gallium zinc oxynitride, zinc oxide, zinc oxynitride, zinc tin oxide, cadmium tin oxide, gallium tin oxide, titanium Materials of the group consisting of tin oxide, copper aluminum oxide, strontium copper oxide, lanthanum copper oxysulfide, gallium nitride, indium gallium nitride, aluminum gallium nitride, and indium gallium aluminum nitride.

According to some embodiments of the present invention, the material of the source-drain metal layer is selected from the group consisting of copper, gold, silver, aluminum, tungsten, molybdenum, chromium, tantalum, titanium, and alloys or combinations thereof.

Through flash lamp annealing the silicon-containing layer, the silicon-containing layer originally amorphous silicon can be better activated, and the silicon-containing layer can be crystallized, and the flash lamp annealing can complete the crystallization process in a large area at one time, compared with the laser annealing process more efficient.

S110-S150: steps

210, 310, 410: substrate

220, 320, 420: gate metal layer

230, 330, 430: gate insulation layer

240, 240’, 340, 440: Silicon-containing layer

250, 350, 450: source-drain metal layer

260: source-drain insulating layer

290: Flash annealing

The above and other aspects and features of the present invention can be understood more clearly by referring to the contents of the manual and with the additional drawings. Among them: Figure 1 is a flow chart of a thin film element manufacturing method according to some embodiments of the present invention.

Figures 2A-2G are schematic cross-sectional views of a thin film device manufacturing method according to some embodiments of the present invention.

Figure 3 is a schematic cross-sectional view of a thin film element according to some embodiments of the present invention.

Figure 4 is a schematic cross-sectional view of a thin film element according to some embodiments of the present invention.

Figure 5 is a schematic cross-sectional view of a thin film element according to some embodiments of the present invention.

In order to make the description of the present disclosure more detailed and complete, the following provides an illustrative description for the implementation aspects and specific embodiments of the present invention; but this is not the only way to implement or use the specific embodiments of the present invention. The embodiments disclosed below can be combined or substituted with each other under beneficial circumstances, and other embodiments can also be added to an embodiment without further description or description. In the following description, many specific details will be described in detail so that the reader can fully understand the following embodiments. However, the embodiments of the present invention may be practiced without these specific details.

The present invention is a method of crystallizing an amorphous semiconductor layer by flash annealing for a thin film transistor manufactured for back channel etching. Please refer to Figure 1. FIG. 1 is a flowchart of a method for manufacturing a thin film element according to some embodiments of the present invention. Step S110 is to form a gate metal active layer on a substrate. Please also refer to Section 2A Figure. FIG. 2A is a schematic cross-sectional view of a thin film device manufacturing method according to some embodiments of the present invention. First, a substrate 210 is provided. The substrate 210 can be glass, plastic or metal. Please refer to Figure 2B. FIG. 2B is a schematic cross-sectional view of a thin film device manufacturing method according to some embodiments of the present invention. The gate metal layer 220 is formed on the upper surface of the substrate 210. The metal layer is usually formed on the substrate 210 by a physical vapor deposition process such as sputtering, and is patterned to form the gate metal layer 220.

The material of the gate metal layer 220 can be indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium Tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), nitride It is made of gallium (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN).

According to the position of the gate electrode, the element structure of the transistor can be inversely-staggered, also known as bottom-gate, or staggered, also known as top-gate 〉. In the top gate structure, the gate electrode is located above the gate insulating layer, and the active layer is formed below the gate insulating layer. In the bottom gate structure, the gate electrode is located under the gate insulating layer, and the active layer is formed above the gate insulating layer. The present invention is not limited to this.

Please refer to step S120 in FIG. 1 again to form a gate insulating layer on the gate metal layer. Please refer to Figure 2C. A gate insulating layer 230 is completely covered on the gate metal layer 220. In more detail, the gate insulating layer 230 conforms to the gate The metal layer 220 is externally coated on the gate metal layer 220 and covers the exposed upper surface area of the substrate 210. Therefore, the substrate 210 with the patterned gate metal layer 220 can be flattened by coating the gate insulating layer 230, so that the surface of the substrate 210 does not have a bulge due to the patterned gate metal layer.

Please refer to step S130 in FIG. 1 again to form a silicon-containing layer on the gate insulating layer. Please refer to Figure 2D. The silicon-containing layer 240 includes an amorphous silicon layer <a-Si>. The silicon-containing layer 240 is deposited on top of the gate insulating layer 230 by, for example, chemical vapor deposition (CVD). The amorphous silicon layer is n+ doped A doped layer in the amorphous silicon layer is formed and becomes the source and drain <S/D> contact points.

Please refer to step S140 in Figure 1 again, the flash lamp anneals the silicon-containing layer. Before the silicon-containing layer 240 is patterned to form regions of a specific shape, flash lamp annealing 290 is performed for crystallization. Flash laser annealing 290 uses a flash lamp to generate white light in a wide wavelength range (for example, 400-800 nm). The flash lamp is a gas-filled discharge lamp, such as xenon, which can produce very short and intense non-coherent full-spectrum white light. Flashlight annealing is to use white light energy to generate radiation on the surface of the target, and it can also set the light through a reflector to focus and guide the light energy to the surface of the target. The power of the flash lamp is supplied by a series of capacitors and inductors, and the discharge light energy density can be as high as 1-20 milliseconds (ms) and the discharge can be as high as 40 joules/cm²<J/cm ² >. The flash lamp annealing 290 allows a single flash to rapidly heat the solid surface of the silicon-containing layer 240.

The variables that affect the crystalline quality of the silicon-containing layer 240 may include the energy density, duration, and light shape of the incident light. Since the flash lamp radiation is a pan-radiation process, the flash lamp can irradiate a large area of the substrate surface with a single pulse, and the amorphous silicon film covering the substrate can be processed at one time. Therefore, no Use multi-pulse operation like excimer laser annealing scanning method. The cost of flash annealing is also lower than that of laser annealing. According to some embodiments of the present invention, the heating rate of the flash lamp annealing is between 700-1300°C/sec.

After the flash lamp annealing 290, the lateral growth of the crystalline structure of the silicon-containing layer 240 starts on the surface of the silicon-containing layer 240 and is amplified along the direction perpendicular to the arrow of the flash lamp annealing 290 to produce a crystalline material. Silicon crystal grains tend to grow laterally perpendicular to the interface between the liquid phase and the solid phase silicon. Therefore, when certain areas of the silicon-containing layer 240 are irradiated and melted while other areas of the silicon-containing layer 240 remain solid, crystal growth starts from the solid/liquid interface of the silicon-containing layer 240 and runs along the silicon-containing layer 240 Travel horizontally. This form of crystal growth is called lateral growth, which can produce large silicon crystal grains, which is conducive to device manufacturing. Therefore, the element can be formed in the lateral growth region of the silicon-containing layer 240.

Please refer to Figure 2F. The silicon-containing layer 240 is first patterned. The patterning process includes forming a photoresist layer on the silicon-containing layer 240 to perform yellow photolithography etching on the amorphous silicon layer and the doped layer of the silicon-containing layer 240 to form a specific shape of the In the silicon layer 240', only a region of a predetermined shape <island> remains on the gate insulating layer 230, and then the photoresist layer is removed. After the photoresist layer is removed, flash lamp annealing 290 is performed. According to some embodiments of the present invention, the flash lamp annealing 290 may be performed before or after the silicon-containing layer 240 is patterned. In Figure 2E, the flash lamp annealing 290 is performed before the patterning of the silicon-containing layer 240, and in Figure 2F, the flash lamp annealing 290 is performed after the silicon-containing layer 240' is patterned. After the silicon-containing layer 240' is patterned, flash lamp annealing is performed. Because the surface of the silicon-containing layer 240' is flattened, the gate insulating layer 230 is coated on the gate metal layer 220. The shape of the silicon-containing layer 240' is crystallized. The impact of characteristics is even smaller.

Please refer to step S150 in Figure 1 again to form a source metal layer And a drain metal layer. Please refer to Figure 2G. After the silicon-containing layer 240' is patterned, the doped layer previously formed in the silicon-containing layer 240' is used as source and drain <S/D> contacts to form a second metal layer, which is the source-drain极metal layer 250. The material of the source-drain metal layer 250 can be selected from copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum ( It is made of materials of the group consisting of Ta), titanium (Ti), their alloys or combinations. The source-drain metal layer 250 is also coated with a source-drain insulating layer (not shown) to complete the manufacturing process of the transistor thin film device.

Please refer to Figure 3. Figure 3 is a schematic cross-sectional view of a thin film element according to some embodiments of the present invention. In the back channel etching process, the above-mentioned method is used to fabricate a transistor film. First, a gate metal layer 320 is formed on the substrate 310, and a gate insulating layer 330 is coated on the gate metal layer 320. In this embodiment, the gate is insulated The layer 330 only flatly covers the area of the gate metal layer 320, and does not form an undulating appearance as shown in FIG. 2C due to the shape of the gate metal layer 310, and the gate insulating layer 330 does not contact the substrate 310 either. Next, a silicon-containing layer 340 is formed on the gate insulating layer 330. The silicon-containing layer 340 includes an amorphous silicon layer and a doped layer. The silicon-containing layer 340 can be subjected to flash lamp annealing before or after patterning. After that, a source-drain metal layer is formed on the silicon-containing layer 340 crystallized by flash lamp annealing. In this embodiment, after the silicon-containing layer 340 is patterned, it does not completely cover the gate insulating layer 330 thereunder. In other words, the shape of the silicon-containing layer 340 and the gate insulating layer 330 are different, so that a part of the gate insulating layer 330 is exposed outside the silicon-containing layer 340. The second metal layer, that is, the source-drain metal layer 350 is then formed on the silicon-containing layer 340. In this embodiment, the silicon-containing layer 340 only partially covers the source-drain metal layer 350. The source-drain metal layer 350 can also be completely omitted in some embodiments of the present invention. That is, the silicon-containing layer The source-drain metal layer 350 is not covered above 340. According to some embodiments of the present invention, this manufacturing process allows the silicon-containing layer to be inconsistent with the gate metal layer and the source-drain metal layer.

Please refer to Figure 4. Figure 4 is a schematic cross-sectional view of a thin film element according to some embodiments of the present invention. The manufacturing method of the thin film transistor in Fig. 4 is similar to the above-mentioned embodiment. However, the gate metal layer 420 and the gate insulating layer 430 do not completely cover the substrate 410, and the topography of the silicon-containing layer 440 and the gate insulating layer 430 are different, and part of the gate insulating layer 430 is not covered by the silicon-containing layer 440 . In addition, the source-drain metal layer 450 only covers a part of the silicon-containing layer 440 and is in contact with the gate insulating layer 430 that is not covered by the silicon-containing layer 440. The top of the source-drain metal layer 450 can be flattened, or show related fluctuations according to the patterning method of the underlying device, such as the state of the silicon-containing layer 440 and the gate insulating layer 450.

Please refer to Figure 5. Figure 5 is a schematic cross-sectional view of a thin film element according to some embodiments of the present invention. The manufacturing method of the thin film transistor in Fig. 5 is similar to the above-mentioned embodiment. The flash lamp annealing crystallization of the silicon-containing layer 240' can be performed before or after patterning. However, after the patterned silicon-containing layer 240' is formed, a source-drain insulating layer 260 is coated on the silicon-containing layer 240'. The source-drain insulating layer 260 covers the silicon-containing layer 240', and then the source-drain metal layer 250 is formed, so that the source-drain insulating layer 260 is located on the silicon-containing layer 240' and the source-drain metal Between layers 250. After a back channel etching process, the contact between the source-drain metal layer 250 and the doped layer of the silicon-containing layer 240' is formed.

The present invention provides a method for manufacturing a thin film transistor. The silicon-containing layer includes an amorphous silicon layer and a doped layer. Before or after the patterning of the silicon-containing layer, a flash lamp annealing is used to form crystals on the amorphous silicon layer. The flash lamp annealing Crystal can One-time, large area emits high-energy flashes to the thin film, and the amorphous silicon layer undergoes crystallization after receiving sufficient light energy. The doped layer containing the silicon layer is connected to the source-drain metal layer, and has better ohmic contact characteristics.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone familiar with the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be subject to those defined in the attached patent scope.

210: Substrate

220: gate metal layer

230: gate insulation layer

240’: Silicon-containing layer

290: Flash annealing

Claims (9)

A method for manufacturing a thin film element, the steps include: forming a gate metal layer on a substrate; forming a gate insulating layer on the gate metal layer; forming a silicon-containing layer on the gate insulating layer; flash lamp annealing The silicon-containing layer; and forming a source-drain metal layer on the silicon-containing layer; wherein the step of forming the silicon-containing layer on the gate insulating layer further includes forming at least one doped layer on the silicon-containing layer . The method for manufacturing a thin film device according to claim 1, wherein after the step of annealing the silicon-containing layer by the flash lamp, the method further comprises: forming a source-drain insulating layer on the silicon-containing layer and located on the silicon-containing layer And the source-drain metal layer. The method of manufacturing a thin film device according to claim 1, wherein the step of forming the silicon-containing layer on the gate insulating layer further includes patterning the silicon-containing layer, and the step of patterning the silicon-containing layer includes: forming a A photoresist layer is on the silicon-containing layer; the silicon-containing layer is lithographically etched; and the photoresist layer is removed. The method of manufacturing a thin film device according to claim 1 further comprising: forming a source-drain insulating layer on the source-drain gold Belonging to the layer. The method for manufacturing a thin film element according to claim 1, wherein the temperature increase rate of the flash lamp annealing is 700-1300° C./sec. The method for manufacturing a thin film element according to claim 1, wherein a wavelength range of the flash lamp annealing is 400-800 nm. The method for manufacturing a thin film device according to claim 1, wherein the flash lamp annealing the silicon-containing layer is formed on the gate insulating layer by chemical vapor deposition. The method of manufacturing a thin film element according to claim 1, wherein the gate metal layer is selected from indium gallium zinc oxide, indium gallium zinc oxynitride, zinc oxide, zinc oxynitride, zinc tin oxide, cadmium tin oxide Compound, gallium tin oxide, titanium tin oxide, copper aluminum oxide, strontium copper oxide, lanthanum copper oxysulfide, gallium nitride, indium gallium nitride, aluminum gallium nitride, and indium gallium aluminum nitride The material of the group. The method for manufacturing a thin film element according to claim 1, wherein the material of the source-drain metal layer is selected from copper, gold, silver, aluminum, tungsten, molybdenum, chromium, tantalum, titanium, and alloys or combinations thereof The materials of the group that it forms.

Images