CN111052368A - 有源硅上封装半导体封装 - Google Patents
有源硅上封装半导体封装 Download PDFInfo
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- CN111052368A CN111052368A CN201780094473.4A CN201780094473A CN111052368A CN 111052368 A CN111052368 A CN 111052368A CN 201780094473 A CN201780094473 A CN 201780094473A CN 111052368 A CN111052368 A CN 111052368A
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- semiconductor package
- conductive
- silicon substrate
- disposed
- active silicon
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 538
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 285
- 239000010703 silicon Substances 0.000 claims abstract description 285
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 272
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- 239000004593 Epoxy Substances 0.000 description 9
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- 238000000151 deposition Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
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Abstract
用于提供低剖面堆叠管芯半导体封装的系统和方法,其中第一半导体封装与第二半导体封装堆叠,并且两个半导体封装都传导耦合到有源硅衬底,该有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。第一半导体封装可使用采用具有第一互连节距的第一互连模式设置的多个互连而传导耦合到有源硅衬底。第二半导体封装可使用采用具有第二节距的第二互连模式设置的多个互连而传导耦合到有源硅衬底,该第二节距大于第一节距。第二半导体封装可以堆叠在第一半导体封装上,并且使用多个传导构件或多个接合线而传导耦合到有源硅衬底。
Description
技术领域
本公开涉及堆叠封装半导体的制造。
背景技术
封装叠加(PoP)是一种集成电路封装技术,其中垂直布置多个球栅阵列(BGA)。PoP封装有益地使半导体封装各自占据的板区(board area)减少。PoP封装还使经常互操作的组件之间的径迹长度(track length)最小化。使径迹长度最小化提供了更加快速的信号传播、减少的噪声和减少的信道串扰(cross-talk)。在组合件中,PoP封装准许在堆叠之前而不是堆叠之后(例如,芯片堆叠)测试个体组件,从而由于在PoP封装中只使用已知的良好组件而减少再处理。
在典型的PoP集成电路中,存储器封装与诸如片上系统(SoC)之类的逻辑封装堆叠。经常地,堆叠封装堆叠并且然后经由重整而物理且传导耦合。由于大部分半导体封装在操作时引起热,所以堆叠中通过半导体封装产生的热必须通过相对小的区域耗散。PoP封装内的减少的热传递导致在堆叠内形成热点,并且最终导致PoP封装过早失效。
附图说明
所要求保护的主题的各种实施例的特征和优势将随着下列详细描述的进行并且在参考附图时变得明显,其中类似标号表示类似部分,并且在所述附图中:
图1是根据本文描述的至少一个实施例的说明性硅上封装(PoS)半导体封装的横截面正视图,其中第一半导体封装和第二半导体封装传导耦合到有源硅衬底,该有源硅衬底使第一半导体封装通信地耦合到第二半导体封装;
图2是根据本文描述的至少一个实施例的说明性硅上封装(PoS)半导体封装的横截面正视图,该说明性硅上封装(PoS)半导体封装包括使用中介层而堆叠且物理耦合的第一半导体封装和第二半导体封装,该中介层设置在第一半导体封装的上表面与该第二半导体封装的下表面之间;
图3是根据本文描述的至少一个实施例的说明性硅上封装(PoS)半导体封装的横截面正视图,该说明性硅上封装(PoS)半导体封装包括物理耦合到至少一个第二半导体封装的堆叠第一半导体封装,该至少一个第二半导体封装经由多个接合线通信地耦合到有源硅衬底;
图4A描绘根据本文描述的至少一个实施例的说明性过程,以用于使第一半导体封装耦合到有源半导体衬底;
图4B描绘根据本文描述的至少一个实施例的说明性过程,以用于将第一半导体封装包覆在模制(molding)化合物中;
图4C描绘根据本文描述的至少一个实施例的说明性过程,其中有源硅衬底已变薄用来暴露硅穿透通孔(through silicon via);
图4D描绘根据本文描述的至少一个实施例的说明性过程,其中靠近传导构件的模制化合物已被去除,从而暴露传导构件,并且焊球已物理且传导耦合到传导构件中的至少一些;
图4E描绘根据本文描述的至少一个实施例的说明性过程,其中中介层已通过高热导率环氧树脂焊剂而物理耦合到第一半导体封装的上表面;
图4F描绘根据本文描述的至少一个实施例的说明性过程,其中焊球已回流(reflow)到设置在有源硅衬底的下表面上的传导凸块之上;
图4G描绘根据本文描述的至少一个实施例的说明性过程,其中硅上封装(PoS)半导体封装已被切割(singulate);
图4H描绘根据本文描述的至少一个实施例的说明性过程,其中经切割的硅上封装(PoS)半导体封装的有源硅衬底已通过使设置在有源硅衬底的下表面上的焊球回流而传导耦合到衬底;
图5A描绘根据本文描述的至少一个实施例的说明性过程,以用于使第一半导体封装耦合到有源半导体衬底;
图5B描绘根据本文描述的至少一个实施例的说明性过程,以用于经由多个接合线使第二半导体封装传导耦合到有源硅衬底并且将合成的硅上封装(PoS)半导体封装包覆在模制化合物中;
图5C描绘根据本文描述的至少一个实施例的说明性过程,其中有源硅衬底已变薄用来暴露硅穿透通孔(TSV);
图5D描绘根据本文描述的至少一个实施例的说明性过程,其中焊球已回流到设置在有源硅衬底的下表面上的传导凸块之上;
图5E描绘根据本文描述的至少一个实施例的说明性过程,其中硅上封装(PoS)半导体封装已被切割;
图5F描绘根据本文描述的至少一个实施例的说明性过程,其中经切割的硅上封装(PoS)半导体封装的有源硅衬底已通过使设置在有源硅衬底的下表面上的焊球回流而传导耦合到衬底;
图6是根据本文描述的至少一个实施例的另一个说明性硅上封装(PoS)半导体封装的横截面正视图,其中散热器(heat spreader)传导耦合到第一半导体封装,并且在散热器与堆叠第二半导体封装的下表面之间存在间隙;
图7是根据本文描述的至少一个实施例制造有源硅上封装(PoS)半导体封装的说明性方法的高级逻辑流程图;
图8是根据本文描述的至少一个实施例制造有源硅上封装(PoS)半导体封装的说明性方法的高级逻辑流程图;
图9是根据本文描述的至少一个实施例制造有源硅上封装(PoS)半导体封装的说明性方法的高级逻辑流程图;
图10是根据本文描述的至少一个实施例制造有源硅上封装(PoS)半导体封装的说明性方法的高级逻辑流程图。
尽管将参考说明性实施例进行以下具体实施方式,但其许多备选方案、修改和变体对于本领域内技术人员而言将是清楚的。
具体实施方式
本文公开的系统和方法提供了硅上封装(PoS)半导体封装,其中第一半导体封装和第二半导体封装堆叠在有源硅衬底上并且传导耦合到有源硅衬底。有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。典型地,第二半导体封装被安置在第一半导体封装上方,并且第一半导体封装使用采用第一模式布置的多个互连而直接传导耦合到有源硅衬底。
在其中第二半导体封装的占用空间(footprint)延伸超出第一半导体封装的占用空间的实施例中,多个传导构件(例如,包铜柱(copper clad pillar))可在采用第二模式布置在有源硅衬底的上表面上的传导结构与设置在第二半导体封装的下表面上的传导结构之间延伸,并且使采用第二模式布置在有源硅衬底的上表面上的传导结构传导耦合到设置在第二半导体封装的下表面上的传导结构。在这样的实施例中,第一模式的互连节距(即,间距和几何布置)可具有大于第二模式的互连节距的密度。在这样的实施例中,传导构件可在使第二半导体封装传导耦合到传导构件之前在有源硅衬底的表面上形成。
在其他实施例中,多个接合线可使第二半导体封装传导耦合到有源硅衬底。在这样的实施例中,采用第二模式跨有源硅衬底的表面设置的衬垫或着落点(land)接收传导耦合到第二半导体封装的接合线的至少一些中的每个接合线。有源硅衬底包括各种导体、电子组件、逻辑装置和/或半导体装置,用以使第一半导体封装通信地耦合到第二半导体封装。在这样的实施例中,使第一半导体封装耦合到有源硅衬底的互连的第一模式的互连节距可具有比使第二半导体封装耦合到有源硅衬底的衬垫或相似的传导结构的第二模式的互连节距更大的密度。在这样的实施例中,衬垫或其他传导结构可在使第二半导体封装传导耦合到传导构件之前在有源硅衬底的表面上形成。
在其他实施例中,可在第一半导体封装的上表面与第二半导体封装的下表面之间设置中介层。在实施例中,中介层的底表面可以例如使用高导热环氧树脂而物理耦合到第一半导体封装。第二半导体封装传导耦合到中介层的上表面。在一些实现中,跨中介层的下表面的全部或一部分设置的传导着落点、衬垫或相似的结构可传导耦合到从有源硅衬底的表面延伸的传导结构。在一些实现中,接合线可使跨中介层的上表面的全部或一部分设置的传导着落点、衬垫或相似的结构传导耦合到采用第二模式跨有源硅衬底的表面设置的传导结构。
提供硅上封装(PoS)半导体封装。PoS半导体封装可包括:有源硅衬底,所述有源硅衬底具有:上表面;下表面;以及跨上表面设置的多个传导结构;其中多个传导结构包括:采用第一模式跨有源硅衬底的上表面设置的传导结构的第一部分;以及采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分;第一半导体封装,所述第一半导体封装具有上表面、下表面和采用第一模式跨第一半导体封装的下表面设置的多个传导凸块;其中多个传导凸块使第一半导体封装通信地耦合到设置在有源硅衬底上的传导结构的第一部分;以及第二半导体封装,所述第二半导体封装具有上表面和下表面;设置第二半导体封装使得第一半导体封装的至少一部分被设置在第二半导体封装的下表面与有源硅衬底的上表面之间;以及第二半导体封装经由多个传导构件通信地耦合到设置在有源硅衬底上的传导结构的第二部分中的至少一些,其中有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。
提供硅上封装(PoS)半导体封装制造方法。该方法可包括:使设置在第一半导体封装的下表面上的多个传导结构中的每个传导结构,传导耦合到采用第一模式跨有源硅衬底的上表面设置的传导结构的第一部分中的对应部分;使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分中的对应部分;其中第二半导体封装可操作地耦合到有源硅衬底,使得第一半导体封装的至少一部分被设置在第二半导体封装的下表面的至少一部分与有源硅衬底的上表面之间;以及经由有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。
提供合并硅上封装(PoS)半导体封装的电子装置。该电子装置可包括:衬底,所述衬底具有与其传导耦合的硅上封装(PoS)半导体封装,PoS半导体封装包括:有源硅衬底,所述有源硅衬底具有多个传导结构;其中所述多个传导结构可包括:采用第一模式跨有源硅衬底的上表面的至少一部分设置的传导结构的第一部分;以及采用第二模式跨有源硅衬底的上表面的至少一部分设置的传导结构的第二部分;第一半导体封装,所述第一半导体封装具有上表面、下表面和采用第一模式跨第一半导体封装的下表面的至少一部分设置的多个传导凸块;其中多个传导凸块使第一半导体封装通信地耦合到设置在有源硅衬底的上表面上的传导结构的第一部分;以及第二半导体封装,所述第二半导体封装具有上表面和下表面;第二半导体封装设置在第一半导体封装的上表面上方;以及第二半导体封装经由多个传导构件通信地耦合到设置在有源硅衬底的上表面上的传导结构的第二部分中的至少一些;其中有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。
提供硅上封装(PoS)半导体封装制造系统。该系统可包括:用于使设置在第一半导体封装的下表面上的多个传导结构中的每个传导结构,传导耦合到采用第一模式跨有源硅衬底的上表面设置的传导结构的第一部分中的对应部分的部件;用于使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分中的对应部分的部件;其中第二半导体封装可操作地耦合到有源硅衬底,使得第一半导体封装的至少一部分被设置在第二半导体封装的下表面的至少一部分与有源硅衬底的上表面之间;以及经由有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。
如本文使用的,术语“顶部”、“底部”、“上面”、“下面”、“最下面”和“最上面”在关于一个或多个元件使用时意在传达相对而不是绝对物理配置。从而,装置中描述为“最上面元件”或“顶部元件”的元件在该装置倒置时相反可以形成该装置中的“最下面元件”或“底部元件”。相似地,装置中描述为“最下面元件”或“底部元件”的元件在装置倒置时相反可以形成装置中的“最上面元件”或“顶部元件”。
如本文使用的,术语“逻辑关联”在参考多个对象、系统或元件使用时意在传达对象、系统或元件之间的关系的存在,使得对一个对象、系统或元件的访问暴露了与所访问对象、系统或元件具有“逻辑关联”或与之“逻辑关联”的余下的对象、系统或元件。关系数据库之间存在示例“逻辑关联”,其中对第一数据库中的元素的访问可以提供来自多个额外数据库中的一个或多个元素的信息和/或数据,每个额外数据库与所访问的元素具有识别关系。在另一个示例中,如果“A”与“B”逻辑关联,则访问“A”将暴露来自“B”的信息和/或数据或另外以其它方式从“B”提取信息和/或数据,并且反之亦然。
图1是根据本文描述的至少一个实施例的说明性硅上封装(PoS)半导体封装100的横截面正视图,其中第一半导体封装110和第二半导体封装150堆叠并且传导耦合到有源硅衬底130,该有源硅衬底130使第一半导体封装110通信地耦合到第二半导体封装150。第一半导体封装110使用采用第一模式142跨有源硅衬底130的上表面设置的多个互连140而传导耦合到有源硅衬底130。第二半导体封装150使用从有源硅衬底130的上表面延伸并且采用第二模式162跨有源硅衬底130的上表面设置的多个传导结构160(例如,传导柱),还传导耦合到有源硅衬底130。在实施例中,第一互连模式142的密度大于第二互连模式162的密度。在实施例中,第一互连模式142中的互连间距离(即,互连140之间的距离)小于第二互连模式162中的互连间距离(即,传导结构160之间的距离)。
有源硅衬底130使第一半导体封装110通信地耦合到第二半导体封装150。在实施例中,着落点、衬垫或相似的传导元件132可设置在有源硅衬底130的下表面上、跨有源硅衬底130的下表面设置、或设置在有源硅衬底130的下表面的全部或一部分周围。诸如传导膏(conductive paste)或焊球134之类的传导材料可使有源硅衬底130通信地耦合到底层有机衬底180,诸如印刷电路板。有源硅衬底130可包括任意数量的传导耦合、连接和/或可配置电路、电组件、传导结构、逻辑元件和/或半导体装置。有源硅衬底130可包括任意数量和/或组合的传导和/或介电层。有源硅衬底130使第一半导体封装110通信地耦合到第二半导体封装150。有源硅层130可具有小于以下的高度:约50微米(μm);约75μm;约100μm;约125μm;约150μm;约175μm;或约200μm。使有源硅层130传导耦合到底层有机衬底的传导元件132可具有小于以下的高度:约50微米(μm);约75μm;约100μm;约125μm;约150μm;约175μm;或约200μm。
在实施例中,第一半导体封装110使用采用第一互连模式142布置的互连140而传导耦合到有源硅衬底130。在实施例中,采用第一互连模式142布置的着落点、衬垫、凸块或相似的传导元件140可设置在有源硅衬底130的上表面上、设置在有源硅衬底130的上表面周围或跨有源硅衬底130的上表面设置。在实施例中,形成第一互连模式142的着落点、衬垫、凸块或相似的传导元件可以间隔以下距离:小于约100微米(μm);小于约80μm;小于约60μm;小于约50μm;小于约40μm;小于约30μm;小于约20μm;或小于约10μm。
在实施例中,第二半导体封装150使用采用第二互连模式162布置的传导构件160而传导耦合到有源硅衬底。在实施例中,采用第二互连模式162布置的传导元件160可设置在有源硅衬底130的上表面上、设置在有源硅衬底130的上表面周围或跨有源硅衬底130的上表面设置。在实施例中,形成第二互连模式162的传导构件160可以间隔以下距离:大于约100微米(μm);大于约120μm;大于约140μm;大于约150μm;大于约170μm;大于约190μm;大于约200μm;或大于约220μm。在一些实现中,传导构件160可使用任何当前或未来开发出的沉积技术在有源硅衬底130的上表面上、在有源硅衬底130的上表面周围或跨有源硅衬底130的上表面形成。在一些实现中,传导构件160可包括但不限于铜镀构件,其传导耦合到有源硅衬底130的上表面。在实施例中,传导构件160可具有以下高度(即,可从有源硅衬底130的上表面投射某一距离):约50微米(μm);约60μm;约70μm;约80μm;约90μm;约100μm;约110μm;约120μm;约130μm;约140μm;或约150μm。
第一半导体封装110可包括任意数量和/或组合的半导体管芯和/或堆叠半导体管芯,其具有跨第一半导体封装110的底表面的全部或一部分设置的第一高密度互连模式142。在实施例中,多个微凸块140可在第一半导体封装110的底表面上提供第一互连模式142。在实施例中,第一半导体封装110可包括片上系统(SoC)半导体封装,诸如从Intel®,Corp.(加利福尼亚州圣克拉拉市)获得的Atom® SoC。第一半导体封装110可包括在机架安装式、台式或便携式基于处理器的装置中使用的一个或多个半导体封装。在至少一些实现中,一个或多个材料在第一半导体封装110的底表面与有源硅衬底130的上表面之间的空间中可以底流(underflow)190。在实施例中,第一半导体封装110可具有小于以下的高度:约50微米(μm);约75μm;约100μm;约125μm;约150μm;或约200μm。
第二半导体封装150可包括任意数量和/或组合的半导体管芯和/或堆叠半导体管芯,其具有第二互连模式162,所述第二互连模式162跨第二半导体封装150的底表面的伸出和/或延伸超出第一半导体封装110的外围的外围部分的全部或一部分设置。在实施例中,第二半导体封装150可包括但不限于:一个或多个存储器和/或存储半导体封装;一个或多个图形/图像处理器半导体封装;和/或一个或多个有线或无线通信接口半导体封装。
如在图1中描绘的,第二半导体封装150的下表面可使用一个或多个化学活性或热固性粘合剂(诸如高热导率粘合剂170,其促使热流向上通过PoS封装)物理附连、耦合和/或接合到第一半导体封装的上表面。在实施例中,高热导率粘合剂170可具有小于以下的高度(即,从第二半导体封装150的下表面到第一半导体封装110的上表面测得的深度):约5微米(μm);约10μm;约15μm;约20μm;约25μm;或约30μm。
在实施例中,第二半导体封装150可包括多个传导特征,诸如多个焊球152,其在回流时使第二半导体封装150传导耦合到从有源硅衬底的上表面延伸的传导构件160。在实施例中,模制化合物112可以插入、沉积、流动或以其它方式设置在第二半导体封装150的下表面与有源硅衬底130的上表面之间。
图2是根据本文描述的至少一个实施例的说明性硅上封装(PoS)半导体封装200的横截面正视图,其包括使用设置在第一半导体封装110的上表面与第二半导体封装150的下表面之间的中介层210而堆叠且物理耦合的第一半导体封装110和第二半导体封装150。第一半导体封装110使用采用第一模式142跨有源硅衬底130的上表面设置的多个互连140而传导耦合到有源硅衬底130。第二半导体封装150包括球栅阵列封装,其传导耦合到设置在中介层210的上表面上、设置在中介层210的上表面周围、或跨中介层210的上表面设置的多个着落点、衬垫或相似的传导特征232。中介层210包括多个传导特征,诸如多个焊球222,其在回流时使中介层210(并且因此,使第二半导体封装150)传导耦合到从有源硅衬底130的上表面延伸的传导构件160。
中介层210将第二半导体封装150的下表面上的接触模式或节距转化(translate)为第二互连模式162,由此有益地使在PoS半导体封装200中能够使用BGA和相似的第二半导体封装150。在一些实现中,中介层210包括夹在上传导层230与下传导层240之间的有机节距再分布层220,所述上传导层230包括和/或合并传导特征232,所述下传导层240包括和/或合并用于使中介层210传导耦合到传导构件160的多个焊球222。如在图2中描绘的,中介层210的下表面可使用一个或多个化学活性或热固性粘合剂(诸如高热导率粘合剂170,其促使热流横向和向上通过PoS封装200)物理附连、耦合和/或接合到第一半导体封装的上表面。在实施例中,中介层210可具有小于以下的高度:约20微米(μm);约30μm;约40μm;约50μm;约60μm;约70μm;或约80μm。
图3是根据本文描述的至少一个实施例的说明性硅上封装(PoS)半导体封装300的横截面正视图,其包括物理耦合到至少一个第二半导体封装150的堆叠第一半导体封装110,该至少一个第二半导体封装150经由多个接合线310A-310n(统称为“接合线310”)通信地耦合到有源硅衬底130。如在图3中描绘的,第一半导体封装110使用采用第一模式142跨有源硅衬底130的上表面设置的多个互连140而传导耦合到有源硅衬底130。如在图3中描绘的,至少一个第二半导体封装150可包括多个第二半导体装置150A-150n(统称为“第二半导体封装或装置150”),所述多个第二半导体装置150A-150n的每个使用一个或多个化学活化或热固性粘合剂170物理附连或耦合到第一半导体封装110的上表面。
如在图3中描绘的,第二半导体装置150A和150B中的每个经由多个接合线310A-310n而传导耦合到有源硅衬底130,所述多个接合线310A-310n中的每个从设置在第二半导体封装或装置150的上表面上的传导特征延伸到采用第二互连模式设置在有源硅衬底130的上表面上、跨有源硅衬底130的上表面设置或设置在有源硅衬底130的上表面周围的相应的传导衬垫320A-320n。在实施例中,诸如在图3中描绘的,底流材料340可设置在有源硅衬底130的下表面与PoS半导体封装300A所耦合到的有机衬底180的上表面之间。在实施例中,诸如在图3中描绘的,模制化合物330可以至少部分设置在第一半导体封装110和第二半导体封装150周围。
图4A-4H描绘根据本文描述的至少一个实施例的说明性过程,以用于制造硅上封装(PoS)半导体封装。图4A描绘根据本文描述的至少一个实施例的说明性过程400A,以用于使第一半导体封装110耦合到有源硅衬底130。如在图4A中描绘的,有源半导体衬底130可包括多个装置,诸如电组件、导体、逻辑元件和半导体装置410,诸如半导体晶体管。多个硅穿透通孔(TSV)414A-414n可延伸到有源硅衬底130内。多个传导元件412可从有源硅衬底130的上表面向上延伸。在实施例中,传导元件412中的一些或全部中的每个传导元件可包括顶端装有薄焊料凸块418的镍柱416。在实施例中,传导元件412可采用第一互连模式142设置。
多个传导结构160A-160n(统称为“传导结构160”)采用第二互连模式162在有源硅衬底130的上表面上形成、沉积或以其它方式设置。在实施例中,传导结构160可使用任何当前可用或未来开发出的材料沉积工艺而形成,所述材料沉积工艺诸如电镀或光刻沉积。在实施例中,传导结构160例如经由焊料或经由导电粘合剂,可预先形成或附连到有源硅衬底130的上表面。传导结构160可使用任何导电材料形成,诸如:铜或含铜合金;铝或含铝合金;传导聚合物;或其组合。在实施例中,传导结构160可具有相同或不同高度。传导结构160可具有大于以下的高度:约50微米(μm);约75μm;约100μm;约125μm;约150μm;约175μm;或约200μm。
第一半导体封装110包括电子组件、电路、导体、逻辑元件和半导体装置430,诸如半导体晶体管。第一半导体封装110还包括采用第一互连模式142布置或设置在第一半导体封装110的下表面上的多个传导元件432。在实施例中,传导元件432中的一些或全部中的每个传导元件可包括顶部装有薄焊料凸块438的镍柱436。环氧树脂焊剂420可用于促进第一半导体封装110传导耦合到有源硅衬底130。
在实施例中,附连到第一半导体封装110的传导元件432上的焊料438熔融并且与附连到有源硅衬底130的传导元件412上的焊料418组合来形成互连140,该互连140使第一半导体封装110传导耦合到有源硅衬底130。在一些实现中,固化的环氧树脂焊剂420仍然在第一半导体封装110的下表面与有源硅衬底130的上表面之间来为第一半导体封装110提供底部填充。
图4B描绘根据本文描述的至少一个实施例的说明性过程400B,以用于将第一半导体封装110包覆在模制化合物112中。如在图4B中描绘的,模制化合物112可部分或完全设置在第一半导体封装110周围。在实施例中,模制化合物的顶表面可以近似地与第一半导体封装110的上表面齐平。在实施例中,传导结构160可被模制化合物112覆盖和/或被包覆在模制化合物112中。
图4C描绘根据本文描述的至少一个实施例的说明性过程400C,其中有源硅衬底130已变薄用来暴露硅穿透通孔(TSV)412A-412n(统称为“TSV 412”)。TSV 412中的至少一些中的每个TSV在设置在有源硅衬底130的下表面上的相应的传导凸块415A-415n(统称为“传导凸块415”)中终止。有源硅衬底130可使用任何当前可用或未来开发出的变薄方法或工艺而变薄,所述变薄方法或工艺诸如化学/机械平坦化(CMP)。在实施例中,传导凸块415可使用任何当前可用或未来开发出的沉积技术、工艺或方法而靠近TSV 412中的每个TSV设置、沉积或以其它方式形成。例如,传导元件415可在有源硅衬底130的下表面上光刻沉积或电镀。
图4D描绘根据本文描述的至少一个实施例的说明性过程400D,其中靠近传导构件160的模制化合物112已被去除,从而暴露传导构件160,并且焊球450已物理且传导耦合到传导构件160中的至少一些。在实施例中,靠近传导构件160中的至少一些的模制化合物112可使用任何当前可用或未来开发出的材料去除技术、工艺或方法而被去除。例如,靠近传导构件160中的一些或全部的末端的模制化合物112可经由激光消融(laser ablation)而去除。
在实施例中,在传导构件160中的每个传导构件上方形成浅通模制互连(shallowthrough mold interconnect)(TMI),从而暴露相应的传导构件的远(参考有源硅衬底130)端。TMI和传导构件160被清洗,将焊膏施加或印刷到模制化合物112的上表面之上并且回流到TMI内,从而形成焊球450,其物理且传导耦合到相应的传导构件160。
图4E描绘根据本文描述的至少一个实施例的说明性过程400E,其中中介层210已通过高热导率环氧树脂焊剂170物理耦合到第一半导体封装110的上表面。中介层210包括夹在上传导层230与下传导层240之间的有机节距再分布层220,该下传导层240传导耦合到在传导构件160的末端上形成的焊球250。
图4F描绘根据本文描述的至少一个实施例的说明性过程400F,其中焊球460已回流到设置在有源硅衬底130的下表面上的传导凸块415之上。尽管在图4F中描绘了回流的焊球460,但靠近设置在有源硅衬底130的下表面上的传导凸块415中的至少一些中的每个传导凸块可设置任何相似的传导元件。
图4G描绘根据本文描述的至少一个实施例的说明性过程400G,其中硅上封装(PoS)半导体封装已被切割。PoS半导体封装400G可使用任何当前可用或未来开发出的切割技术、方法或工艺来切割。例如,在一些实现中,PoS半导体封装400G可使用机械或磨切锯(abrasive saw)来切割。
图4H描绘根据本文描述的至少一个实施例的说明性过程400H,其中经切割的硅上封装(PoS)半导体封装已通过使设置在有源硅衬底130的下表面上的焊球460回流而传导耦合到衬底480。在实施例中,底部填充材料470可在有源硅衬底130的下表面与衬底480的上表面之间流动。在实施例中,衬底480可包括印刷电路板,其具有多个高密度衬底的层。
图5A-5F描绘根据本文描述的至少一个实施例的说明性过程,以用于制造硅上封装(PoS)半导体封装,其中多个接合线310使第二半导体封装150通信地耦合到有源硅衬底130。图5A描绘根据本文描述的至少一个实施例的说明性过程500A,以用于使第一半导体封装110耦合到有源半导体衬底130。如在图5A中描绘的,有源半导体衬底130可包括多个装置,诸如电组件、导体、逻辑元件和半导体装置410,诸如半导体晶体管。多个硅穿透通孔(TSV)414A-414n可延伸到有源硅衬底130内。多个传导元件412可从有源硅衬底130的上表面向上延伸。在实施例中,传导元件412中的一些或全部中的每个传导元件可包括顶部装有薄焊料凸块418的镍柱416。在实施例中,传导元件412可采用第一互连模式142设置。
多个传导衬垫320A-320n(统称为“传导衬垫320”)采用第二互连模式162在有源硅衬底130的上表面上形成、沉积或以其它方式设置。在实施例中,传导衬垫320可使用任何当前可用或未来开发出的材料沉积工艺而形成,诸如电镀或光刻沉积。传导衬垫320可使用任何传导材料形成,诸如:铜或含铜合金;铝或含铝合金;传导聚合物;或其组合。
第一半导体封装110包括电子组件、电路、导体、逻辑元件和半导体装置430,诸如半导体晶体管。第一半导体封装110还包括采用第一互连模式142布置或设置在第一半导体封装110的下表面上的多个传导元件432。在实施例中,传导元件432中的一些或全部中的每个传导元件可包括顶部装有薄焊料凸块438的镍柱436。环氧树脂焊剂420可用于促进第一半导体封装110传导耦合到有源硅衬底130。
在实施例中,附连到第一半导体封装110的传导元件432上的焊料438熔融并且与附连到有源硅衬底130的传导元件412上的焊料418组合来形成互连140,该互连140使第一半导体封装110传导耦合到有源硅衬底130。在一些实现中,固化的环氧树脂焊剂420仍然在第一半导体封装110的下表面与有源硅衬底130的上表面之间来为第一半导体封装110提供底部填充。
图5B描绘根据本文描述的至少一个实施例的说明性过程500B,以用于经由多个接合线310A-310n(统称为“接合线310”)使第二半导体封装150传导耦合到有源硅衬底130,并且将合成的硅上封装(PoS)半导体封装包覆在模制化合物330中。第二半导体封装150可包括使用接合剂(诸如高热导率(Hi-K)环氧树脂170)物理耦合到第一半导体封装110的上表面的一个或多个半导体封装。多个接合线310中的每个接合线的第一端传导耦合到设置在第二半导体封装150的上表面的至少一部分上、跨第二半导体封装150的上表面的至少一部分设置、或设置在第二半导体封装150的上表面的至少一部分周围的相应的传导衬垫510A-510n(统称为“传导衬垫510”)。多个接合线310中的每个接合线的第二端传导耦合到采用第二互连模式设置在有源硅衬底130的上表面上的相应的传导衬垫320A-320n。
同样如图5B中描绘的,模制化合物330可设置在有源硅衬底130的上表面的至少一部分上、设置在有源硅衬底130的上表面的至少一部分周围、或跨有源硅衬底130的上表面的至少一部分设置,使得模制化合物330至少部分环绕和/或覆盖堆叠第一半导体封装110、第二半导体封装150和接合线310。在实施例中,模制化合物可包括高热导率模制化合物330。在这样的实施例中,高热导率模制化合物330可具有大于以下的热导率:约2瓦/米-开尔文(W/m-K);约3W/m-K;约4W/m-K;约5W/m-K;约7W/m-K;约10W/m-K;或约15W/m-K。
图5C描绘根据本文描述的至少一个实施例的说明性过程500C,其中有源硅衬底130已变薄用来暴露硅穿透通孔(TSV)412A-412n(统称为“TSV 412”)。TSV 412中的至少一些中的每个TSV在设置在有源硅衬底130的下表面上的相应的传导凸块415A-415n(统称为“传导凸块415”)中终止。有源硅衬底130可使用任何当前可用或未来开发出的变薄方法或工艺而变薄,所述变薄方法或工艺诸如化学/机械平坦化(CMP)。在实施例中,传导凸块415可使用任何当前可用或未来开发出的沉积技术、工艺或方法而靠近TSV 412中的每个TSV设置、沉积或以其它方式形成。例如,传导元件415可在有源硅衬底130的下表面上光刻沉积或电镀。
图5D描绘根据本文描述的至少一个实施例的说明性过程500D,其中焊球460已回流到设置在有源硅衬底130的下表面上的传导凸块415之上。尽管在图5D中描绘了回流的焊球460,但靠近设置在有源硅衬底130的下表面上的传导凸块415中的至少一些中的每个传导凸块可设置任何相似的传导元件。
图5E描绘根据本文描述的至少一个实施例的说明性过程500E,其中硅上封装(PoS)半导体封装已被切割。PoS半导体封装可使用任何当前可用或未来开发出的切割技术、方法或工艺来切割。例如,在一些实现中,PoS半导体封装可使用机械或磨切锯来切割。
图5F描绘的说明性过程500F,其中经切割的硅上封装(PoS)半导体封装的有源硅衬底已通过使设置在有源硅衬底130的下表面上的焊球460回流而传导耦合到衬底480。在实施例中,根据本文描述的至少一个实施例,底部填充材料470可在有源硅衬底130的下表面与衬底480的上表面之间流动。在实施例中,衬底480可包括印刷电路板,其具有多个高密度衬底的层。
图6是根据本文描述的至少一个实施例的另一个说明性硅上封装(PoS)半导体封装600的横截面正视图,其中散热器610传导耦合到第一半导体封装110,并且在散热器610与堆叠第二半导体封装150的下表面之间存在间隙。如在图6中描绘的,在实施例中,第二半导体封装150可以未直接物理或热耦合到第一半导体封装110。在实例中,有源硅衬底130使第一半导体封装110通信地耦合且物理连接到第一半导体封装110上方安置的第二半导体封装150。在这样的实现中,第一半导体封装110包括采用第一互连模式142布置的多个互连140,其耦合到有源半导体衬底130。在这样的实现中,采用第二互连模式162布置的多个传导结构160使第二半导体封装150通信地耦合到有源硅衬底130。第一互连模式142可具有比第二互连模式162更大的互连密度。
散热器610可以热传导耦合到第一半导体封装110的上表面的至少一部分。在实施例中,散热器610可使热能(即,热)跨第一半导体封装110的上表面更加均匀地分布。在实施例中,散热器610可以帮助将通过第一半导体封装110生成的热耗散到PoS半导体封装100周围的周边环境。在实施例中,在散热器610与第二半导体封装150的下表面之间可以存在气隙620,用以促进空气跨散热器610流动,并且用以促进散热器610与PoS半导体封装100周围的周边环境之间的对流热传递。在实施例中,散热器610可包括或合并任意数量的表面特征(例如,点、凹陷、翼片、叶片等),用以延伸表面面积和/或增强散热器610的表面之上的对流。
图7是根据本文描述的至少一个实施例制造有源硅上封装(PoS)半导体封装的说明性方法700的高级逻辑流程图。PoS半导体封装包括第一半导体封装110,所述第一半导体封装110通过采用第一互连模式142布置的多个互连140而传导耦合到有源硅衬底130。PoS半导体封装还包括第二半导体封装150,所述第二半导体封装150通过采用第二互连模式162布置的多个传导构件160或接合线310而传导耦合到有源硅衬底130。有源硅衬底130使第一半导体封装110通信地耦合到第二半导体封装150。方法700在702处开始。
在704处,第一半导体封装110使用采用第一互连模式142布置的多个互连140而传导耦合到有源硅衬底130。第一互连模式142包括布置在第一节距(例如,互连间距)上的多个互连140。在实施例中,第一节距可以小于50微米(μm)。
在706处,第二半导体封装150传导耦合到有源硅衬底130。在实施例中,第二半导体封装150可使用从有源硅衬底130的表面延伸并且采用第二互连模式162布置的多个传导构件160而传导耦合到有源硅衬底130。在实施例中,第二半导体封装或装置150可使用传导耦合到采用第二互连模式162跨有源硅衬底130的上表面设置的多个传导衬垫320的多个接合线310而传导耦合到有源硅衬底130。第二互连模式162包括布置在第二节距(例如,互连/传导衬垫间距)上的多个互连160或多个传导衬垫320。在实施例中,第二节距可以大于150微米(μm)。
在708处,有源硅衬底130使第一半导体封装110和第二半导体封装150通信地耦合以促进第一半导体封装110与第二半导体封装150之间数据和/或信息的双向交换。方法700在710结束。
图8是根据本文描述的至少一个实施例制造有源硅上封装(PoS)半导体封装的说明性方法800的高级逻辑流程图。方法800可以连同图7中详细描述的方法700一起使用。PoS半导体封装包括第一半导体封装110,所述第一半导体封装110通过多个互连140而传导耦合到有源硅衬底130。方法800在802处开始。
在804处,底部填充材料190可在第一半导体封装110的下表面与有源硅衬底130的上表面之间形成的空间中流动。在实施例中,底部填充材料190可包括任意数量和/或组合的材料,其可流动且可固化为半刚性或刚性终态。在实施例中,底部填充材料190可包括具有高热导率的非导电材料。例如,底部填充材料190可具有大于以下的热导率:约1瓦/米-开尔文(W/m-K);约2W/m-K;约3W/m-K;约5 W/m-K;约10 W/m-K;约12 W/m-K;约15 W/m-K;或约20 W/m-K。方法800在806处结束。
图9是根据本文描述的至少一个实施例制造有源硅上封装(PoS)半导体封装的说明性方法900的高级逻辑流程图。方法900可以连同图7中详细描述的方法700和/或图8中详细描述的方法800一起使用。PoS半导体封装包括第二半导体封装150,所述第二半导体封装150设置在第一半导体封装110上方,使得该第二半导体封装150的下表面的至少一部分与第一半导体封装110的上表面的至少一部分重叠。方法900在902处开始。
在904处,第二半导体封装150物理耦合到第一半导体封装110。在实施例中,第二半导体封装150的下表面可使用粘合材料170接合到第一半导体封装110的上表面。在一些实现中,粘合材料可包括具有高热导率的基于环氧树脂的粘合材料。例如,粘合材料170可具有大于以下的热导率:约1瓦/米-开尔文(W/m-K);约2W/m-K;约3W/m-K;约5 W/m-K;约10W/m-K;约12 W/m-K;约15 W/m-K;或约20 W/m-K。方法900在906处结束。
图10是根据本文描述的至少一个实施例制造有源硅上封装(PoS)半导体封装的说明性方法1000的高级逻辑流程图。方法1000可以连同图7中详细描述的方法700、图8中详细描述的方法800和/或图9中详细描述的方法900一起使用。在实施例中,PoS半导体封装可包括设置在第二半导体封装150的下表面与第一半导体封装110的上表面之间的中介层210。方法1000在1002处开始。
在1004处,中介层210设置在第二半导体封装150的下表面与第一半导体封装110的上表面之间。在实施例中,中介层210包括多个传导特征,诸如多个焊球222,其在回流时使中介层210(并且因此,使第二半导体封装150)传导耦合到从有源硅衬底130的上表面延伸的传导构件160。
中介层210将第二半导体封装150的下表面上的接触模式或节距转化为第二互连模式162。在一些实现中,中介层210包括夹在上传导层230与下传导层240之间的有机节距再分布层220,该上传导层230包括和/或合并传导特征232,该下传导层240包括和/或合并用于使中介层210传导耦合到传导构件160的多个焊球222。
在1006处,第二半导体封装150传导耦合到中介层210。
在1008处,中介层210传导耦合到有源硅衬底130。在实施例中,中介层210的下表面可使用一个或多个化学活性或热固性粘合剂(诸如高热导率粘合剂170,其促使热流横向和向上通过PoS半导体封装)而物理附连、耦合和/或接合到第一半导体封装110的上表面。方法1000在1010处结束。
尽管图7至图10图示根据一个或多个实施例的各种操作,但要理解不是图7至图10中描绘的所有操作对于其他实施例而言都是必要的。实际上,本文充分考虑到在本公开的其他实施例中,图7至图10中所描绘的操作和/或本文描述的其他操作可采用未特别在任一图中示出的方式组合,但仍然完全符合本公开。从而,针对一个图中未确切示出的特征和/或操作的权利要求被视作在本公开的范围和内容内。
如在本申请和权利要求书中使用的,加上术语“和/或”的条目的列表可以表示所列条目的任何组合。例如,短语“A、B和/或C”可以表示A;B;C;A和B;A和C;B和C;或A、B和C。如在本申请和权利要求书中使用的,加上术语“…中的至少一个”的条目的列表可以表示所列条目的任何组合。例如,短语“A、B或C中的至少一个”可以表示A;B;C;A和B;A和C;B和C;或A、B和C。
从而,本公开针对用于提供低剖面堆叠管芯半导体封装的系统和方法,其中第一半导体封装与第二半导体封装堆叠,并且两个半导体封装都传导耦合到有源硅衬底,该有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。第一半导体封装可使用采用具有第一互连节距的第一互连模式设置的多个互连而传导耦合到有源硅衬底。第二半导体封装可使用采用具有第二节距的第二互连模式设置的多个互连而传导耦合到有源硅衬底,该第二节距大于第一节距。第二半导体封装可以堆叠在第一半导体封装上,并且使用多个传导构件或多个接合线而传导耦合到有源硅衬底。
下列示例关于另外的实施例。本公开的下列示例可包括主题材料,诸如至少一个装置、方法、用于存储指令的至少一个机器可读介质,所述指令在被执行时促使机器执行基于方法的动作、用于执行基于方法的动作的部件和/或用于改进和增强跨PoP半导体封装中的第一半导体封装的上表面的横向热分布并且改进和增强在PoP半导体封装内从第一半导体封装到第二半导体封装的热流的系统。
根据示例1,提供有硅上封装(PoS)半导体封装。PoS半导体封装可包括:有源硅衬底,所述有源硅衬底具有:上表面;下表面;以及跨上表面设置的多个传导结构;其中多个传导结构包括:采用第一模式跨有源硅衬底的上表面设置的传导结构的第一部分;以及采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分;第一半导体封装,所述第一半导体封装具有上表面、下表面和采用第一模式跨第一半导体封装的下表面设置的多个传导凸块;其中多个传导凸块使第一半导体封装通信地耦合到设置在有源硅衬底上的传导结构的第一部分;以及第二半导体封装,所述第二半导体封装具有上表面和下表面;设置第二半导体封装使得第一半导体封装的至少一部分被设置在第二半导体封装的下表面与有源硅衬底的上表面之间;以及第二半导体封装经由多个传导构件通信地耦合到设置在有源硅衬底上的传导结构的第二部分中的至少一些,其中有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。
示例2可包括示例1的元素,其中第一模式包括设置在50微米(μm)或更少的第一节距上的传导结构;以及其中第二模式包括设置在150μm或更多的第二节距上的传导结构。
示例3可包括示例1或2中的任一个的元素,其中一个或多个粘合剂使第二半导体封装的下表面物理耦合到第一半导体封装的上表面的至少一部分。
示例4可包括示例1至3中的任一个的元素,其中第二半导体封装的下表面伸出第一半导体封装的上表面的边缘的至少一部分。
示例5可包括示例1至4中的任一个的元素,其中第二半导体封装的下表面上的多个传导凸块包括多个传导凸块,所述多个传导凸块设置在第二半导体封装的伸出第一半导体封装的上表面的那部分周围;以及其中多个传导构件包括多个传导柱,所述多个传导柱使多个传导凸块中的至少一些通信地耦合到设置在有源硅衬底的上表面上的传导结构的第二部分中的至少一些,所述多个传导凸块设置在第二半导体封装的伸出第一半导体封装的上表面的那部分周围。
示例6可包括示例1至5中的任一个的元素,并且PoS半导体封装可另外包括设置在第一半导体封装的上表面与第二半导体封装的下表面之间的中介层,中介层包括:跨中介层的上表面设置的多个传导衬垫;跨中介层的下表面的至少一部分设置的多个传导结构;以及多个导体,所述多个导体使设置在中介层的上表面上的多个传导衬垫中的至少一些通信地耦合到设置在中介层的下表面上的多个传导结构中的至少一些。
示例7可包括示例1至6中的任一个的元素,其中设置在第二半导体封装的下表面上的多个传导凸块中的至少一些中的每个传导凸块,物理且通信地耦合到跨中介层的上表面设置的多个传导衬垫中的对应传导衬垫;以及其中中介层包括跨中介层的下表面的至少一部分设置的粘合剂,用于使第二半导体封装和中介层物理耦合到第一半导体封装。
示例8可包括示例1至7中的任一个的元素,其中中介层的下表面伸出第一半导体封装的上表面的边缘的至少一部分。
示例9可包括示例1至8中的任一个的元素,其中中介层的下表面上的多个传导结构包括多个传导凸块,所述多个传导凸块设置在有机中介层的伸出第一半导体封装的上表面的那部分周围;以及其中多个传导构件包括多个传导柱,所述多个传导柱使传导凸块中的至少一些中的每个传导凸块,通信地耦合到设置在有源硅衬底的上表面上的传导结构的第二部分中的对应部分,所述传导凸块设置在中介层的伸出第一半导体封装的上表面的那部分周围。
示例10可包括示例1至9中的任一个的元素,其中通信地耦合到第二半导体封装的多个传导构件包括多个接合线,所述多个接合线通信地耦合到第二半导体封装;以及其中多个接合线中的至少一些中的每个接合线,通信地耦合到设置在有源硅衬底的表面上的传导结构的第二部分中的对应部分。
根据示例11,提供有硅上封装(PoS)半导体封装制造方法。该方法可包括:使设置在第一半导体封装的下表面上的多个传导结构中的每个传导结构,传导耦合到采用第一模式跨有源硅衬底的上表面设置的传导结构的第一部分的对应部分;使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分的对应部分;其中第二半导体封装可操作地耦合到有源硅衬底,使得第一半导体封装的至少一部分被设置在第二半导体封装的下表面的至少一部分与有源硅衬底的上表面之间;以及经由有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。
示例12可包括示例11的元素,并且该方法可另外包括在第一半导体封装的下表面与有源硅衬底的上表面之间设置底部填充材料。
示例13可包括示例11或12中的任一个的元素,其中使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分的对应部分,可包括:使具有采用第二模式设置在第二半导体封装的下表面上的多个传导结构的第二半导体封装传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分。
示例14可包括示例11至13中的任一个的元素,并且该方法可另外包括:使第二半导体封装的下表面的至少一部分粘合地耦合到第一半导体封装的上表面的至少一部分。
示例15可包括示例11至14中的任一个的元素,其中使第二半导体封装的下表面的至少一部分粘合地耦合到第一半导体封装的上表面的至少一部分,可包括:使第二半导体封装的下表面的至少一部分粘合地耦合到第一半导体封装的上表面的至少一部分,使得第二半导体封装的下表面的至少一部分伸出第一半导体封装的上表面的边缘的至少一部分。
示例16可包括示例11至15中的任一个的元素,其中使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分的对应部分,可包括:使多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分,所述多个传导结构设置在第二半导体封装的下表面的伸出第一半导体封装的上表面的那部分周围。
示例17可包括示例11至16中的任一个的元素,其中使多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分,所述多个传导结构设置在第二半导体封装的下表面的伸出第一半导体封装的上表面的那部分周围,可包括:经由传导柱,使多个传导结构中的至少一些中的每个传导结构,传导耦合到采用第二模式设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分,所述多个传导结构设置在第二半导体封装的下表面的伸出第一半导体封装的上表面的那部分周围。
示例18可包括示例11至17中的任一个的元素,并且该方法可另外包括:在第一半导体封装的上表面与第二半导体封装的下表面之间设置中介层,中介层包括:跨中介层的上表面设置的多个传导衬垫;跨中介层的下表面的至少一部分设置的多个传导结构;以及多个导体,所述多个导体使设置在中介层的上表面上的多个传导衬垫中的至少一些通信地耦合到中介层的下表面上的多个传导结构中的至少一些。
示例19可包括示例11至18中的任一个的元素,其中使第二半导体封装传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分,还可包括:使采用第二模式设置在第二半导体封装的下表面上的多个传导结构中的至少一些中的每个传导结构,传导耦合到跨中介层的上表面设置的多个传导衬垫中的对应传导衬垫;以及使跨中介层的下表面的至少一部分设置的多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分。
示例20可包括示例11至19中的任一个的元素,并且该方法可另外包括:使中介层的下表面粘合地耦合到第一半导体封装的上表面的至少一部分,以使中介层和第二半导体封装物理耦合到第一半导体封装。
示例21可包括示例11至20中的任一个的元素,其中使中介层的下表面粘合地耦合到第一半导体封装的上表面的至少一部分,还可包括:使中介层的下表面粘合地耦合到第一半导体封装的上表面的至少一部分,使得中介层的下表面的至少一部分伸出第一半导体封装的上表面的边缘的至少一部分。
示例22可包括示例11至21中的任一个的元素,其中使跨中介层的下表面的至少一部分设置的多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分,可包括:经由传导柱,使多个传导结构中的至少一些中的每个传导结构,传导耦合到采用第二模式设置在有源硅衬底的上表面上的传导结构的第二部分,所述多个传导结构设置在中介层的下表面的伸出第一半导体封装的上表面的那部分周围。
示例23可包括示例11至22中的任一个的元素,其中使第二半导体封装传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分,可包括:经由多个接合线中的至少一些中的每个接合线,使第二半导体封装传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分。
根据示例24,提供有电子装置。电子装置可包括:衬底,所述衬底具有与其传导耦合的硅上封装(PoS)半导体封装,PoS半导体封装包括:有源硅衬底,所述有源硅衬底具有多个传导结构;其中多个传导结构包括:采用第一模式跨有源硅衬底的上表面的至少一部分设置的传导结构的第一部分;以及采用第二模式跨有源硅衬底的上表面的至少一部分设置的传导结构的第二部分;第一半导体封装,所述第一半导体封装具有上表面、下表面和采用第一模式跨第一半导体封装的下表面的至少一部分设置的多个传导凸块;其中所述多个传导凸块使第一半导体封装通信地耦合到设置在有源硅衬底的上表面上的传导结构的第一部分;以及第二半导体封装,所述第二半导体封装具有上表面和下表面;第二半导体封装设置在第一半导体封装的上表面上方;以及第二半导体封装经由多个传导构件通信地耦合到设置在有源硅衬底的上表面上的传导结构的第二部分中的至少一些;其中有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。
示例25可包括示例24的元素,其中第一模式包括设置在50微米(μm)或更少的第一节距上的传导结构;以及其中第二模式包括设置在150μm或更多的第二节距上的传导结构。
示例26可包括示例24或25中的任一个的元素,其中一个或多个粘合剂使第二半导体封装的下表面物理耦合到第一半导体封装的上表面的至少一部分。
示例27可包括示例24至26中的任一个的元素,其中第二半导体封装的下表面伸出第一半导体封装的上表面的边缘的至少一部分。
示例28可包括示例24至27中的任一个的元素,其中第二半导体封装的下表面上的多个传导凸块包括设置在第二半导体封装的伸出第一半导体封装的上表面的那部分周围的多个传导凸块;以及其中多个传导构件包括多个传导柱,所述多个传导柱使多个传导凸块中的至少一些通信地耦合到设置在有源硅衬底上的传导结构的第二部分中的至少一些,所述多个传导凸块设置在第二半导体封装的伸出第一半导体封装的上表面的那部分周围。
示例29可包括示例24至28中的任一个的元素,并且电子装置可另外包括:设置在第一半导体封装的上表面与第二半导体封装的下表面之间的中介层,中介层包括:跨中介层的上表面设置的多个传导衬垫;跨中介层的下表面的至少一部分设置的多个传导结构;以及多个导体,所述多个导体使设置在中介层的上表面上的多个传导衬垫中的至少一些通信地耦合到设置在中介层的下表面上的多个传导结构中的至少一些。
示例30可包括示例24至29中的任一个的元素,其中设置在第二半导体封装的下表面上的多个传导凸块通信地耦合到跨中介层的上表面设置的多个传导衬垫中的对应传导衬垫;以及其中中介层还包括跨中介层的下表面的至少一部分设置的粘合剂,用于使中介层和第二半导体封装物理耦合到第一半导体封装。
示例31可包括示例24至30中的任一个的元素,其中中介层的下表面伸出第一半导体封装的上表面的边缘的至少一部分。
示例32可包括示例24至31中的任一个的元素,其中中介层的下表面上的多个传导结构包括多个传导凸块,所述多个传导凸块设置在有机中介层的伸出第一半导体封装的上表面的那部分周围;以及其中多个传导构件包括多个传导柱,所述多个传导柱使传导凸块中的至少一些通信地耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分,所述传导凸块设置在有机中介层的伸出第一半导体封装的上表面的那部分周围。
示例33可包括示例24至32中的任一个的元素,其中通信地耦合到第二半导体封装的多个传导构件包括通信地耦合到第二半导体封装的多个接合线;以及其中多个接合线中的至少一些中的每个接合线,通信地耦合到设置在有源硅衬底的上表面上的传导结构的第二部分中的至少一些中的每个传导结构。
根据示例34,提供有硅上封装(PoS)半导体封装制造系统。该系统可包括:用于使设置在第一半导体封装的下表面上的多个传导结构中的每个传导结构,传导耦合到采用第一模式跨有源硅衬底的上表面设置的传导结构的第一部分的对应部分的部件;用于使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分的对应部分的部件;其中第二半导体封装可操作地耦合到有源硅衬底,使得第一半导体封装的至少一部分被设置在第二半导体封装的下表面的至少一部分与有源硅衬底的上表面之间;以及经由有源硅衬底使第一半导体封装通信地耦合到第二半导体封装。
示例35可包括示例34的元素,并且该系统可另外包括:用于在第一半导体封装的周边(perimeter)的至少一部分周围设置模制化合物的部件。
示例36可包括示例34或35中的任一个的元素,其中用于使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分的对应部分的部件可包括:用于使具有采用第二模式设置在第二半导体封装的下表面上的多个传导结构的第二半导体封装传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的部件。
示例37可包括示例34至36中的任一个的元素,并且该系统可另外包括:用于使第二半导体封装的下表面的至少一部分物理耦合到第一半导体封装的上表面的至少一部分的部件。
示例38可包括示例34至37中的任一个的元素,其中用于使第二半导体封装的下表面的至少一部分物理耦合到第一半导体封装的上表面的至少一部分的部件可包括:用于使第二半导体封装的下表面的至少一部分物理耦合到第一半导体封装的上表面的至少一部分,使得第二半导体封装的下表面的至少一部分伸出第一半导体封装的上表面的边缘的至少一部分的部件。
示例39可包括示例34至38中的任一个的元素,其中用于使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨有源硅衬底的上表面设置的传导结构的第二部分的对应部分的部件可包括:用于使多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分,所述多个传导结构设置在第二半导体封装的下表面的伸出第一半导体封装的上表面的那部分周围的部件。
示例40可包括示例34至39中的任一个的元素,其中用于使多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分(所述多个传导结构设置在第二半导体封装的下表面的伸出第一半导体封装的上表面的那部分周围)的部件可包括:经由传导柱,使多个传导结构中的至少一些中的每个传导结构,传导耦合到采用第二模式设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分,所述多个传导结构设置在第二半导体封装的下表面的伸出第一半导体封装的上表面的那部分周围。
示例41可包括示例34至40中的任一个的元素,并且该系统还可包括:用于在第一半导体封装的上表面与第二半导体封装的下表面之间设置中介层的部件,中介层包括:跨中介层的上表面设置的多个传导衬垫;
跨中介层的下表面的至少一部分设置的多个传导结构;以及多个导体,所述多个导体使设置在中介层的上表面上的多个传导衬垫中的至少一些通信地耦合到中介层的下表面上的多个传导结构中的至少一些。
示例42可包括示例34至41中的任一个的元素,其中用于使第二半导体封装传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的部件还可包括:用于使采用第二模式设置在第二半导体封装的下表面上的多个传导结构中的至少一些中的每个传导结构,传导耦合到跨中介层的上表面设置的多个传导衬垫中的对应传导衬垫的部件;以及用于使跨中介层的下表面的至少一部分设置的多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分的部件。
示例43可包括示例34至42中的任一个的元素,并且该系统还可包括:用于使中介层的下表面物理耦合到第一半导体封装的上表面的至少一部分,以使中介层和第二半导体封装物理耦合到第一半导体封装的部件。
示例44可包括示例34至43中的任一个的元素,其中用于使中介层的下表面物理耦合到第一半导体封装的上表面的至少一部分的部件还可包括:用于使中介层的下表面物理耦合到第一半导体封装的上表面的至少一部分,使得中介层的下表面的至少一部分伸出第一半导体封装的上表面的边缘的至少一部分的部件。
示例45可包括示例34至44中的任一个的元素,其中用于使跨中介层的下表面的至少一部分设置的多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的对应部分的部件可包括:用于经由传导柱,使多个传导结构中的至少一些中的每个传导结构,传导耦合到采用第二模式设置在有源硅衬底的上表面上的传导结构的第二部分,所述多个传导结构设置在中介层的下表面的伸出第一半导体封装的上表面的那部分周围的部件。
示例46可包括示例34至45中的任一个的元素,其中用于使第二半导体封装传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的部件可包括:用于经由多个接合线中的至少一些中的每个接合线,使第二半导体封装传导耦合到设置在有源硅衬底的上表面上的传导结构的第二部分的部件。
本文已采用的术语和表达用作说明的术语并且无限制,并且在这样的术语和表达的使用中没有排除示出和描述的特征(或其部分)的任何等同物的意图,并且认识到各种修改在权利要求书的范围内是可能的。因此,权利要求书意在涵盖所有这样的等同物。
Claims (25)
1.一种硅上封装(PoS)半导体封装,包括:
有源硅衬底,所述有源硅衬底具有:
上表面;
下表面;以及
跨所述上表面设置的多个传导结构;
其中所述多个传导结构包括:
采用第一模式跨所述有源硅衬底的所述上表面设置的传导结构的第一部分;以及
采用第二模式跨所述有源硅衬底的所述上表面设置的传导结构的第二部分;
第一半导体封装,所述第一半导体封装具有上表面、下表面和采用所述第一模式跨所述第一半导体封装的所述下表面设置的多个传导凸块;
其中所述多个传导凸块使所述第一半导体封装通信地耦合到设置在所述有源硅衬底上的传导结构的所述第一部分;以及
第二半导体封装,所述第二半导体封装具有上表面和下表面;
设置所述第二半导体封装使得所述第一半导体封装的至少一部分被设置在所述第二半导体封装的所述下表面与所述有源硅衬底的所述上表面之间;以及
所述第二半导体封装经由多个传导构件通信地耦合到设置在所述有源硅衬底上的传导结构的所述第二部分中的至少一些,其中所述有源硅衬底使所述第一半导体封装通信地耦合到所述第二半导体封装。
2. 如权利要求1所述的PoS半导体封装:
其中所述第一模式包括设置在50微米(μm)或更少的第一节距上的传导结构;以及
其中所述第二模式包括设置在150μm或更多的第二节距上的传导结构。
3.如权利要求2所述的PoS半导体封装,其中一个或多个粘合剂使所述第二半导体封装的所述下表面物理耦合到所述第一半导体封装的所述上表面的至少一部分。
4.如权利要求3所述的PoS半导体封装,其中所述第二半导体封装的所述下表面伸出所述第一半导体封装的所述上表面的边缘的至少一部分。
5. 如权利要求4所述的PoS半导体封装:
其中所述第二半导体封装的所述下表面上的所述多个传导凸块包括多个传导凸块,所述多个传导凸块设置在所述第二半导体封装的伸出所述第一半导体封装的所述上表面的所述部分周围;以及
其中所述多个传导构件包括多个传导柱,所述多个传导柱使所述多个传导凸块中的至少一些通信地耦合到设置在所述有源硅衬底的所述上表面上的传导结构的所述第二部分中的至少一些,所述多个传导凸块设置在所述第二半导体封装的伸出所述第一半导体封装的所述上表面的所述部分周围。
6.如权利要求2所述的PoS半导体封装,还包括设置在所述第一半导体封装的所述上表面与所述第二半导体封装的所述下表面之间的中介层,所述中介层包括:
跨所述中介层的上表面设置的多个传导衬垫;
跨所述中介层的下表面的至少一部分设置的多个传导结构;以及
多个导体,所述多个导体使设置在所述中介层的所述上表面上的所述多个传导衬垫中的至少一些通信地耦合到设置在所述中介层的所述下表面上的所述多个传导结构中的至少一些。
7. 如权利要求6所述的PoS半导体封装:
其中设置在所述第二半导体封装的所述下表面上的所述多个传导凸块中的至少一些中的每个传导凸块,物理且通信地耦合到跨所述中介层的所述上表面设置的所述多个传导衬垫中的对应传导衬垫;以及
其中所述中介层包括跨所述中介层的所述下表面的至少一部分设置的粘合剂,用于使所述第二半导体封装和所述中介层物理耦合到所述第一半导体封装。
8.如权利要求7所述的PoS半导体封装,其中所述中介层的所述下表面伸出所述第一半导体封装的所述上表面的边缘的至少一部分。
9. 如权利要求8所述的PoS半导体封装;
其中所述中介层的所述下表面上的所述多个传导结构包括多个传导凸块,所述多个传导凸块设置在有机中介层的伸出所述第一半导体封装的所述上表面的所述部分周围;以及
其中所述多个传导构件包括多个传导柱,所述多个传导柱使所述传导凸块中的至少一些中的每个传导凸块,通信地耦合到设置在所述有源硅衬底的所述上表面上的传导结构的所述第二部分中的对应部分,所述传导凸块设置在所述中介层的伸出所述第一半导体封装的所述上表面的所述部分周围。
10. 如权利要求1至9中的任一项所述的PoS半导体封装:
其中通信地耦合到所述第二半导体封装的所述多个传导构件包括多个接合线,所述多个接合线通信地耦合到所述第二半导体封装;以及
其中所述多个接合线中的至少一些中的每个接合线,通信地耦合到设置在所述有源硅衬底的所述表面上的传导结构的所述第二部分的对应部分。
11.一种硅上封装(PoS)半导体封装制造方法,包括:
使设置在第一半导体封装的下表面上的多个传导结构中的每个传导结构,传导耦合到采用第一模式跨有源硅衬底的上表面设置的传导结构的第一部分的对应部分;
使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨所述有源硅衬底的所述上表面设置的传导结构的第二部分的对应部分;
其中所述第二半导体封装可操作地耦合到所述有源硅衬底,使得所述第一半导体封装的至少一部分被设置在所述第二半导体封装的下表面的至少一部分与所述有源硅衬底的所述上表面之间;以及
经由所述有源硅衬底使所述第一半导体封装通信地耦合到所述第二半导体封装。
12.如权利要求11所述的方法,还包括:
在所述第一半导体封装的下表面与所述有源硅衬底的上表面之间设置底部填充材料。
13.如权利要求11所述的方法,其中使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨所述有源硅衬底的所述上表面设置的传导结构的第二部分的对应部分,包括:
使具有采用所述第二模式设置在所述第二半导体封装的所述下表面上的多个传导结构的第二半导体封装传导耦合到设置在所述有源硅衬底的所述上表面上的传导结构的所述第二部分。
14.如权利要求13所述的方法,还包括:
使所述第二半导体封装的所述下表面的至少一部分粘合地耦合到所述第一半导体封装的所述上表面的至少一部分。
15.如权利要求14所述的方法,其中使所述第二半导体封装的所述下表面的至少一部分粘合地耦合到所述第一半导体封装的所述上表面的至少一部分包括:
使所述第二半导体封装的所述下表面的至少所述部分粘合地耦合到所述第一半导体封装的所述上表面的至少所述部分,使得所述第二半导体封装的所述下表面的至少一部分伸出所述第一半导体封装的所述上表面的边缘的至少一部分。
16.如权利要求15所述的方法,其中使设置在第二半导体封装上的多个传导结构中的每个传导结构,传导耦合到采用第二模式跨所述有源硅衬底的所述上表面设置的传导结构的第二部分的对应部分,包括:
使多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在所述有源硅衬底的所述上表面上的传导结构的所述第二部分中的对应部分,所述传导结构设置在所述第二半导体封装的所述下表面的伸出所述第一半导体封装的所述上表面的那部分周围。
17.如权利要求16所述的方法,其中使多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在所述有源硅衬底的所述上表面上的传导结构的所述第二部分的对应部分,所述多个传导结构设置在所述第二半导体封装的所述下表面的伸出所述第一半导体封装的所述上表面的所述部分周围,包括:
经由传导柱,使所述多个传导结构中的至少一些中的每个传导结构,传导耦合到采用所述第二模式设置在所述有源硅衬底的所述上表面上的传导结构的所述第二部分的对应部分,所述多个传导结构设置在所述第二半导体封装的所述下表面的伸出所述第一半导体封装的所述上表面的所述部分周围。
18.如权利要求13所述的方法,还包括:
在所述第一半导体封装的上表面与所述第二半导体封装的所述下表面之间设置中介层,所述中介层包括:
跨所述中介层的上表面设置的多个传导衬垫;
跨所述中介层的下表面的至少一部分设置的多个传导结构;以及
多个导体,所述多个导体使设置在所述中介层的所述上表面上的所述多个传导衬垫中的至少一些通信地耦合到所述中介层的所述下表面上的所述多个传导结构中的至少一些。
19. 如权利要求18所述的方法,其中使第二半导体封装传导耦合到设置在所述有源硅衬底的所述上表面上的传导结构的第二部分,还包括:
使采用所述第二模式设置在所述第二半导体封装的下表面上的所述多个传导结构中的至少一些中的每个传导结构,传导耦合到跨所述中介层的所述上表面设置的所述多个传导衬垫中的对应传导衬垫;以及
使跨所述中介层的下表面的至少一部分设置的所述多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在所述有源硅衬底的所述上表面上的传导结构的所述第二部分的对应部分。
20.如权利要求19所述的方法,还包括:
使所述中介层的所述下表面粘合地耦合到所述第一半导体封装的上表面的至少一部分,以使所述中介层和所述第二半导体封装物理耦合到所述第一半导体封装。
21.如权利要求20所述的方法,其中使所述中介层的所述下表面粘合地耦合到所述第一半导体封装的上表面的至少一部分,还包括:
使所述中介层的所述下表面粘合地耦合到所述第一半导体封装的上表面的至少一部分,使得所述中介层的所述下表面的至少一部分伸出所述第一半导体封装的所述上表面的边缘的至少一部分。
22.如权利要求21所述的方法,其中使跨所述中介层的下表面的至少一部分设置的所述多个传导结构中的至少一些中的每个传导结构,传导耦合到设置在所述有源硅衬底的所述上表面上的传导结构的所述第二部分的对应部分,包括:
经由传导柱,使所述多个传导结构中的至少一些中的每个传导结构,传导耦合到采用所述第二模式设置在所述有源硅衬底的所述上表面上的传导结构的第二部分,所述多个传导结构设置在所述中介层的所述下表面的伸出所述第一半导体封装的所述上表面的所述部分周围。
23.如权利要求11至22中的任一项所述的方法,其中使第二半导体封装传导耦合到设置在所述有源硅衬底的所述上表面上的传导结构的第二部分,包括:
经由多个接合线中的至少一些中的每个接合线,使第二半导体封装传导耦合到设置在所述有源硅衬底的所述上表面上的传导结构的第二部分。
24.一种电子装置,包括:
衬底,所述衬底具有与其传导耦合的硅上封装(PoS)半导体封装,所述PoS半导体封装包括:
有源硅衬底,所述有源硅衬底具有多个传导结构;
其中所述多个传导结构包括:
采用第一模式跨所述有源硅衬底的上表面的至少一部分设置的传导结构的第一部分;以及
采用第二模式跨所述有源硅衬底的所述上表面的至少一部分设置的传导结构的第二部分;
第一半导体封装,所述第一半导体封装具有上表面、下表面和采用所述第一模式跨所述第一半导体封装的所述下表面的至少一部分设置的多个传导凸块;
其中所述多个传导凸块使所述第一半导体封装通信地耦合到设置在所述有源硅衬底的所述上表面上的传导结构的所述第一部分;以及
第二半导体封装,所述第二半导体封装具有上表面和下表面;
所述第二半导体封装设置在所述第一半导体封装的所述上表面上方;以及
所述第二半导体封装经由多个传导构件通信地耦合到设置在所述有源硅衬底的所述上表面上的传导结构的所述第二部分中的至少一些;
其中所述有源硅衬底使所述第一半导体封装通信地耦合到所述第二半导体封装。
25. 如权利要求24所述的电子装置:
其中所述第一模式包括设置在50微米(μm)或更少的第一节距上的传导结构;以及
其中所述第二模式包括设置在150μm或更多的第二节距上的传导结构。
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EP3688801A1 (en) | 2020-08-05 |
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US20210013188A1 (en) | 2021-01-14 |
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