CN111052359A - 附接在偏移引线框管芯附接焊盘和离散管芯附接焊盘之间的集成电路(ic)管芯 - Google Patents

附接在偏移引线框管芯附接焊盘和离散管芯附接焊盘之间的集成电路(ic)管芯 Download PDF

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CN111052359A
CN111052359A CN201880055370.1A CN201880055370A CN111052359A CN 111052359 A CN111052359 A CN 111052359A CN 201880055370 A CN201880055370 A CN 201880055370A CN 111052359 A CN111052359 A CN 111052359A
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package
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M·K·拉姆
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Microchip Technology Inc
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Microchip Technology Inc
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Abstract

一种集成电路(IC)封装(例如功率MOSFET封装)可以包括引线框，该引线框包括：(a)主引线框结构，该主引线框结构包括多个引线，并且限定或位于主引线框平面中；以及(b)偏移引线框管芯附接焊盘(DAP)，偏移引线框管芯附接焊盘(DAP)限定从偏移主引线框平面偏移的偏移平面或位于其中。功率IC封装还可以包括半导体管芯，该半导体管芯具有附接到偏移引线框DAP的第一侧，以及附接到(a)半导体管芯的第二侧和(b)主引线框结构两者的导电元件。包括偏移DAP的引线框可以模拟铜夹的功能，因此消除对铜夹的需要。功率IC封装还可以表现出增强的散热能力。

Description

附接在偏移引线框管芯附接焊盘和离散管芯附接焊盘之间的 集成电路(IC)管芯
相关专利申请
本申请要求2017年10月30日提交的共同拥有的美国临时专利申请号62/578,630的优先权，出于所有目的，该申请的全部内容据此以引用方式并入。
技术领域
本公开涉及半导体封装和封装技术，例如一种具有半导体管芯(例如MOSFET管芯)的集成电路(IC)封装(例如功率MOSFET封装)，该半导体管芯附接在偏移引线框管芯附接焊盘和离散厚管芯附接焊盘(例如离散金属散热块)之间。
背景技术
集成电路(IC)通常形成在保护性封装中，用以处理和组装到印刷电路板上并且保护器件免受损坏。存在大量不同类型的封装。包含被设计为处理显著功率电平的器件(例如功率MOSFET器件)的IC封装可被称为高功率IC封装或简称为功率IC封装。
在典型的功率IC封装例如MOSFET器件中，为了改进器件性能，可能需要向器件施加大电流以帮助降低RDS(on)(漏极源极导通电阻)。解决这一问题的一种技术是应用多导线键合将源极连接到封装引线框。然而，导线电阻和接触电阻限制了这种设计的有效性。另一种技术是将离散铜夹焊料附接在封装引线框上，以将其连接到MOSFET源极端子。然而，这种解决方案增加了成本。
另一种共同技术是将离散铜夹焊料附接到管芯的源极焊盘，并且将另一端焊接到封装引线框焊盘。图1示出了根据这种常规技术形成的示例结构。具体地讲，图1是制造期间示例常规MOSFET DFN(双平面无引线)MOSFET封装10的顶视图。封装10包括引线框12，该引线框12包括管芯附接焊盘(DAP)14和从DAP 14延伸的多个引线指16。MOSFET管芯20例如通过环氧树脂安装到DAP14，并且使用铜夹30固定，铜夹30可以焊料附接到引线框12。然而，铜夹30和相关联的组装步骤通常会给封装增加显著成本，并且可能需要对定制自动化组装设备进行投资。
功率IC封装中的另一个共同问题是例如由于高操作电流的热管理。在上文讨论的常规技术中，功率器件(例如，功率MOSFET)通常被焊料附接到封装引线框的管芯附接焊盘(DAP)上。通过DAP的散热能力通常受到引线框的材料特性和厚度的限制。
发明内容
本发明的实施方案可以将铜夹功能集成到引线框设计中，并且因此可以提供一个或多个以下优点：(a)消除离散铜夹部件成本和部分相关联的组装成本(加上产量损失和周期时间)；(b)消除自动组装设备的资本投资成本；和/或(c)增强封装的散热能力。
本发明的一些实施方案可以将封装引线框的管芯附接焊盘(DAP)转换成源极引线(使用引线形成技术)，并且将DAP焊料附接到MOSFET源极焊盘。例如，一些实施方案修改了常规DAP设计，并且使用形成技术将DAP弯出主引线框平面(例如，向上)以模拟Cu夹。这可以消除焊接在封装引线上的离散Cu夹之间的接触电阻。此外，可以消除安装离散Cu夹的零件和组装成本。
由于DAP区域可以是“空的”或“空缺的”，在一些实施方案中，相对高导热率和厚度(与原始引线框材料相比)的散热块例如相对厚的金属块可以作为漏极连接附接(例如，焊接)到封装引线框，与常规设计相比，这可以增加DAP的散热能力。
一般来说，本领域的普通技术人员出于各种原因不会考虑消除DAP，包括DAP对于管芯附接是关键的这一事实，并且因为工业中的制造商通常已经为他们的产品安装了Cu夹机器。
一个实施方案提供了一种可以包括引线框的IC封装(例如功率MOSFET封装)，该引线框包括：(a)主引线框结构，该主引线框结构包括多个引线，并且限定或位于主引线框平面中；以及(b)偏移引线框管芯DAP，该偏移引线框DAP限定从主引线框平面偏移的偏移平面或位于其中。功率IC封装还可以包括半导体管芯，该半导体管芯具有附接到偏移引线框DAP的第一侧，以及附接到(a)半导体管芯的第二侧和(b)主引线框结构两者的导电元件，例如铜或其他金属散热块。
在一个实施方案中，导电元件至少部分地位于主引线框平面和偏移平面之间的区域中。
在一个实施方案中，导电元件的表面与主引线框结构共面。
在一个实施方案中，在垂直于主引线框平面的方向上，导电元件比主引线框结构更厚(例如，1-5倍或至少2倍)。
在一个实施方案中，在垂直于主引线框平面的方向上，导电元件至少是主引线框结构的两倍厚。
在一个实施方案中，偏移引线框DAP限定用于半导体管芯的源极引线，并且导电元件限定用于半导体管芯的漏极引线。
在一个实施方案中，IC封装包括功率MOSFET封装，并且半导体管芯包括MOSFET管芯。
在一个实施方案中，主引线框结构还包括位于主引线框平面中的至少一个附加的管芯附接焊盘，用于接收至少一个附加的半导体管芯或器件。例如，在一个实施方案中，引线框还包括微控制器管芯附接焊盘(DAP)，并且IC封装包括安装到微控制器DAP的微控制器。微控制器DAP可以形成主引线框结构的位于主引线框平面中的一部分。
另一实施方案提供了一种形成集成电路(IC)封装的方法，该方法包括：提供包括引线框的引线框，该引线框包括(a)包括多个引线并且位于主引线框平面中的主引线框结构，以及(b)位于从主引线框平面偏移的偏移平面中的偏移引线框管芯附接焊盘(DAP)；将半导体管芯的第一侧附接到所述偏移引线框DAP；将导电元件(例如铜或其他金属散热块)附接到半导体管芯的第二侧；以及将导电元件附接到主引线框结构。
在一个实施方案中，在共同步骤中将导电元件附接到半导体管芯的第二侧并且附接到主引线框结构。
在一个实施方案中，该方法包括通过弯曲或以其他方式重新塑形引线框来形成引线框，使得偏移引线框DAP位于偏移平面中。
在一个实施方案中，该方法还包括将至少一个附加的半导体器件(例如，微控制器)安装在至少一个附加管芯附接焊盘上，该附加管芯附接焊盘可以形成位于主引线框平面中的主引线框结构的一部分。
另一个实施方案提供了一种用于集成电路(IC)器件的引线框，包括：包括多个引线的主引线框结构，该主引线框结构位于主引线框平面中；以及用于安装半导体管芯的偏移引线框管芯附接焊盘(DAP)，该偏移引线框DAP位于从主引线框平面偏移的偏移平面中。
附图说明
下文结合附图描述了本公开的示例方面，其中：
图1示出了示例常规功率MOSFET封装；
图2A-2B、3A-3B、4-6、7A-7B和8-10示出了根据本发明的一个实施方案的形成功率IC封装(例如功率MOSFET)的示例工艺；
图11示出了在模制包封之前的示例常规双MOSFET封装组件的顶视图；
图12A示出了根据本发明一个示例实施方案的双MOSFET封装的示例引线框的顶视图；并且
图12B示出了例如根据本发明的一个示例实施方案在焊料附接一对MOSFET和导电元件或“厚DAP”结构(例如，金属块)之后，图12A的示例引线框的顶视图。
具体实施方式
图2A-2B、3A-3B、4-6、7A-7B和8-10示出了根据本发明一个实施方案的用于形成功率IC封装(例如用于功率MOSFET)的示例工艺。图2A和图2B示出了第一步骤，其中在制造引线框100期间或之后，引线框100的选定部分例如引线框DAP 102和/或栅极信号引线104相对于引线框100的主结构106被弯曲或以其他方式形成在平面外(例如，向上或向下)。
图2A示出了引线框100的顶视图(或底视图)，并且图2B示出了通过图2A所示的剖面线A-A的横截面视图。
主引线框结构106可以包括多个引线和/或其他结构。在一些实施方案中，主引线框结构106可以包括一个或多个附加的管芯附接焊盘(例如，如下面讨论的图12A-12B所示)。引线框100的主结构106可以限定主引线框平面PLF或位于其中，而DAP 102和/或栅极信号引线104被弯曲或以其他方式形成在主引线框平面PLF的平面外。主引线框架结构106可以包括引线框架100的总尺寸或覆盖区的任何分数百分比(例如，大于或小于50％)。
在图2B所示的示例实施方案中，DAP 102限定平行于主引线框平面PLF的偏移平面Poffset或位于其中。在其他实施方案中，偏移平面Poffset可以从主引线框平面PLF偏移但不平行于主引线框平面PLF。在例示的示例实施方案中，栅信号引线104也位于偏移平面Poffset中。在其他实施方案中，栅极信号引线104可以限定不同的偏移平面或位于其中，例如，以匹配要安装到DAP 102和栅极信号引线104的MOSFET管芯的三维结构。
DAP 102和栅极信号引线104可以分别经由过渡或耦合区110和112与主引线框结构106的部分连接，过渡或耦合区110和112可以垂直于主引线框平面PLF和/或偏移平面Poffset延伸，或者相对于主引线框平面PLF和/或偏移平面Poffset以不平行、不垂直的角度延伸。例如，在图2B所示的示例中，过渡区110相对于主引线框平面PLF以大约45度的角度延伸。DAP 102和栅极信号引线104可以彼此共面，或者可以例如基于要安装到DAP 102和栅极信号引线104的MOSFET管芯的三维结构位于彼此偏移的偏移平面中。
DAP 102和栅极信号引线104以任何合适的方式并且使用任何合适的制造系统、器件或工艺在具有平面PLF的平面外弯曲或以其他方式形成。例如，任何合适的引线形成夹具或工具(例如气动或手动工具)可用于将引线框100冲压、压制或弯曲成如图2A和图2B所示的形状。
如图3A(顶视图)和图3B(通过图3A所示的线B-B的横截面)所示，引线框100可以被布置在夹具130中，并且MOSFET管芯120可以附接到引线框100的弯曲部分。例如，源极接触区122可以附接(例如，经由焊接或导线键合)到引线框DAP 102，并且栅极接触区124可以附接(例如，经由焊接或导线键合)到栅极信号引线104。示例焊料材料在图3B中以142表示。
如下所述，导电和导热元件150(在本文称为“厚DAP”或“散热块”)然后可以被安装到MOSFET管芯120的自由侧(即，与附接到DAP 102的侧相对)。在一些实施方案中，导电元件150可以包括金属散热块，例如包括铜。导电元件150(例如，金属散热块)150可以具有任何合适的厚度，例如，大于引线框材料厚度，或者约是引线框厚度(例如，1.5倍-2.5倍引线框厚度)的2倍，或者是引线框厚度的至少2倍，或者是引线框厚度的1倍到5倍。
如图3A所示，引线框100可以包括引导或配准特征140，该引导或配准特征140被塑形和/或定位以便利在安装到MOSFET管芯120期间导电元件150(例如，金属散热块)的物理对准和/或引导。因此，在一些实施方案中，引线框结构可以为导电元件的“浮动”对准提供内置引导。
如图4的横截面侧视图所示，导电元件或“厚DAP”150(例如，金属散热块)可以被安装在夹具160上，夹具160可以包括对准或引导结构162，例如加工销。焊膏164可以被施配在导电元件150上。
如图5所示，具有附接的MOSFET 120的引线框100可以经由对准或引导结构162例如经由加工销引导而被布置到导电元件150上。
如图6所示，例如在170所示的位置处，可以执行回流焊料附接工艺。由于引线框DAP 102在主引线框结构106平面外形成/弯曲，导电元件150可以被接收到引线框DAP区域中。
如图7A所示，然后可以从夹具160移除附接有MOSFET 120和导电元件150的引线框100。图7B是图7A所示结构的顶视图，示出了附接到引线框100的MOSFET 120和导电元件150。
如图8所示，引线框胶带176可以被施加到导电元件150的背侧和引线框100的共面部分。
如图9所示，可以施加模制化合物180来包住MOSFET封装。
如图10所示，可以例如通过沿着边缘190切割来分割MOSFET封装，从而限定单个的功率MOSFET封装200。胶带176可以被剥离或以其他方式移除。
图11和图12A-12B示出了根据本发明一个示例实施方案的常规双MOSFET封装组件(图11)和双MOSFET封装组件(图12A-12B)。
图11示出了在模制包封之前的示例常规双MOSFET封装组件的顶视图。常规设计包括引线框、安装在引线框的MCU管芯附接焊盘上的微控制器(MCU)、安装在第一MOSFET管芯附接焊盘上的第一MOSFET(例如高侧MOSFET)，以及安装在第二MOSFET管芯附接焊盘上的第二MOSFET(例如低侧MOSFET)。如所示，每个MOSFET通过许多导线键合耦合到相应的源极焊盘，用于传导高操作电流。
图12A示出了根据本发明一个示例实施方案的双MOSFET封装的示例引线框200的顶视图。引线框200可以包括两个DAP接线片202A和202B，该两个DAP接线片202A和202B例如以类似于前面讨论的DAP接线片102在主引线框结构106平面外(例如，从主引线框平面PLF偏移)形成并且经由过渡区110连接到主引线框结构106(参见图2A和图2B以作参考)的方式，相对于主引线框结构206弯曲或以其他方式形成在平面外(例如，向上)并且经由过渡或耦合区210A和210B连接到主引线框结构206。主引线框结构206包括多个引线、被配置为接收微控制器的MCU附接焊盘254、以及下面讨论的引线框区206A-206C，它们共同限定主引线框平面或位于其中。
图12B示出了在例如根据图3A-7B所示和以上讨论的技术焊料附接一对MOSFET管芯220A、220B和相应对导电元件(例如，金属块)150A、150B之后(并且在模制包封之前)的示例引线框200的顶视图。具体地讲，如图12B所示，第一MOSFET管芯220A(例如，高侧MOSFET)的源极区222A被焊料附接到第一DAP接线片202A，并且第一导电元件(例如，金属块)250A被焊料附接到第一MOSFET管芯220A的背(漏极)侧；并且第二MOSFET管芯220B(例如，低侧MOSFET)的源极区222B被焊料附接到第二DAP接线片202B，并且第二导电元件(例如，金属块)250B被焊料附接到第二MOSFET管芯220B的背(漏极)侧。在一个实施方案中，第一和第二MOSFET管芯220A和220B可以同时焊接到引线框200(具体来讲焊接到DAP接线片202A和202B)，并且第一和第二导电元件(例如，金属块)250A和250B可以同时焊接到MOSFET管芯220A和220B。参考图12B，导电元件250A可以被焊接到第一漏极接触引线框区206A，并且导电元件250B可以被焊接到第二漏极接触引线框区206B。
微芯片(MCU)252可以被固定(例如，通过环氧树脂或焊料附接)到引线框200的MCU附接焊盘254。MCU 252的选定元件可以导线键合到引线框20的引线框指或其他结构。在该示例实施方案中，MOSFET 220A和220B的栅极接触区224A和224B可以导线键合到MCU 252。在另一个实施方案中，引线框200可以包括一对栅极信号引线，该对栅极信号引线可以弯曲或者与DAP接线片202A和202B共面形成，例如类似于图2A-2B和图3A-3B所示的栅极信号引线104，并且MOSFET 220A和220B的每个栅极接触区224A和224B可以被焊料附接到相应的栅极信号引线。
如所示，每个引线框DAP接线片202A、202B限定源极引线，并且每个导电元件250A、250B限定相应的MOSFET 202A、202B的漏极引线。在该示例器件中，第一MOSFET 202A的源极引线(引线框DAP接线片202A)经由过渡/耦合区210A和焊料附接到第二MOSFET 202B的漏极的第二漏极接触引线框区206B导电连接到第二MOSFET 202B的漏极引线(导电元件250B)。此外，第二MOSFET 202的源极引线(引线框DAP接线片202B)经由过渡/耦合区210B导电连接到引线框区206C。例如，与常规设计中的源极和源极焊盘之间的多导线键合连接相比，经由相应引线框结构的这些导电连接可以适于以减小的电阻传导高操作电流。此外，与传统设计相比，焊接到MOSFET漏极侧的导电元件(例如，金属散热块)可以增加器件的散热能力。
尽管本公开详细描述了所公开的实施方案，但应当理解，在不脱离本发明的实质和范围的情况下，可对本实施方案做出各种改变、替换和更改。

Claims (23)

1.一种集成电路(IC)封装，所述集成电路(IC)封装包括：
引线框，所述引线框包括：
主引线框结构，所述主引线框结构包括多个引线，所述主引线框结构位于主引线框平面中；以及
偏移引线框管芯附接焊盘(DAP)，所述偏移引线框管芯附接焊盘位于从所述主引线框平面偏移的偏移平面中；
半导体管芯，所述半导体管芯具有附接到所述偏移引线框DAP的第一侧；以及
导电元件，所述导电元件附接到(a)所述半导体管芯的第二侧和(b)所述主引线框结构。
2.根据权利要求1所述的IC封装，其特征在于，所述导电元件至少部分地位于所述主引线框平面和所述偏移平面之间的区域中。
3.根据权利要求1至2中任一项所述的IC封装，其特征在于，所述导电元件的表面与所述主引线框结构共面。
4.根据权利要求1至3中任一项所述的IC封装，其特征在于，在垂直于所述主引线框平面的方向上，所述导电元件比所述主引线框结构更厚。
5.根据权利要求1至4中任一项所述的IC封装，其特征在于，在垂直于所述主引线框平面的方向上，所述导电元件至少是所述主引线框结构的两倍厚。
6.根据权利要求1至5中任一项所述的IC封装，其特征在于，所述导电元件包括金属散热块。
7.根据权利要求1至6中任一项所述的IC封装，其特征在于：
所述偏移引线框DAP限定用于所述半导体管芯的源极引线；并且
所述导电元件限定用于所述半导体管芯的漏极引线。
8.根据权利要求1至7中任一项所述的IC封装，其特征在于，所述IC封装包括功率MOSFET封装，并且所述半导体管芯包括MOSFET管芯。
9.根据权利要求1至8中任一项所述的IC封装，其特征在于，所述主引线框结构还包括位于所述主引线框平面中的至少一个附加的管芯附接焊盘，用于接收至少一个附加的半导体管芯或器件。
10.根据权利要求1至9中任一项所述的IC封装，其特征在于，所述引线框还包括微控制器管芯附接焊盘(DAP)；并且
所述IC封装包括微控制器，所述微控制器安装到所述微控制器DAP。
11.根据权利要求10所述的IC封装，其特征在于，所述微控制器DAP形成所述主引线框结构的位于所述主引线框平面中的一部分。
12.一种形成集成电路(IC)封装的方法，所述方法包括：
提供包括引线框的引线框，所述引线框包括：
主引线框结构，所述主引线框结构包括多个引线，所述主引线框结构位于主引线框平面中；以及
偏移引线框管芯附接焊盘(DAP)，所述偏移引线框管芯附接焊盘位于从所述主引线框平面偏移的偏移平面中；
将半导体管芯的第一侧附接到所述偏移引线框DAP；
将导电元件附接到所述半导体管芯的第二侧；以及
将所述导电元件附接到所述主引线框结构。
13.根据权利要求12所述的方法，其特征在于，所述IC封装包括功率MOSFET封装，并且所述半导体管芯包括MOSFET管芯。
14.根据权利要求12至13中任一项所述的方法，其特征在于，所述方法包括在共同步骤中将所述导电元件附接到所述半导体管芯的所述第二侧并且附接到所述主引线框结构。
15.根据权利要求12至14中任一项所述的方法，其特征在于，所述方法包括通过弯曲或以其他方式重新塑形所述引线框来形成所述引线框，使得所述偏移引线框DAP位于所述偏移平面中。
16.根据权利要求12至15中任一项所述的方法，其特征在于，在将所述导电元件附接到所述半导体管芯和主引线框结构之后，所述导电元件至少部分地位于所述主引线框平面和所述偏移平面之间的区域中。
17.根据权利要求12至16中任一项所述的方法，其特征在于，在将所述导电元件附接到所述半导体管芯和主引线框结构之后，所述导电元件的表面与所述主引线框结构共面。
18.根据权利要求12至17中任一项所述的方法，其特征在于，在垂直于所述主引线框平面的方向上，所述导电元件至少是所述主引线框结构的两倍厚。
19.根据权利要求12至18中任一项所述的方法，其中所述导电元件包括金属散热块。
20.根据权利要求12至18中任一项所述的方法，其特征在于：
所述偏移引线框DAP限定用于所述半导体管芯的源极引线；并且
所述导电元件限定用于所述半导体管芯的漏极引线。
21.根据权利要求12至12中任一项所述的方法，其特征在于：
所述主引线框结构还包括位于所述主引线框平面中的至少一个附加的管芯附接焊盘；并且
所述方法还包括在所述至少一个附加的管芯附接焊盘上安装至少一个附加的半导体管芯或器件。
22.一种用于集成电路(IC)器件的引线框，所述引线框包括根据权利要求1至11中任一项所述的IC封装的引线框。
23.一种装置，所述装置包括通过根据权利要求12至21中任一项所述的方法形成的集成电路(IC)封装。
CN201880055370.1A 2017-10-30 2018-10-29 附接在偏移引线框管芯附接焊盘和离散管芯附接焊盘之间的集成电路(ic)管芯 Pending CN111052359A (zh)

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