CN110993687B - 一种超结逆导型栅控双极型器件 - Google Patents

一种超结逆导型栅控双极型器件 Download PDF

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CN110993687B
CN110993687B CN201911310477.9A CN201911310477A CN110993687B CN 110993687 B CN110993687 B CN 110993687B CN 201911310477 A CN201911310477 A CN 201911310477A CN 110993687 B CN110993687 B CN 110993687B
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郑崇芝
李青岭
夏云
陈万军
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University of Electronic Science and Technology of China
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    • HELECTRICITY
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/7398Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

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Abstract

本发明涉及功率半导体技术,特别涉及一种超结逆导型栅控双极型器件。与传统超结IGBT相比,本发明器件采用介质隔离层将器件沿超结的纵向分界线分为两部分,第一漂移区一侧正向导通时不参与导电,反向导通时作为二极管起续流作用。第二漂移区一侧,正向导通时为双极导电,内部发生电导调制效应,因此器件导通压降较低,而在反向导通时不参与导电。本发明的有益成果:正向导通时为双极型导电,具有反向导通能力。

Description

一种超结逆导型栅控双极型器件
技术领域
本发明属于功率半导体技术领域,特别涉及一种超结逆导型栅控双极型器件。
背景技术
具有低导通电阻同时具有逆向导通能力的功率器件在很多领域都有应用,如三相逆变电路。IGBT由于其正向导通时为双极导电模式,电导调制效应降低了其正向导通电阻,因此在诸多领域应用。超结IGBT由于其正向耐压时近乎矩形的电场分布,因此其漂移区长度进一步降低,进一步降低了其正向导通电阻。但是由于反向导通时,其体内存在寄生的三极管,因此其不具备反向导通能力。
发明内容
本发明的目的,就是针对超结IGBT无反向导通能力,提出一种超结逆导型栅控双极型器件。
本发明的技术方案是:一种超结逆导型栅控双极型器件,其元胞包括集电极结构、耐压层结构、发射极结构、栅极结构以及绝缘介质结构,其中耐压层结构位于集电极结构之上,发射极结构和栅极结构位于耐压层结构之上,绝缘介质结构垂直插入集电极结构、耐压层结构以及发射极结构的中间;
所述发射极结构包括位于耐压层结构上表面的N型载流子存储区6,所述N型载流子存储区6上表面具有P型阱区8,所述P型阱区8上表面具有并列设置的N+发射极区10和P+体接触区9,且N+发射极区10位于靠近栅极结构的一侧,N+发射极区10和P+体接触区9的共同引出端为发射极E;
所述栅极结构为沟槽栅,所述沟槽栅由绝缘介质11和位于绝缘介质11之中的导电材料12构成;所述导电材料12的引出端为器件的栅极G;所述沟槽栅沿器件垂直方向贯穿P型阱区8和N型载流子存储区6并延伸入耐压层结构中,沟槽栅的侧面与N型载流子存储区6、P型阱区8以及N+型发射极区10的侧面接触;
所述耐压层结构包括第一漂移区4以及第二漂移区5,所述第二漂移区5与第一漂移区4呈间隔分布,所述沟槽栅的底部延伸入第二漂移区5中,第二漂移区5的上表面与N型载流子存储区6下表面接触,所述第一漂移区4的上表面与N型载流子存储区6的下表面接触;所述第一漂移区4的掺杂杂质与第二漂移区5的掺杂杂质是极性相反两种掺杂,所述第一漂移区4与第二漂移区5组成超结结构;
所述集电极结构包括P+集电极区2、N+集电极区1和N型缓冲层3,所述N型缓冲层3的上表面与耐压层相连接,所述P+集电极区2以及N+集电极区1的上表面与N型缓冲层3相连接,所述P+集电极区2与第二漂移区5位于同一侧,且横向宽度大于或等于第二漂移区5的横向宽度,所述N+集电极区1与第一漂移区4位于同一侧,且其横向宽度小于或等于P型漂移区5的横向宽度;所述P+集电极区2以及N+集电极区1的共同引出端为集电极C;
所述绝缘介质结构为绝缘介质7,绝缘介质7位于第一漂移区4及第二漂移区5的垂直分界线处,并沿着垂直分界线处向上依次穿过N型载流子存储区6、P型阱区8以及P+体接触区9,同时沿着垂直分界线处向下穿过N型缓冲层3,其下表面与P+集电极区2接触。
本发明的有益效果为,本发明的逆导型栅控双极型器件,具有逆向导通能力。
附图说明
图1是本发明的超结逆导型栅控双极型器件结构示意图;
图2是本发明的超结逆导型栅控双极型器件结构实施例一;
图3是本发明的超结逆导型栅控双极型器件结构实施例一对应的等效电路图;
图4是本发明的超结逆导型栅控双极型器件结构实施例二;
图5是本发明的超结逆导型栅控双极型器件结构实施例二对应的等效电路图;
图6是常规超结IGBT的结构示意图;
图7是常规超结IGBT的结构对应的等效电路图;
具体实施方式
下面结合附图对本发明进行详细的描述
如图1所示,为本发明的超结逆导型栅控双极型器件。其第一漂移区4和第二漂移区5为掺杂着两种极性相反的杂质,因此分为两种情况:当第一漂移区4为掺杂N型杂质时,第二漂移区5掺杂P型杂质,如图2所示;当第一漂移区4为掺杂P型杂质时,第二漂移区5掺杂N型杂质,如图4所示。
以下对图2所示具体实施例进行分析:
图3为本发明器件的等效电路图。绝缘介质层7将器件分为左右两侧。从图2中可以看出器件右侧为普通的PiN二极管,因此器件可以逆向导通。而器件左侧体内存在一个寄生肖克来二极管(Shockley diode),此肖克来二极管由寄生的PNP晶体管(集电极:P型漂移区5;基区:N型缓冲层3;发射极:P+集电区2)和NPN晶体管(集电极:N型缓冲层3;基区:P型漂移区5;发射极:N型载流子存储区6)组成,由于寄生的PNP的发射区浓度高导致注入效率高,且基区窄并且浓度低,因此PNP的电流放大系数大,因此只需较小的漏电流既可触发此寄生肖克来二极管。肖克来二极管触发后P型漂移区内发生强烈电导调制效应,因此其导通电阻较低。由于栅极沟道电阻的限制,因此左侧区域最终电流会发生饱和。
以下对图4所示具体实施例进行分析:
图5为本发明器件的等效电路图。绝缘介质层7将器件分为左右两侧。从图4中看出器件左侧与普通IGBT结构类似,因此正向导通时,器件左侧会发生电导调制效应,降低器件的正向导通电阻。而器件右侧为反并联的PNPN肖克来二极管,因此器件可以逆向导通。
图6为普通超结IGBT器件结构示意图,图7为对应的等效电路图。由于逆向导通时,超结IGBT等效为PNP三极管,因此其不具备反向导通能力。所以,本发明相对普通超结IGBT器件具有反向导通能力。

Claims (1)

1.一种超结逆导型栅控双极型器件,其元胞包括集电极结构、耐压层结构、发射极结构、栅极结构以及绝缘介质结构,其中耐压层结构位于集电极结构之上,发射极结构和栅极结构位于耐压层结构之上,绝缘介质结构垂直插入集电极结构、耐压层结构以及发射极结构的中间;
所述发射极结构包括位于耐压层结构上表面的N型载流子存储区(6),所述N型载流子存储区(6)上表面具有P型阱区(8),所述P型阱区(8)上表面具有并列设置的N+发射极区(10)和P+体接触区(9),且N+发射极区(10)位于靠近栅极结构的一侧,N+发射极区(10)和P+体接触区(9)的共同引出端为发射极(E);
所述栅极结构为沟槽栅,所述沟槽栅由第一绝缘介质(11)和位于第一绝缘介质(11)之中的导电材料(12)构成;所述导电材料(12)的引出端为器件的栅极(G);所述沟槽栅沿器件垂直方向贯穿P型阱区(8)和N型载流子存储区(6)并延伸入耐压层结构中,沟槽栅的侧面与N型载流子存储区(6)、P型阱区(8)以及N+发射极区(10)的侧面接触;
所述耐压层结构包括第一漂移区(4)以及第二漂移区(5),所述第二漂移区(5)与第一漂移区(4)呈间隔分布,所述沟槽栅的底部延伸入第二漂移区(5)中,第二漂移区(5)的上表面与N型载流子存储区(6)下表面接触,所述第一漂移区(4)的上表面与N型载流子存储区(6)的下表面接触;所述第一漂移区(4)的掺杂杂质与第二漂移区(5)的掺杂杂质是极性相反两种掺杂,所述第一漂移区(4)与第二漂移区(5)组成超结结构;
所述集电极结构包括P+集电极区(2)、N+集电极区(1)和N型缓冲层(3),所述N型缓冲层(3)的上表面与耐压层结构相连接,所述P+集电极区(2)以及N+集电极区(1)的上表面与N型缓冲层(3)相连接,所述P+集电极区(2)与第二漂移区(5)位于同一侧,且横向宽度大于或等于第二漂移区(5)的横向宽度,所述N+集电极区(1)与第一漂移区(4)位于同一侧,且其横向宽度小于或等于第一漂移区(4)的横向宽度;所述P+集电极区(2)以及N+集电极区(1)的共同引出端为集电极(C);
所述绝缘介质结构为第二绝缘介质(7),第二绝缘介质(7)位于第一漂移区(4)及第二漂移区(5)的垂直分界线处,并沿着垂直分界线处向上依次穿过N型载流子存储区(6)、P型阱区(8)以及P+体接触区(9),同时沿着垂直分界线处向下穿过N型缓冲层(3),其下表面与P+集电极区(2)接触。
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