CN110993490A - Method for realizing heterogeneous bonding of chips with different sizes - Google Patents
Method for realizing heterogeneous bonding of chips with different sizes Download PDFInfo
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- CN110993490A CN110993490A CN201911390635.6A CN201911390635A CN110993490A CN 110993490 A CN110993490 A CN 110993490A CN 201911390635 A CN201911390635 A CN 201911390635A CN 110993490 A CN110993490 A CN 110993490A
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 238000002360 preparation method Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 239000000463 material Substances 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- -1 InP Chemical compound 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
Abstract
A method for realizing heterogeneous bonding of chips with different sizes belongs to the field of semiconductor manufacturing and comprises the following steps: 1) preparing a first device chip, a second device chip and a carrier chip, wherein the size of the second device chip is larger than that of the first device chip, the first device chip is a sensor chip, an alignment mark is etched on the first device chip, the second device chip is a logic chip, and a first graph is formed on the second device chip and is used as a bonding alignment mark; 2) bonding the first device chip with the carrier chip; 3) aligning by using a photoetching alignment mark on the first device chip, and forming a second pattern with the same shape as the first pattern on the carrier chip as a bonding alignment mark; 4) the first device chip and the second device chip are aligned to form electrical contacts and bonded together. The invention realizes the effective electrical connection between the small-size device and the large-size device, thereby improving the processing of other semiconductor materials except silicon on the CIS image sensor.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, and particularly relates to a method for realizing heterogeneous bonding of chips with different sizes.
Background
With the continuous development of image sensor technology, the conventional silicon-based materials cannot meet the requirements of special environments and special fields, and other new semiconductor materials, such as compound semiconductors of InP, InGaAs, Ge, InSb, etc., are produced accordingly, and in addition, because the existing special semiconductor preparation equipment cannot realize large-size processing, and the requirement of image sensing process processing technology is relatively high, a large-size machine of 8 inches or 12 inches is generally required, a special method is urgently needed in the prior art to process a small-size chip on a large-size machine, and then realize heterogeneous bonding of the small-size chip and the large-size chip.
Disclosure of Invention
In view of the above problems in the prior art, the present invention provides a method for realizing heterogeneous bonding of chips with different sizes, in which a small-sized device chip is bonded to a large-sized carrier chip, then a bonding alignment mark is made on the large-sized carrier chip, and finally, the electrode interconnection with another large-sized device chip heterogeneous bonding is realized.
The technical scheme adopted by the invention for realizing the purpose is as follows: a method for realizing heterogeneous bonding of chips with different sizes is characterized by comprising the following steps:
step one, early preparation:
preparing three chips, namely a first device chip, a second device chip and a carrier chip, wherein the size of the second device chip is larger than that of the first device chip, the size of the second device chip is the same as that of the carrier chip, the first device chip is a sensor chip and is used for processing a sensor device, an alignment mark is etched on the first device chip, the second device chip is a logic chip and is used for manufacturing a logic circuit, a first graph is formed on the second device chip, and the first graph is used as a bonding alignment mark;
bonding the first device chip and the carrier chip in the step one;
aligning by using the photoetching alignment mark on the first device chip, and forming a second pattern with the same shape as the first pattern on the carrier chip, wherein the second pattern is used as a bonding alignment mark;
and step four, aligning the first device chip and the second device chip to form electrical contact, and bonding the first device chip and the second device chip together.
Further, the size of the first device chip is 2 inches, 3 inches, 4 inches, 5 inches or 6 inches, and the size of the second device chip and the carrier chip is 8 inches or 12 inches.
Preferably, the first pattern and the second pattern are circular in shape.
Preferably, the first graph and the second graph are in a closed graph formed by sequentially connecting more than three line segments end to end.
Through the design scheme, the invention can bring the following beneficial effects: the invention aims to provide a method for realizing heterogeneous bonding of chips with different sizes, which comprises the steps of bonding a small-size device chip to a large-size carrier chip, photoetching an alignment mark by using the bonded small-size device chip, etching a bonding alignment mark on the bonded large-size carrier chip, and bonding two chips together by using the bonding alignment marks on the two large-size chips. The invention effectively solves the processing technical problem that the small-size chip can not be processed on a large-size machine table with 8 inches or 12 inches, and promotes a processing method for applying a new material to an image sensor in a special field.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below in connection with preferred embodiments. As will be appreciated by those skilled in the art. The following detailed description is to be construed as illustrative and not restrictive, and various changes may be made in the following parameters by a user without departing from the spirit and scope of the invention as set forth in the appended claims. Well-known methods and procedures have not been described in detail so as not to obscure the present invention.
The invention provides a method for realizing heterogeneous bonding of chips with different sizes, which comprises the following steps:
step one, early preparation:
preparing three chips, namely a first device chip, a second device chip and a carrier chip, wherein the size of the second device chip is larger than that of the first device chip, the size of the second device chip is the same as that of the carrier chip, the size of the first device chip is 2 inches, 3 inches, 4 inches, 5 inches or 6 inches, the size of the second device chip and the size of the carrier chip are 8 inches or 12 inches, the first device chip is a sensor chip and is used for processing a sensor device, firstly, the first device chip is processed according to the process flow of the sensor chip, the first device chip is made of semiconductor materials except silicon, such as InP, InGaAs, Ge, InSb and the like, then, an alignment mark is etched on the first device chip, no pattern is arranged on the surface of the carrier chip, the method mainly plays a supporting role when the first device chip is processed on a large-size machine table, and the material of the carrier chip is silicon semiconductor material, the bonding principle is surface combined construction connection; the second device chip is a logic chip and is used for manufacturing a logic circuit, manufacturing the second device chip according to the process requirements of the logic circuit chip, and forming a first graph on the chip to be used as a bonding alignment mark so as to be capable of being accurately aligned with the carrier chip on a bonding machine table;
bonding the first device chip and the carrier chip;
and step three, aligning by using the photoetching alignment mark on the first device chip, forming a second pattern with the same shape as the first pattern on the carrier chip as a bonding alignment mark, and finally aiming at aligning by using the bonding alignment mark on the carrier chip and the bonding alignment mark on the second device chip to realize the accurate alignment electrical connection of the first device chip and the second device chip and bond the first device chip and the second device chip together so as to form the effective interconnection of electrodes.
The first pattern and the second pattern are circular, or the first pattern and the second pattern are closed patterns formed by sequentially connecting more than three line segments end to end, but the shape is not limited to this, and other patterns are also possible.
By the method, the alignment and the electrical contact between the small-size sensor chip and the large-size logic chip can be completed, the effective electrical connection between the small-size device and the large-size device is realized, and the processing of other semiconductor materials except silicon on the CIS image sensor is improved.
Claims (4)
1. A method for realizing heterogeneous bonding of chips with different sizes is characterized by comprising the following steps:
step one, early preparation:
preparing three chips, namely a first device chip, a second device chip and a carrier chip, wherein the size of the second device chip is larger than that of the first device chip, the size of the second device chip is the same as that of the carrier chip, the first device chip is a sensor chip and is used for processing a sensor device, an alignment mark is etched on the first device chip, the second device chip is a logic chip and is used for manufacturing a logic circuit, a first graph is formed on the second device chip, and the first graph is used as a bonding alignment mark;
bonding the first device chip and the carrier chip in the step one;
aligning by using the photoetching alignment mark on the first device chip, and forming a second pattern with the same shape as the first pattern on the carrier chip, wherein the second pattern is used as a bonding alignment mark;
and step four, aligning the first device chip and the second device chip to form electrical contact, and bonding the first device chip and the second device chip together.
2. The method for realizing heterogeneous bonding of chips with different sizes according to claim 1, wherein: the size of the first device chip is 2 inches, 3 inches, 4 inches, 5 inches or 6 inches, and the size of the second device chip and the carrier chip is 8 inches or 12 inches.
3. The method for realizing heterogeneous bonding of chips with different sizes according to claim 1 or 2, wherein the method comprises the following steps: the first pattern and the second pattern are circular in shape.
4. The method for realizing heterogeneous bonding of chips with different sizes according to claim 1 or 2, wherein the method comprises the following steps: the first graph and the second graph are in a closed graph formed by sequentially connecting more than three line segments end to end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911390635.6A CN110993490A (en) | 2019-12-30 | 2019-12-30 | Method for realizing heterogeneous bonding of chips with different sizes |
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|---|---|---|---|
| CN201911390635.6A CN110993490A (en) | 2019-12-30 | 2019-12-30 | Method for realizing heterogeneous bonding of chips with different sizes |
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| CN110993490A true CN110993490A (en) | 2020-04-10 |
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| CN201911390635.6A Pending CN110993490A (en) | 2019-12-30 | 2019-12-30 | Method for realizing heterogeneous bonding of chips with different sizes |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112701058A (en) * | 2020-12-30 | 2021-04-23 | 长春长光圆辰微电子技术有限公司 | Method for testing wafer bonding force |
| CN112951713A (en) * | 2021-02-07 | 2021-06-11 | 长春长光圆辰微电子技术有限公司 | Processing method of small-size wafer |
| CN114236983A (en) * | 2021-12-30 | 2022-03-25 | 北海惠科半导体科技有限公司 | Method for manufacturing alignment mark of photoetching machine and wafer |
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