CN110970304A - 半导体处理方法 - Google Patents
半导体处理方法 Download PDFInfo
- Publication number
- CN110970304A CN110970304A CN201910910816.0A CN201910910816A CN110970304A CN 110970304 A CN110970304 A CN 110970304A CN 201910910816 A CN201910910816 A CN 201910910816A CN 110970304 A CN110970304 A CN 110970304A
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- Prior art keywords
- layer
- silicon
- gate dielectric
- metal
- dielectric layer
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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Abstract
实施例为半导体处理方法。方法包括沉积高介电常数的栅极介电层于半导体鳍状物上;沉积阻障层于高介电常数的栅极介电层上;沉积硅钝化层于阻障层上;在硅钝化层上进行氮处理;沉积盖层于硅钝化层上;退火盖层。
Description
技术领域
本发明实施例关于装置与其形成方法,特别关于包括金属硅酸盐层的装置。
背景技术
半导体集成电路产业已经历快速成长。在集成电路演进中,功能密度(定义为单位芯片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作工艺所能产生的最小构件或线路)缩小而增加。尺寸缩小的工艺通常有利于增加产能并降低相关成本。尺寸缩小亦增加处理与形成集成电路的复杂度。为了实现这些进展,形成集成电路的方法需要类似发展。
随着半导体集成电路产业进步至纳米技术工艺节点中以求更高装置密度、更高效能、与更低成本,来自制作与设计的挑战导致三维装置如鳍状场效晶体管的发展。鳍状场效晶体管装置的优点包括减少短通道效应与增加电流。目前需要采用具有高介电常数的栅极介电层与金属栅极的鳍状场效晶体管,以在结构尺寸持续缩小时改善装置效能。
发明内容
本发明一实施例提供的半导体处理方法,包括:沉积高介电常数的栅极介电层于半导体鳍状物上;沉积阻障层于高介电常数的栅极介电层上;沉积硅钝化层于阻障层上;在硅钝化层上进行氮处理;沉积盖层于硅钝化层上;以及退火盖层。
本发明一实施例提供的装置结构,包括:高介电常数的栅极介电层,位于半导体鳍状物上;阻障层,位于高介电常数的栅极介电层上;金属硅酸盐层,位于阻障层上;功函数金属层,位于金属硅酸盐层上;以及金属填充层,位于功函数金属层上。
本发明一实施例提供的半导体处理方法,包括:沉积含有金属氧化物的高介电常数的栅极介电层于半导体鳍状物上;沉积阻障层于高介电常数的栅极介电层上;沉积硅钝化层于阻障层上,其中阻障层与硅钝化层是原位沉积;在硅钝化层上进行氮处理;沉积盖层于硅钝化层上;以及退火硅钝化层,使金属自高介电常数的栅极介电层的金属氧化物扩散以形成金属硅酸盐层。
附图说明
图1是一些实施例中,形成半导体装置的工艺的流程图。
图2是一些实施例中,半导体基板在形成具有虚置栅极结构的半导体装置的一阶段的透视图。
图3至图15是一些实施例中,半导体基板在形成高介电常数的栅极介电层与金属栅极结构的多种阶段的剖视图。
图16是一些实施例中,高介电常数的栅极介电层与金属栅极结构中的原子%含量的图表。
附图标记说明:
A-A 剖线
8 工艺
10、11、12、13、14、15、16、17、18、19 步骤
20 基板
22 鳍状结构
23 凹陷
24 隔离结构
28 虚置栅极结构
30 界面介电层
32 虚置栅极层
34 硬遮罩层
36 间隔物结构
42 源极/漏极区
50 接点蚀刻停止层
52、80 层间介电层
54 栅极沟槽
60 界面层
62 栅极介电层
64 阻障层
66 硅钝化层
67 氮处理
68 盖层
69 退火
70 金属硅酸盐层
72 功函数金属层
76 金属填充层
82 接点
200 图表
具体实施方式
下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件、与配置的实施例是用以简化本发明内容而非局限本发明。举例来说,形成第一构件于第二构件上的叙述包含两者直接接触的实施例,或两者之间隔有其他额外构件而非直接接触的实施例。另一方面,本发明的多个实例可重复采用相同标号以求简洁,但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外,空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件,而非局限于图示方向。元件亦可转动90°或其他角度,因此方向性用语仅用以说明图示中的方向。
高介电常数的栅极介电层与金属栅极结构可用于增加电路效能。一些实施例以置换栅极工艺的内容说明。一些实施例的实施方法可用于其他工艺。举例来说,其他工艺的例子可包含栅极优先工艺。
一些实施例以鳍状场效晶体管的内容说明。鳍状场效晶体管的鳍状物可由任何合适方法图案化。举例来说,鳍状物的图案化方法可采用一或多道光微影(光刻)工艺,包括双重图案化或多重图案化工艺。一般而言,双重图案化或多重图案化工艺结合光微影与自对准工艺,其产生的图案间距小于采用单一的直接光微影工艺所得的图案间距。举例来说,一实施例形成牺牲层于基板上,并采用光微影工艺图案化牺牲层。采用自对准工艺,沿着图案化的牺牲层的侧部形成间隔物。接着移除牺牲层,再采用保留的间隔物图案化鳍状物。一些实施例可用于其他装置。举例来说,其他装置包含水平全绕式栅极场效晶体管、垂直全绕式栅极场效晶体管、纳米线通道晶体管、或其他装置。
工艺、结构、与装置的例子的一些变化将说明如下。本技术领域中技术人员应理解其他调整属于其他实施例的范围中。虽然以特定顺序说明工艺的实施例,但可由任何逻辑性的顺序进行多种其他工艺实施例,且其他工艺实施例可包含比此处所述的步骤更多或更少的步骤。
金属栅极结构包括栅极介电层、栅极介电层上的阻障层、阻障层上的功函数金属层、与功函数金属层上的栅极金属填充层。此处所述的一些实施例关于提供装置与其形成方法,其中装置包括金属硅酸盐层。金属硅酸盐层的形成方法可为采用硅前驱物钝化或形成硅钝化层于阻障层上,并退火金属栅极结构。在这些实施例中,金属栅极结构的介电值增加且装置效能提升。
图1是形成高介电常数的栅极介电层与金属栅极结构的工艺8的例示性流程图,比如图2至图15所示的工艺。图2是结构的透视图,而图3至图15是一些实施例中对应工艺8的多种阶段的基板的一部分的部分剖视图。工艺8可用于形成任何合适结构,包括图2至图15所示的结构或其他可行的半导体结构。
如图2所示,结构包括基板20。基板20可为或包含基体半导体基板、绝缘层上半导体基板、或另一基板。基板20的半导体材料可包含或可为硅(如结晶硅,例如Si<100>或Si<111>)、硅锗、锗、砷化镓、或另一半导体材料。半导体材料可掺杂或未掺杂,比如掺杂p型或n型掺质。在绝缘层上半导体结构作为基板20的一些实施例中,基板20可包含半导体材料位于绝缘层上,其可为位于半导体基板中的埋置绝缘层,或可为玻璃或蓝宝石基板。在这些实施例中,基板20可为硅晶圆。举例来说,基板20可为圆形基板,其直径可为150nn、200mm、300mm、450mm、或其他尺寸。在其他实施例中,基板20可为任何具体尺寸、形状、或材料。举例来说,基板20亦可为任何多边形、方形、矩形、弧形、或其他非圆形的工件。
结构包含一或多个半导体鳍状物,此处视作鳍状结构22。每一鳍状结构提供一或多个电子电路形成其中的主动区。鳍状结构22的制作方法可采用合适工艺,包括遮罩、光微影、及/或蚀刻工艺。蚀刻工艺可形成凹陷23至基板中,并留下延伸的鳍状物如鳍状结构22。凹陷23的蚀刻方法可采用反应性离子蚀刻及/或其他合适工艺。亦可采用其他实施例的方法形成鳍状结构于基板上。举例来说,可外延成长鳍状结构于沟槽中,且鳍状结构可具有与图示结构类似的一般结构。
在这些实施例中,鳍状结构22包括硅材或另一半导体元素如锗,或半导体化合物如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟。鳍状结构22亦可为半导体合金,其包含硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、磷砷化镓铟、或上述的组合。可依需要采用n型及/或p型掺质掺杂鳍状结构22。
可将介电材料填入凹陷23,并回蚀刻介电材料以形成隔离结构24。隔离结构24及/或鳍状结构22所用的其他制作工艺亦属可能。隔离结构24可隔离基板20的一些区域,比如鳍状结构22中的主动区。在这些实施例中,隔离结构24可为浅沟槽隔离结构及/或其他合适的隔离结构。浅沟槽隔离结构的组成可为氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃、低介电常数的介电材料、及/或其他合适的绝缘材料。浅沟槽隔离结构可包含多层结构,比如具有一或多层。
虚置栅极结构28形成于鳍状结构22上。在图2所示的例子中,虚置栅极结构28包含界面介电层30、虚置栅极层32、与硬遮罩层34。虚置栅极结构28亦可包含盖层及/或其他合适层。可由合适的沉积工艺形成虚置栅极结构28中的多种层状物,并以合适的光微影与蚀刻工艺图案化沉积的层状物。虚置栅极结构28接合鳍状结构22的侧部与顶部。此处的用语“虚置”指的是牺牲结构,其可移除于后段阶段中,并可置换为另一结构如置换栅极工艺中的高介电常数的栅极介电层与金属栅极。置换栅极工艺指的是在完整的栅极形成工艺的后段阶段中形成栅极结构。
界面介电层30可为介电氧化物层。举例来说,介电氧化物层的形成方法可为化学氧化、热氧化、原子层沉积、化学气相沉积、及/或其他合适方法。虚置栅极层32可为多晶硅层或其他合适层。举例来说,虚置栅极层32的形成方法可为合适的沉积工艺如低压化学气相沉积或等离子体辅助化学气相沉积。硬遮罩层34可为适于图案化虚置栅极结构28于基板上,使其具有所需结构与尺寸的任何材料。
在这些实施例中,先沉积虚置栅极结构28的多种层如毯状层。以光微影与蚀刻工艺图案化毯状层以移除毯状层的部分,并保留毯状层的其他部分于隔离结构24与鳍状结构22上,以形成虚置栅极结构28。
在这些实施例中,结构可在p型区中以用于形成一或多个p型装置,或在n型区中以用于形成一或多个n型装置。结构可包含于集成电路中,比如逻辑装置、存储器装置、及/或其他集成电路。
在这些实施例中,间隔物结构36形成于虚置栅极结构28的侧壁上,如图3所示。图3是沿着剖线A-A的剖视图,而剖线A-A穿过图2的鳍状结构22之一。间隔物结构36包括的材料与虚置栅极结构28所用的材料不同。间隔物结构36包括介电材料如氮化硅或氮氧化硅。间隔物结构36可为单层或多层。这些实施例在形成虚置栅极结构28之后,可顺应性地沉积间隔物材料于结构上以形成一或多个间隔物层。进行非等向的蚀刻工艺可移除间隔物层的部分,以形成间隔物结构36,如图3所示。
在形成间隔物结构36之后,可进行一或多道外延成长工艺以成长外延的源极/漏极区42。外延的源极/漏极区42可形成于鳍状结构22的凹陷中,或形成于未凹陷的鳍状结构上(未图示)。外延成长工艺可原位掺杂形成p型装置所用的p型掺质(或形成n型装置所用的n型掺质)至外延的源极/漏极区。
之后可形成层间介电层52于基板20及间隔物结构36上。在这些实施例中,结构亦可包含接点蚀刻停止层50于层间介电层52之下与间隔物结构36之上。层间介电层52的材料包含氧化硅(如四乙氧基硅烷所形成的氧化硅)、未掺杂的硅酸盐玻璃、掺杂的氧化硅如硼磷硅酸盐玻璃、掺杂氟的硅酸盐玻璃、磷硅酸盐玻璃、硼硅酸盐玻璃、及/或其他合适的介电材料。层间介电层52的沉积方法可为等离子体辅助化学气相沉积工艺、高密度等离子体化学气相沉积工艺、或其他合适的沉积工艺。层间介电层52至少填入相邻的虚置栅极结构28之间的凹陷23。
进行化学机械研磨工艺,可平坦化层间介电层52与间隔物结构36,以露出虚置栅极结构28。一旦露出虚置栅极结构28,即自基板20移除虚置栅极结构28以定义栅极沟槽54于层间介电层52中,如图4所示。栅极沟槽54露出隔离结构24的表面(未图示于图4)以及鳍状结构22的表面。虚置栅极结构28的移除方法可采用蚀刻工艺,比如干(等离子体)蚀刻、湿蚀刻、及/或其他合适的蚀刻工艺。举例来说,干蚀刻工艺可采用含氯气体、含氟气体、其他蚀刻气体、或上述的组合。湿蚀刻溶液可包含氢氟酸、氢氧化四甲基铵、其他合适的湿蚀刻溶液、或上述的组合。
在图1的工艺8的步骤10中,形成界面层60于栅极沟槽54上,如图5所示。在这些实施例中,界面层60可包含介电材料如氧化硅层、氮氧化硅层、或类似物。界面层60的形成方法可为化学氧化、热氧化、原子层沉积、化学气相沉积、及/或其他合适工艺。界面层60的初始厚度可为约至约虽然图5所示的界面层60形成于鳍状结构22上,界面层60亦可沿着间隔物结构36的侧壁形成。
在图1的工艺8的步骤11中,沉积高介电常数的栅极介电层62于界面层60上,如图6所示。高介电常数的栅极介电层62包含的金属氧化物材料具有高介电常数。举例来说,高介电常数的栅极介电层62可包含氧化铪、氧化铝、氧化镧、氧化钛、氧化铪锆、氧化铪硅、氧化锆、氧化锆硅、氧化钽、氧化钇、氧化锶钛、氧化钡钛、氧化钡锆、氧化铪锆、氮氧化铪锆、氧化铪镧、氧化铪硅、氮氧化铪硅、氧化镧硅、氧化铝硅、氧化铪钽、氧化铪钛、氧化钡锶钛、上述的组合、或其他合适材料。在这些实施例中,高介电常数的栅极介电层62包含氧化镧、氧化镧硅、氧化铪镧、或上述的组合。高介电常数的栅极介电层62的形成方法可为原子层沉积、化学气相沉积、及/或其他合适方法。在其他实施例中,当界面层60不存在时,高介电常数的栅极介电层62可直接形成于基板20上(比如鳍状结构22上)。
在图1的工艺8的步骤12中,沉积阻障层64于高介电常数的栅极介电层62上,如图7所示。阻障层64包含氮化钛、氮化钽、上述的多层、或其他合适材料。在这些实施例中,阻障层64的厚度为约至约可顺应性地沉积阻障层64,且沉积方法可为化学气相沉积工艺如等离子体辅助化学气相沉积、有机金属化学气相沉积、原子层沉积、循环沉积、或其他合适的沉积工艺。
在这些实施例中,阻障层64可为循环沉积如原子层沉积所沉积的氮化钛层。在循环沉积中,可使前驱物的多个循环流向基板表面,以沉积层状物于其上。每一循环包括提供钛前驱物(如氯化钛)的脉冲与氮前驱物(如氨气)的脉冲,以形成氮化钛。在这些实施例中,钛前驱物的流速为约50sccm至约150sccm。在这些实施例中,氮前驱物的流速为约50sccm至约150sccm。在这些实施例中,循环沉积的压力为约1torr至约15torr之间,比如约4torr至约8torr之间。
在钛前驱物与氮前驱物的脉冲之间的净化气体的脉冲,有助于移除基板表面上多余的钛前驱物与氮前驱物以控制成长。除了净化气体的脉冲之外,亦可在钛前驱物的脉冲与氮前驱物的脉冲之间抽气足够的时间,有助于移除基板表面上的多余钛前驱物与氮前驱物以控制成长。在这些实施例中,亦可提供等离子体。举例来说,可提供氮前驱物的脉冲如等离子体。在这些实施例中,每一循环大致可形成氮化钛的单层或原子层。在其他实施例中,每一循环可形成少于一单层,因为只部分吸附或部分反应钛前驱物与氮前驱物。在其他实施例中,每一循环可形成超过一单层,因为只部分移除或未移除基板表面上多余的钛前驱物与氮前驱物。
在其他实施例中,其他钛前驱物可用于取代四氯化钛或与四氯化钛结合,比如碘化钛、溴化钛、四(二甲基酰胺基)钛、四(二乙基酰胺基)钛、或其他合适的钛前驱物。在其他实施例中,其他氮前驱物可用于取代氨或与氨结合,比如联胺、单甲基联胺、二甲基联胺、第三丁基联胺、苯基联胺、2,2’-.偶氮异丁烷、乙基偶氮、氮气、其他合适的氮前驱物、或上述的组合。
在图1的工艺8的步骤13中,沉积硅钝化层于阻障层64上,如图8所示。在这些实施例中,硅钝化层66的组成可为硅或氢化硅。硅钝化层66的沉积方法可为将结构浸入硅前驱物,通过热分解、等离子体分解、或其他合适的沉积工艺以沉积硅。硅前驱物可为硅烷、乙硅烷、丙硅烷、上述的组合、或其他合适的硅前驱物。在这些实施例中,硅钝化层66的沉积厚度为约至约比如约至约硅钝化层66有助于保护阻障层64。若硅钝化层66过薄,则氧可扩散穿过硅钝化层66至下方层如阻障层64、栅极介电层62、及/或界面层60。若氧扩散至界面层60,则会负面影响结构性质,比如改变晶体管的临界电压。若硅钝化层66过厚,则可能抑制氮穿透硅钝化层66至下方层,而负面影响步骤14的氮前驱物处理。
在这些实施例中,硅前驱物的流速为约300sccm至约500sccm。在一些实施例中,亦可提供额外的工艺气体及/或载气如氢气。在这些实施例中,浸入的温度为约400℃至约600℃。若浸入硅前驱物时的温度低于400℃,则硅前驱物的分解不足而无法形成硅层于阻障层64上。举例来说,硅或氢化硅的钝化层的形成方法,可为式(I)中的下述反应:
SiH4(g)→Si(s)+2H2(g) (I)
若在浸入硅前驱物时的温度高于600℃,则难以控制硅材的分解速率。在这些实施例中,提供上述流速的硅前驱物的步骤历时约2分钟至约10分钟。
在图1的工艺8的步骤14中,以氮气处理结构(此处视作氮处理67),如图9所示。氮处理67包括使氮前驱物流向结构。氮前驱物可为氨、联胺、氮气、其他合适的含氮且无氧的前驱物、或上述的组合。在这些实施例中,氮前驱物的流速为约5slm至约15slm,比如约7slm至约11slm。在这些实施例中,氮处理为金属后退火,其温度为约700℃至约1000℃。在这些实施例中,在两步骤的金属后退火工艺中提供氮处理。在这些实施例中,在两步骤或更多步骤中进行金属后退火工艺,可减少因超过预期温度而损伤半导体基板的半导体装置的问题。举例来说,第一步骤包括温度为约700℃至约800℃的第一退火,与温度高于第一退火的温度的第二退火(如约850℃至约930℃)。在另一例中,第一步骤包括温度为约700℃至约800℃且压力为约40torr至约50torr的第一退火,与温度为约850℃至约930℃且压力为约1torr至约10torr的第二退火。
在这些实施例中,氮处理67的此温度与此压力可热氮化结构,使氮穿透至阻障层64、栅极介电层62、及/或界面层60中。若氮处理的温度及/或压力过低,则自氮前驱物解离的氮量可能不足以穿透至结构的层状物中。若氮处理的温度过高,则可能损伤结构。若氮处理的压力过高,则可能因氮前驱物停留在结构的时间短而浪费氮前驱物。在其他实施例中,在结构的等离子体氮化中提供氮等离子体至结构的步骤,可取代热氮化或与热氮化结合。
在这些实施例中,氮处理67可钝化阻障层64、高介电常数的栅极介电层62、及/或界面层60。悬吊键与电荷捕获点位可存在于阻障层64、高介电常数的栅极介电层62、及/或界面层60中,并可存在于阻障层64、高介电常数的栅极介电层62、及/或界面层60之间的界面。自氮处理67导入氮,可钝化悬吊键并消除一些电荷捕获点位(若无氮处理则存在)。在这些实施例中,氮处理67自氮前驱物及/或含金属氮化物如氮化钛的阻障层64,驱动氮至高介电常数的栅极介电层62与界面层60中。在这些实施例中,氮处理67自氮前驱物驱动氮至含金属氮化物如氮化钛的阻障层64中,并使阻障层64致密化以增进阻障层64的阻障性质。
在这些实施例中,在相同的整合工艺系统中进行步骤12、13、与14,而不暴露结构至周围环境或大气。在一些实施例中,可在相同的工艺腔室中进行步骤12与步骤13,或原位地以一工艺配方进行步骤12以沉积阻障层64,并以另一工艺配方进行步骤13以沉积硅钝化层66。在一些实施例中,可在快速热处理腔室中进行步骤14,以快速达到步骤14的高温。在其他实施例中,先进行结构的氮处理的步骤14,再进行步骤13以沉积硅钝化层66。
在图1的工艺8的步骤15中,沉积盖层68于硅钝化层66上,如图10所示。盖层68可包含硅、其他合适材料、或上述的组合。在这些实施例中,盖层68包含硅或氢化硅,其沉积方法可为热分解或等离子体分解硅前驱物(如硅烷、乙硅烷、或上述的组合)或其他合适的沉积工艺。硅或氢化硅的盖层68的形成方法,可如上述的式(I)。在这些实施例中,盖层68的厚度为约至约在这些实施例中,除了硅钝化层66保护阻障层64免于暴露至周围环境或大气以外,盖层68可提供阻障层64额外的保护。
在图1的工艺8的步骤16中,对图10的结构进行退火69(比如盖层后退火),如图11所示。在这些实施例中,退火的温度为约800℃至约1000℃。可在快速热处理腔室中进行退火69。在这些实施例中,退火69会造成硅钝化层66及/或盖层68清除或吸收界面层60、高介电常数的栅极介电层62、及/或阻障层64中的弱键结氧。氧自界面层60、高介电常数的栅极介电层62、及/或阻障层64向外扩散,并与硅钝化层66及/或盖层68反应。在这些实施例中,退火69造成硅钝化层66及/或盖层68自界面层60吸收氧,以减少界面层的厚度。界面层60的厚度可自初始厚度减少超过30%。较薄的界面层60有助于改善晶体管性质。在这些实施例中,结合较薄的界面层60与高介电常数的栅极介电层62,可使高介电常数的栅极介电层与金属栅极结构具有优选的临界电压效能。
在步骤16的退火69时(及/或在步骤14的热氮化时),高介电常数的栅极介电层62的金属与界面层60及/或高介电常数的栅极介电层62的氧扩散至硅钝化层66,以形成金属硅酸盐层70于硅钝化层66及阻障层64的界面。以含有氧化镧及/或氧化镧硅的高介电常数的栅极介电层62为例,扩散的镧跟硅钝化层66中的硅及扩散的氧反应,以形成硅酸镧。以含有氧化铪镧的高介电常数的栅极介电层62为另一例,扩散的镧与扩散的铪跟硅钝化层66中的硅及扩散的氧反应,以形成铪镧硅酸盐。在这些实施例中,金属硅酸盐层70包括高介电常数的介电材料。高介电常数的栅极介电层62与含有高介电常数的介电材料的金属硅酸盐层70,可作为金属填充层76(如图15所示)与鳍状结构22之间的栅极介电层,以帮助降低漏电流并增进装置效能。
在图1的工艺8的步骤17中可移除盖层68,如图12所示。盖层的移除方法可为干蚀刻(如等离子体蚀刻或反应性离子蚀刻)、湿蚀刻、或其他蚀刻工艺。举例来说,蚀刻工艺可为等向蚀刻工艺。在这些实施例中,步骤17亦移除硅钝化层66。举例来说,当盖层68含硅时,步骤17移除硅钝化层66,因为盖层68与硅钝化层66均含硅。在步骤17之后,金属硅酸盐层70保留于阻障层64上。
在图1的工艺8的步骤18中,沉积一或多个功函数金属层72于金属硅酸盐层70上,如图13所示。选择一或多个功函数金属层72以调整鳍状场效晶体管装置的功函数值,以达晶体管所需的临界电压。n型鳍状场效晶体管装置所用的功函数金属层72的例子包含钛、银、钽铝、碳化钽铝、氮化钛铝、碳化钽、碳氮化钽、氮化钽硅、锰、锆、其他合适的功函数材料、或上述的组合。p型鳍状场效晶体管装置所用的功函数金属层72的例子包含氮化钛、氮化钽、钌、钼、铝、氮化钨、锆硅化物、钼硅化物、钽硅化物、镍硅化物、其他合适的功函数材料、或上述的组合。功函数金属层72的厚度可为约至约可顺应性地沉积功函数金属层72,且沉积方法可为化学气相沉积工艺如等离子体辅助化学气相沉积或有机金属化学气相沉积、原子层沉积、循环沉积、或其他合适的沉积工艺。
在图1的工艺8的步骤19中,沉积金属填充层76于功函数金属层72上,如图14所示。在这些实施例中,金属填充层76可包含钨、钴、铝、钌、铜、其他合适金属、上述的多层、上述的组合、或类似物。金属填充层76的沉积方法可为合适工艺如化学气相沉积、物理气相沉积、溅镀、原子层沉积、等离子体辅助化学气相沉积、电镀、或其他沉积工艺。
可进一步处理结构,如图15所示。可对高介电常数的栅极介电层62、阻障层64、金属硅酸盐层70、功函数金属层72、与金属填充层76进行平坦化工艺,比如化学机械研磨工艺或另一合适的平坦化工艺。层间介电层80可沉积于平坦化的结构上,且沉积工艺可为化学气相沉积、物理气相沉积、原子层沉积、高密度等离子体化学气相沉积、有机金属化学气相沉积、或等离子体辅助化学气相沉积。举例来说,层间介电层80可为氧化硅、氮化硅、氮氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、或其他介电层。可图案化层间介电层80以形成开口,其可填有金属(如铜、钨、或其他合适金属)以形成接触源极/漏极区42的接点82。接点82的沉积方法可为物理气相沉积、电化学沉积、化学气相沉积、上述的组合、或其他合适的沉积工艺。
图16是一些实施例中,高介电常数的栅极介电层与金属栅极结构(如图15的结构)的原子%含量的图表200。高介电常数的栅极介电层与金属栅极结构包括含有氧化硅的界面层60、含有氧化铪镧的高介电常数的栅极介电层62、含有氮化钛的阻障层64、以及含有铪镧硅酸盐的金属硅酸盐层70。为了方便说明,图表200省略硅与氮的原子含量。如图表200所示,镧与铪自高介电常数的栅极介电层62扩散以形成金属硅酸盐层70。与氧化硅的界面层60、氮化钛的阻障层64、或铪镧硅酸盐的金属硅酸盐层70相较,镧与铪的峰值浓度在氧化铪镧的高介电常数的栅极介电层62中。自氧化硅的界面层60及/或氧化铪镧的高介电常数的栅极介电层62扩散的氧,可形成铪镧硅酸盐的金属硅酸盐层70,并形成氮化钛阻障层64中的氮氧化钛。在图表200所示的实施例中,氧化铪镧的高介电常数的栅极介电层62维持富氧。若高介电常数的栅极介电层62不富氧,将不利地降低其介电常数。氧化铪镧的高介电常数的栅极介电层62的氧含量,高于氧化硅的界面层60、氮化钛的阻障层64、或铪镧硅酸盐的金属硅酸盐层70的氧含量。
在这些实施例中,高介电常数的栅极介电层与金属栅极结构包括高介电常数的栅极介电层、高介电常数的栅极介电层上的阻障层、阻障层上的金属硅酸盐层、金属硅酸盐层上的功函数金属层、与功函数金属层上的栅极。金属硅酸盐层的形成方法为在形成阻障层及/或盖层后退火工艺之后,采用硅前驱物钝化或形成硅钝化层于阻障层上,并进行金属后退火(比如热氮化)以退火金属栅极结构。在这些实施例中,金属栅极结构的介电值增加且装置效能提升。
一实施例为半导体处理方法。方法包括沉积高介电常数的栅极介电层于半导体鳍状物上。沉积阻障层于高介电常数的栅极介电层上。沉积硅钝化层于阻障层上。在硅钝化层上进行氮处理。沉积盖层于硅钝化层上。退火盖层。
在一实施例中,方法还包括形成界面层于半导体鳍状物上,其中该介电常数的栅极介电层形成于界面层上。
在一实施例中,氮处理将氮驱入高介电常数的栅极介电层,以钝化高介电常数的栅极介电层与界面层。
在一实施例中,沉积阻障层、沉积硅钝化层、与进行氮处理的步骤未暴露阻障层或硅钝化层至大气。
在一实施例中,在相同腔室中沉积阻障层与硅钝化层。
在一实施例中,退火造成硅钝化层与盖层吸收氧。
另一实施例为装置结构。装置结构包括高介电常数的栅极介电层位于半导体鳍状物上。阻障层位于高介电常数的栅极介电层上。金属硅酸盐层位于阻障层上。功函数金属层位于金属硅酸盐层上。金属填充层位于功函数金属层上。
在一实施例中,高介电常数的栅极介电层包括镧。
在一实施例中,阻障层包括氮化钛。
在一实施例中,阻障层包括氮氧化钛。
在一实施例中,金属硅酸盐层包括硅酸镧。
在一实施例中,装置结构还包括界面层于半导体鳍状物上,其中高介电常数的栅极介电层位于界面层上。
在一实施例中,界面层包括的材料是氧化硅、氮氧化硅、或上述的组合。
又一实施例为另一半导体处理方法。方法包括沉积含有金属氧化物的高介电常数的栅极介电层于半导体鳍状物上。沉积阻障层于高介电常数的栅极介电层上。沉积硅钝化层于阻障层上。阻障层与硅钝化层是原位沉积。在硅钝化层上进行氮处理。沉积盖层于硅钝化层上。退火硅钝化层,使金属自高介电常数的栅极介电层的金属氧化物扩散以形成金属硅酸盐层。
在一实施例中,阻障层的沉积方法为循环沉积。
在一实施例中,循环沉积包括流动钛前驱物与氮前驱物,钛前驱物的流速为约50sccm至约150sccm,且氮前驱物的流速为约50sccm至约150sccm。
在一实施例中,硅钝化层的沉积温度为约400℃至约600℃。
在一实施例中,氮处理的热氮化温度为约700℃至约1000℃。
在一实施例中,热氮化包括第一温度为约700℃至约800℃的第一退火,以及第二温度为约850℃至约930℃的第二退火。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础,设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解,这些等效置换并未脱离本发明构思与范围,并可在未脱离本发明的构思与范围的前提下进行改变、替换、或变动。
Claims (1)
1.一种半导体处理方法,包括:
沉积一高介电常数的栅极介电层于一半导体鳍状物上;沉积一阻障层于该高介电常数的栅极介电层上;
沉积一硅钝化层于该阻障层上;
在该硅钝化层上进行一氮处理;
沉积一盖层于该硅钝化层上;以及
退火该盖层。
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