CN110783195A - 半导体装置的形成方法 - Google Patents

半导体装置的形成方法 Download PDF

Info

Publication number
CN110783195A
CN110783195A CN201910405924.2A CN201910405924A CN110783195A CN 110783195 A CN110783195 A CN 110783195A CN 201910405924 A CN201910405924 A CN 201910405924A CN 110783195 A CN110783195 A CN 110783195A
Authority
CN
China
Prior art keywords
layer
semiconductor
fin
region
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910405924.2A
Other languages
English (en)
Inventor
王俊杰
白岳青
杨怀德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110783195A publication Critical patent/CN110783195A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H01L21/02661—In-situ cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本公开涉及一种半导体装置的形成方法，且涉及包含盖层的半导体装置与其形成方法。在一实施例中，方法包括外延成长第一半导体层于n型井上；蚀刻第一半导体层以形成第一凹陷；外延成长第二半导体层以填入第一凹陷；蚀刻第二半导体层、第一半导体层与n型井以形成第一鳍状物；形成浅沟槽隔离区以与第一鳍状物相邻；以及形成盖层于第一鳍状物上，且盖层接触第二半导体层，其中形成盖层的步骤包括：进行预清洁工艺以自第二半导体层的露出表面移除原生氧化物；进行升华工艺以产生第一前驱物；以及进行沉积工艺，其中来自第一前驱物的材料沉积于第二半导体层上以形成盖层。

Description

半导体装置的形成方法
技术领域
本发明实施例涉及半导体装置与其形成方法，特别涉及半导体鳍状物的盖层与其形成方法。
背景技术
半导体装置已用于多种电子应用，比如个人电脑、手机、数码相机与其他电子设备。半导体的制作方法为依序沉积绝缘或介电层、导电层与半导体层的材料于半导体基板上，并采用微影图案化多种材料层以形成电路构件与单元于半导体基板上。
半导体产业持续缩小最小结构尺寸，以持续改善多种电子构件(如晶体管、二极管、电阻、电容或类似物)的集成密度，以整合更多构件至给定面积中。然而随着最小结构尺寸缩小，需解决额外问题。
发明内容
本发明一实施例提供的半导体装置的形成方法，包括：外延成长第一半导体层于n型井上；蚀刻第一半导体层以形成第一凹陷；外延成长第二半导体层以填入第一凹陷；蚀刻第二半导体层、第一半导体层与n型井以形成第一鳍状物；形成浅沟槽隔离区以与第一鳍状物相邻；以及形成盖层于第一鳍状物上，且盖层接触第二半导体层，其中形成盖层的步骤包括：进行预清洁工艺以自第二半导体层的露出表面移除原生氧化物；进行升华工艺以产生第一前驱物；以及进行沉积工艺，其中来自第一前驱物的材料沉积于第二半导体层上以形成盖层。
本发明一实施例提供的半导体装置的形成方法，包括：形成n型井与p型井于基板上；形成第一半导体层于n型井与p型井上，且第一半导体层包括第一半导体材料；蚀刻第一半导体层以形成第一凹陷于n型井上；形成第二半导体层于第一凹陷中，且第二半导体层包括第二半导体材料；蚀刻第一半导体层与第二半导体层以形成第一鳍状物于n型井上，并形成第二鳍状物于p型井上，第一鳍状物包括第二半导体层，且第二鳍状物包括第一半导体层；以及形成盖层于第一鳍状物与第二鳍状物上，且盖层包括第三半导体材料，其中形成盖层的步骤包括：自第二半导体层移除原生氧化物；升华样品以产生前驱物气体；以及自前驱物气体沉积盖层于第一鳍状物与第二鳍状物上。
本发明一实施例提供的半导体装置，包括：第一半导体鳍状物，包括：n型井；第一半导体层，位于n型井上；第二半导体层，位于第一半导体层上；盖层，位于第二半导体层的上表面与侧壁上并接触第二半导体层的上表面与侧壁，盖层包括多晶材料，第一半导体层与第二半导体层包括单晶材料；以及混合层，位于第二半导体层与盖层之间，混合层包括第二半导体层的材料与盖层的材料，且混合层的厚度介于
Figure BDA0002061216780000021
至
Figure BDA0002061216780000022
之间。
附图说明
图1是在一些实施例中，鳍状场效晶体管的三维图。
图2是在一些实施例中，基板上的n型井与p型井的剖视图。
图3是在一些实施例中，形成第一外延层、遮罩层与图案化光刻胶的剖视图。
图4是在一些实施例中，形成第一开口的剖视图。
图5是在一些实施例中，形成第二外延层的剖视图。
图6是在一些实施例中，平坦化第一外延层与第二外延层的剖视图。
图7是在一些实施例中，形成第一半导体鳍状物与第二半导体鳍状物的剖视图。
图8是在一些实施例中，形成绝缘材料的剖视图。
图9是在一些实施例中，平坦化绝缘材料、第一半导体鳍状物与第二半导体鳍状物的剖视图。
图10是在一些实施例中，形成浅沟槽隔离的剖视图。
图11A与图11B是在一些实施例中，形成盖层的剖视图。
图12A与图12B是在一些实施例中，形成虚置介电层、虚置栅极层与遮罩层的剖视图。
图13A与图13B是在一些实施例中，形成虚置栅极、遮罩与栅极密封间隔物的剖视图。
图14A与图14B是在一些实施例中，形成栅极间隔物的剖视图。
图15A至图15D是在一些实施例中，形成外延的源极/漏极区的剖视图。
图16A与图16B是在一些实施例中，形成第一层间介电层的剖视图。
图17A与图17B是在一些实施例中，平坦化第一层间介电层、遮罩、栅极密封间隔物与栅极间隔物的剖视图。
图18A与图18B是在一些实施例中，移除虚置栅极的剖视图。
图19A与图19B是在一些实施例中，形成栅极介电层、功函数层与栅极的剖视图。
图20A与图20B是在一些实施例中，形成第二层间介电层的剖视图。
图21A与图21B是在一些实施例中，形成栅极接点与源极/漏极接点的剖视图。
附图标记说明：
A-A、B-B、C-C 参考剖面
D1 距离
H1 高度
T1、T2、T3、T4、T5 厚度
50、100 基板
56 隔离区
58 鳍状物
82、138 源极/漏极区
92、144 栅极介电层
94、146 栅极
100A 第一区
100B 第二区
100D 密集区
100I 疏离区
102 n型井区
104 p型井区
106 第一外延层
108、132 遮罩层
110 图案化光刻胶
112 第一开口
114 第二外延层
116A 第一半导体鳍状物
116B 第二半导体鳍状物
118 衬垫层
120 介电材料
122 绝缘材料
124 浅沟槽隔离区
126 盖层
127 混合层
128 虚置介电层
130 虚置栅极层
131 虚置栅极
133 遮罩
134 栅极密封间隔物
136 栅极间隔物
140 第一层间介电层
142 凹陷
147 功函数层
148 充填材料
149 自对准接点
150 第二层间介电层
152 栅极接点
154 源极/漏极接点
具体实施方式
下述内容提供的不同实施例或实例可实施本公开的不同结构。特定构件与排列的实施例是用以简化本公开而非局限本公开。举例来说，形成第一构件于第二构件上的叙述包含两者直接或物理接触，或两者之间隔有其他额外构件而非直接接触。此外，本公开的多种例子中可重复标号，但这些重复仅用以简化与清楚说明，不代表不同实施例及/或设置之间具有相同标号的单元之间具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“下侧”、“上方”、“上侧”或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
多种实施例提供改善半导体鳍状物所用的工艺。举例来说，可形成硅盖层于至少部分组成为硅锗的半导体鳍状物上。半导体鳍状物可位于n型井上，且可包含n型井的一部分。盖层的形成方法可采用低温工艺，因此可限制锗自半导体鳍状物向外扩散。具体而言，低温工艺可包含在炉中原位(比如在相同位置或在相同的半导体工艺腔室中)进行预清洁工艺、升华工艺、沉积工艺与冷却工艺。
上述步骤形成的p型半导体鳍状物其弯曲效应可降低(比如沿着p型半导体鳍状物的长度方向弯曲)、其线路边缘粗糙度优选、其漏极诱导能障负载改善、其通道电阻低，且其临界电压变异下降。此外，半导体鳍状物可不具有小翼状物(比如自半导体鳍状物侧壁延伸的三角形凸起)。如此一来，含有这些工艺所形成的半导体鳍状物的半导体装置，具有改善的装置效能。
图1是在一些实施例中，用于参考的鳍状场效晶体管的三维图。鳍状场效晶体管包括鳍状物58于基板50(如半导体基板)上。隔离区56位于基板50中，而鳍状物58自相邻的隔离区56之间凸起。虽然附图与说明中的隔离区56与基板50为不同单元，但此处的用语“基板”可为半导体基板，或者含有隔离区56的半导体基板。栅极介电层92沿着鳍状物58的侧壁并位于鳍状物58的上表面上，而栅极94位于栅极介电层92上。源极/漏极区82位于鳍状物58的两侧中(相对于栅极介电层92与栅极94)。图1亦显示后续附图所用的参考剖面。参考剖面A-A沿着栅极94的纵轴，且其方向垂直于流经鳍状场效晶体管的源极/漏极区82之间的电流方向。参考剖面B-B垂直于参考剖面A-A并沿着鳍状物58的纵轴，其方向为流经鳍状场效晶体管的源极/漏极区82之间的电流方向。参考剖面C-C平行于参考剖面A-A，并延伸穿过鳍状场效晶体管的源极/漏极区82之一。后续附图将依据这些参考剖面以达清楚说明的目的。
此处所述的一些实施例内容为采用栅极后制工艺所形成的鳍状场效晶体管。在其他实施例中，可采用栅极优先工艺。此外，一些实施例可用于平面装置如平面场效晶体管。
图2至图21B是在一些实施例中，形成鳍状场效晶体管的中间阶段的剖视图。图2至图11B显示图1所示的参考剖面A-A，差别在于其具有多个鳍状物及/或鳍状场效晶体管。在图12A至图21B中，附图末尾标示“A”者沿着图1所示的参考剖面A-A，差别在其具有多个鳍状物及/或鳍状场效晶体管；而附图末尾标示“B”者沿着图1所示的参考剖面B-B。图15C与图15D沿着图1所示的参考剖面C-C。
在图2中，提供基板100，其具有n型井区102与p型井区104形成其中。基板100可为半导体基板如基体半导体、绝缘层上半导体基板或类似物，其可掺杂(如掺杂p型掺质或n型掺质)或未掺杂。基板100可为晶圆如硅晶圆。一般而言，绝缘层上半导体基板为半导体材料层形成于绝缘层上。举例来说，绝缘层可为埋置氧化物层、氧化硅层或类似物。可提供绝缘层于基板上，且基板一般为硅基板或玻璃基板。然而亦可采用其他基板如多层基板或组成渐变基板。在一些实施例中，基板100的半导体材料可包含硅、锗、半导体化合物(包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟)、半导体合金(包括硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟及/或磷砷化镓铟)或上述的组合。
基板100可具有第一区100A与第二区100B。第一区100A可用于形成p型装置如p型金属氧化物半导体晶体管(例如p型鳍状场效晶体管)。第二区100B可用于形成n型装置如n型金属氧化物半导体晶体管(例如n型鳍状场效晶体管)。第一区100A与第二区100B之间可物理分隔(如图示的分隔线)，而任何数目的装置结构(如其他主动装置、掺杂区、隔离结构或类似物)可位于第一区100A与第二区100B之间。
可采用遮罩(如光刻胶、氧化物或类似物)覆盖p型井区104，并在n型井区102上进行离子布植工艺，以形成n型井区102于基板100中。可布植n型掺质如砷离子至n型井区102中。可采用遮罩(如光刻胶、氧化物或类似物)覆盖n型井区102，并在p型井区104上进行离子布植工艺，以形成p型井区104形成于基板100中。可布植p型掺质如硼离子至p型井区104中。在一些实施例中，n型井区102可包含n型掺杂的硅，而p型井区104可包含p型掺杂的硅。
在图3中，形成第一外延层106于n型井区102及p型井区104中，形成遮罩层108于第一外延层106上，并形成图案化光刻胶110于遮罩层108上。第一外延层106可为后续形成的n型金属氧化物半导体装置中的通道，且可用于减少后续形成的第二外延层114中的错位缺陷。第一外延层106的形成工艺可为外延成长或类似方法。第一外延层106可包含材料如硅(如单晶硅)或类似物。第一外延层106的晶格常数与n型井区102及p型井区104的晶格常数类似或相同。如下详述，将图案化第一外延层106以形成鳍状物于第二区100B(比如用于n型金属氧化物半导体装置)中，且第一外延层106可作为晶种层以形成另一外延层于第一区100A(比如用于p型金属氧化物半导体装置)中。在一些实施例中，第一外延层106的厚度介于约
Figure BDA0002061216780000071
至约
Figure BDA0002061216780000072
之间。
可由化学气相沉积、原子层沉积或类似方法形成遮罩层108。遮罩层108可包含材料如氧化硅、氮化硅或类似物。可采用旋转涂布技术或类似方法沉积光刻胶材料，再以图案化的能量源(如图案化的光源、电子束源或类似能量源)曝光光刻胶材料，并采用显影剂溶液显影曝光的光刻胶材料，以形成图案化光刻胶110。显影剂溶液可移除光刻胶材料的一部分，以露出遮罩层108的一部分。如图3所示，图案化光刻胶110延伸于p型井区104上而未延伸于n型井区102上。然而在多种其他实施例中，图案化光刻胶110可与n型井区102的至少一部分重叠，或未完全覆盖p型井区104。
在图4中，采用图案化光刻胶110作为遮罩并蚀刻遮罩层108，以及采用遮罩层108作为遮罩并蚀刻第一外延层106，以形成第一开口112。可采用合适的蚀刻工艺如非等向蚀刻工艺，蚀刻遮罩层108与第一外延层106。在一些实施例中，可采用干蚀刻工艺如反应性离子蚀刻、中性束蚀刻、上述的组合或类似方法蚀刻遮罩层108与第一外延层106。在蚀刻遮罩层108之后，可采用合适的光刻胶剥除技术如化学溶液清洁、等离子体灰化、干剥除及/或类似方法移除图案化光刻胶110。在蚀刻第一外延层106之前或之后，可移除图案化光刻胶110。如图4所示，第一开口112可形成于n型井区102上，而不延伸于p型井区104上。然而一些实施例中的第一开口112可延伸于p型井区104的至少一部分上。如图4所示，第一外延层106的至少一部分仍保留为低于第一开口112。保留在n型井区102上的第一外延层106的部分，可用于成长第二外延层114，如搭配图5说明的下述内容。在一些实施例中，蚀刻第一开口112之后，第一外延层106的部分厚度仍维持在约
Figure BDA0002061216780000081
至约
Figure BDA0002061216780000082
之间。在一些实施例中，第一开口112的深度介于约
Figure BDA0002061216780000083
至约
Figure BDA0002061216780000084
之间。
在图5中，形成第二外延层114于第一开口112中。第二外延层114的形成工艺可为外延成长或类似方法。第二外延层114可包含材料如硅锗(如单晶硅锗)或类似物。在第一区100A为p型金属氧化物半导体区的实施例中，第二外延层114包含的材料的晶格常数可大于第一外延层106的晶格常数。举例来说，一些实施例的第二外延层114可包含硅锗。硅锗的能隙小于硅，其较大的空穴迁移率可用于后续形成的p型金属氧化物半导体装置。
如图5所示，第二外延层114可填入第一开口112，使第二外延层114的上表面高于第一外延层106的上表面。第二外延层114可具有一定厚度，使第一外延层106与第二外延层114的平坦化工艺产生平坦表面。在一些实施例中，第二外延层114的至少一部分可延伸于遮罩层108上。
在图6中，移除遮罩层108并在第一外延层106与第二外延层114上进行平坦化工艺。遮罩层108的移除方法可采用合适的蚀刻工艺，比如湿蚀刻工艺(如稀释氢氟酸或类似物)。第一外延层106与第二外延层114的平坦化方法可为任何合适的平坦化工艺，比如化学机械研磨、回蚀刻工艺、上述的组合或类似方法。如图6所示，在平坦化工艺之后，第一外延层106的上表面可与第二外延层114的上表面齐平。在一些实施例中，在平坦化工艺之后，第二外延层114的厚度可介于约
Figure BDA0002061216780000085
至约
Figure BDA0002061216780000086
之间，而第二区100B中的第一外延层106的厚度可介于约
Figure BDA0002061216780000087
至约之间。
在图7中，蚀刻第二外延层114、第一外延层106、n型井区102与p型井区104以形成第一半导体鳍状物116A于第一区100A中，并形成第二半导体鳍状物116B于第二区100B中。在一些实施例中，第一半导体鳍状物116A与第二半导体鳍状物116B的形成方法，可为蚀刻沟槽于第二外延层114、第一外延层106、n型井区102与p型井区104中。蚀刻可为一或多种可接受的任何蚀刻工艺，比如反应性离子蚀刻、中性束蚀刻、类似方法或上述的组合。蚀刻可为非等向。虽然附图中的第一半导体鳍状物116A与第二半导体鳍状物116B具有圆润的角落与直线的边缘，但第一半导体鳍状物116A与第二半导体鳍状物116B可具有任何其他合适形状，比如具有锥形侧壁。在一些实施例中，第一半导体鳍状物116A与第二半导体鳍状物116B的高度可介于约
Figure BDA0002061216780000091
至约
Figure BDA0002061216780000092
之间。
可由任何合适方法图案化第一半导体鳍状物116A与第二半导体鳍状物116B。举例来说，可采用一或多道光微影工艺(如双重图案化或多重图案化工艺)图案化第一半导体鳍状物116A与第二半导体鳍状物116B。一般而言，双重图案化或多重图案化工艺结合光微影与自对准工艺，其产生的图案间距可小于采用单一直接光微影工艺所得的图案间距。虽然未图示双重图案化或多重图案化工艺，一实施例中的双重图案化或多重图案化工艺可包含形成牺牲层于基板上。采用光微影工艺图案化牺牲层。采用自对准工艺沿着牺牲层的侧部形成间隔物。接着移除牺牲层，而保留的间隔物可用于图案化第一半导体鳍状物116A与第二半导体鳍状物116B。
由于第一区110A(如p型金属氧化物半导体区)中的第一半导体鳍状物116A中包含组成为硅锗的第二外延层114，因此可增加后续形成的p型金属氧化物半导体晶体管的空穴迁移率。此外，由于锗的能带隙低于硅，第一半导体鳍状物116A中包含的第二外延层114可造成后续形成的p型金属氧化物半导体晶体管中的较高电流。
在图8中，形成绝缘材料122于基板100、第一半导体鳍状物116A与第二半导体鳍状物100B上，以填入第一半导体鳍状物116A与第二半导体鳍状物116B之间的开口。在一些实施例中，绝缘材料122包含衬垫层118与衬垫层118上的介电材料120，如图8所示。衬垫层118的组成可为顺应性的层状物，其水平部分与垂直部分的厚度彼此相近。
在一些实施例中，在含氧环境中氧化基板100、第一半导体鳍状物116A与第二半导体鳍状物116B的露出表面(如局部氧化硅)以形成衬垫层118，其中氧气可包含在个别的工艺气体中。在其他实施例中，衬垫层118的形成方法可采用具有水蒸汽或氢气与氧气的组合气体进行原位蒸汽产生法，以氧化基板100、第一半导体鳍状物116A与第二半导体鳍状物116B的露出表面。可升温进行原位蒸汽产生氧化。在其他实施例中，采用沉积技术如原子层沉积、化学气相沉积、次压化学气相沉积、类似方法或上述的组合形成衬垫层118。在一些实施例中，衬垫层118的厚度可介于约至约
Figure BDA0002061216780000102
之间。
形成介电材料120以填入第一半导体鳍状物116A与第二半导体鳍状物116B之间的开口的剩余部分。介电材料120可超填第一半导体鳍状物116A与第二半导体鳍状物116B之间的开口，因此介电材料120的一部分延伸于第一半导体鳍状物116A与第二半导体鳍状物116B的上表面上。在一些实施例中，介电材料120可包含氧化硅、碳化硅、氮化硅、类似物或上述的组合，且其形成方法可采用可流动的化学气相沉积、旋转涂布、化学气相沉积、原子层沉积、高密度等离子体化学气相沉积、低压化学气相沉积、类似方法或上述的组合。在沉积介电材料120之后，可进行退火及/或硬化步骤，以将可流动的介电材料转换成固体介电材料。在一些实施例中，由于不同的材料特性(如不同的材料形态及/或不同密度)，可分辨衬垫层118与介电材料120之间的界面。
在图9中，对绝缘材料122进行平坦化工艺。在一些实施例中，平坦化工艺包含化学机械研磨、回蚀刻工艺、上述的组合或类似方法。如图9所示，平坦化工艺可露出第一半导体鳍状物116A与第二半导体鳍状物116B的上表面。亦可由平坦化工艺平坦化第一半导体鳍状物116A与第二半导体鳍状物116B的部分。在完成平坦化工艺之后，第一半导体鳍状物116A、第二半导体鳍状物116B与绝缘材料122的上表面齐平。
在图10中，使绝缘材料122凹陷以形成浅沟槽隔离区124。由于绝缘材料122凹陷，第一区100A与第二区100B中的第一半导体鳍状物116A与第二半导体鳍状物116B自相邻的浅沟槽隔离区124之间凸起。如图10所示，绝缘材料122可凹陷，因此第一外延层106、第二外延层114与n型井区102及p型井区104的至少部分自浅沟槽隔离区124凸起。n型井区102与p型井区104可自浅沟槽隔离区124凸起，且凸起的距离D1介于约
Figure BDA0002061216780000111
至约
Figure BDA0002061216780000112
之间。第一半导体鳍状物116A与第二半导体鳍状物116B的露出部分，其自浅沟槽隔离区的上表面至第一半导体鳍状物116A与第二半导体鳍状物116B的上表面的高度H1介于约
Figure BDA0002061216780000113
至约之间。可采用可接受的蚀刻工艺(如对浅沟槽隔离区124的材料具有选择性的蚀刻工艺)，使浅沟槽隔离区124凹陷。举例来说，可采用无等离子体的气相蚀刻工艺(如采用氢氟酸气体、氨气或类似物的蚀刻工艺)、远端等离子体辅助干蚀刻工艺(如采用氢气、三氟化氮与氨副产物或类似物的工艺)或稀释氢氟酸。
在图11A与图11B中，形成盖层126于第一半导体鳍状物116A与第二半导体鳍状物116B的露出部分上。盖层126可形成于第一半导体鳍状物116A与第二半导体鳍状物116B上，以减少自第一半导体鳍状物116A向外扩散至后续形成的上方层中的锗。在一些实施例中，盖层126的组成可为硅如多晶硅或类似物。盖层126的晶格常数可小于第二外延层114的晶格常数，且可与第一外延层106的晶格常数大致相同。盖层126的厚度可介于约
Figure BDA0002061216780000115
至约
Figure BDA0002061216780000116
之间。盖层126的形成方法可为化学气相沉积、炉化学气相沉积、外延成长或类似方法。在特定实施例中，盖层126的形成方法可为装载图10所示的基板100至炉中、在第一半导体鳍状物116A与第二半导体鳍状物116B上进行预清洁工艺、进行升华工艺、沉积盖层于第一半导体鳍状物116A与第二半导体鳍状物116B上以及冷却基板100。
在形成盖层126的初始步骤中，可在第一半导体鳍状物116A与第二半导体鳍状物116B的露出部分上进行预清洁工艺，以移除氧化第一半导体鳍状物116A与第二半导体鳍状物116B的露出表面所形成的原生氧化物。在一些实施例中，可采用工艺气体如氢氟酸为主的气体、硅钴镍为主的气体或类似物进行预清洁。在其他实施例中，预清洁可采用具有蚀刻剂如含氢氟酸的溶液的湿蚀刻，但亦可采用其他蚀刻剂(如氢气)与其他方法(如反应性离子蚀刻、具有蚀刻剂如氨及/或三氟化氮的干蚀刻、化学氧化物移除或干式化学清洁)。在这些实施例中，预清洁可采用氨的远端等离子体预清洁工艺。将基板100装载至炉中之后，可原位(比如在相同位置或在相同的半导体工艺腔室中)进行预清洁工艺。在其他实施例中，将基板100装载至炉中之前，可非原位进行预清洁工艺。预清洁工艺的温度可介于约50℃至约350℃之间，压力可介于约0.5Torr至约700Torr之间，且时间可介于约5秒至约250秒之间。预清洁工艺可采用载气如氩气，且用于预清洁工艺的气体(如工艺气体与载气)的流速可介于约0.1SLM至约100SLM之间。预清洁工艺可改善盖层126与第一半导体鳍状物116A及第二半导体鳍状物116B之间的粘着性。
在炉中进行升华工艺，以准备沉积盖层126所用的前驱物气体。可用于沉积盖层126的前驱物包含硅烷(SiH4)、二氯硅烷(SiH2Cl2)、乙硅烷(Si2H6)、上述的组合或类似物。在一些实施例中，可在载气如氢气的存在下升华硅。升华工艺可在氢气环境下进行。升华工艺的温度可介于约50℃至约300℃之间。在升华工艺时，炉中的氢气分压可介于约1mTorr至约4mTorr之间。在沉积盖层126于第一半导体鳍状物116A与第二半导体鳍状物116B上之前，可采用升华工艺稳定炉中的温度、压力与前驱物气体流速。此外，采用特定工艺条件(如温度与压力)进行升华工艺，可减少锗自第一半导体鳍状物116A向外扩散至环境，以改善第一半导体鳍状物116A的材料与后续沉积的盖层126的材料之间的陡峭锗浓度(比如锗浓度变化)。
接着升高炉温以在盖层沉积工艺中，沉积盖层126于第一半导体鳍状物116A与第二半导体鳍状物116B上。在一实施例中，增加炉温会造成前驱物气体分解，使来自前驱物气体的硅沉积于第一半导体鳍状物116A与第二半导体鳍状物116B上。炉温可升高至介于约200℃至约450℃之间，比如介于约340℃至约380℃之间。炉压可介于约0Torr至约120Torr之间。盖层126的沉积工艺可持续约5秒至约100秒。在盖层126的沉积工艺时，氢气可与前驱物气体一起流动于基板100上，且流速可介于约200sccm(即0.2slm)至约5000sccm(即5slm)之间。在盖层126的沉积工艺时，在基板100上流动的前驱物气体(如硅烷、乙硅烷、上述的组合或类似物)的流速可介于约200sccm至约800sccm之间。采用特定工艺条件(如沉积时间、温度与压力)沉积盖层126，以及将氢气搭配前驱物气体，均可减少自第一半导体鳍状物116A向外扩散至环境与盖层126中的锗，并改善第一半导体鳍状物116A的材料与盖层126的材料之间的陡峭锗浓度(比如锗浓度变化)。
接着冷却基板100。可让冷却气体如氮气或类似物流过基板100上，或采用盘水管或类似物以冷却基板100。冷却气体的温度可介于约25℃至约380℃之间。基板100的冷却时间可介于约20秒至约120秒之间。基板100可冷却至介于约60℃至约18℃之间。
最终盖层126的界面陷阱密度(每平方公分的悬吊键浓度)小于约1×1011cm-2eV-1。在一些实施例中，在盖层126的硅材料与第一半导体鳍状物116A的硅锗材料之间有一些混合，可产生混合层127(如图11所示的虚线)于与盖层126相邻的第一半导体鳍状物116A中。混合层127的锗浓度，可低于第一半导体鳍状物116A的第二外延层114的其余部分的锗浓度，因此混合层127可称作第一半导体鳍状物116A的空乏区。混合层127的厚度可介于约
Figure BDA0002061216780000131
至约
Figure BDA0002061216780000132
之间。盖层126的底部的厚度T1可介于约至约
Figure BDA0002061216780000134
之间。盖层126的中间部分(位于图10中露出的第一半导体鳍状物116A与第二半导体鳍状物116B的一半上)的厚度T2，可介于约至约
Figure BDA0002061216780000135
之间。位于第一半导体鳍状物116A与第二半导体鳍状物116B的上表面上的盖层126的部分，其厚度T3可介于约
Figure BDA0002061216780000138
至约
Figure BDA0002061216780000137
之间。盖层126的平均厚度可介于约至约
Figure BDA00020612167800001310
之间，比如约
Figure BDA00020612167800001311
在一些实施例中，盖层126可选择性地形成于第一半导体鳍状物116A与第二半导体鳍状物116B上，而不形成于浅沟槽隔离区124上。然而在其他实施例中，盖层126的材料可沉积于浅沟槽隔离区124上。盖层126形成于浅沟槽隔离区124上的现象有时可称作选择性损失，因为在理想工艺中的盖层126的材料只成长于第一半导体鳍状物116A与第二半导体鳍状物116B的露出部分上，而不成长于浅沟槽隔离区124上(如完全选择性)。浅沟槽隔离区124上的选择性损失可小于约
Figure BDA00020612167800001312
与其他工艺相较，依据上述低温工艺形成盖层126，可减少自第一半导体鳍状物116A向外扩散至环境与盖层126中的锗，因此第一半导体鳍状物116A的材料与盖层126的材料之间的锗浓度变化较陡峭。这会造成盖层126与第一半导体鳍状物116A之间的混合层127的厚度，比其他工艺形成的盖层中的混合层厚度小。盖层126、混合层127与第一半导体鳍状物116A中的锗浓度可随着深度变化。举例来说，盖层126中的锗浓度可为约0原子％。混合层127中的锗浓度在盖层126的边界处近似0原子％并可快速增加，且在靠近第一半导体鳍状物116A的深度开始趋于平缓。随着深度增加，介于约15原子％至约30原子％之间的锗浓度可变的平缓(比如锗浓度不再上升或下降)。举例来说，第一半导体鳍状物116A中的锗浓度可介于约15原子％至约30原子％之间。
此外，自半导体鳍状物向外扩散的锗会造成半导体鳍状物弯曲(称作弯曲效应)，这会增加半导体鳍状物的线路边缘粗糙度。此外，向外扩散的锗会造成自半导体鳍状物的最低侧壁延伸出三角形凸起物(称作小翼状物)。自半导体鳍状物向外扩散的锗造成的这些变异，会造成后续形成的晶体管的临界电压变异。
依据上述低温工艺形成第一半导体鳍状物116A，可减少自半导体鳍状物116A向外扩散的锗。因为向外扩散的锗减少，可减少第一半导体鳍状物116A中的弯曲效应(比如沿着第一半导体鳍状物116A的长度弯曲)，改善(如降低)第一半导体鳍状物116A的线路边缘粗糙度并减少形成与第一半导体鳍状物116A相邻的小翼状物。这些改善会造成后续形成的晶体管的临界电压变异下降。在一些实施例中，形成盖层126之后的第一半导体鳍状物116A其线路边缘粗糙度可小于约10nm或小于约0.1nm。
图11B显示疏离区110I与密集区100D中的第一半导体鳍状物116A。如图11B所示，基板100可包含疏离区110I与密集区100D，其中密集区100D定义为具有高密度的鳍状物于其上的区域(比如鳍状物密度介于约8鳍状物/单位至约30/单位之间)，而疏离区100I定义为具有低密度的鳍状物于其上的区域(比如鳍状物密度介于约1鳍状物/单位至约8鳍状物/单位之间)。上述形成盖层126所用的低温工艺，其压力介于约0Torr至约120Torr之间。此低压会造成前驱物气体撞击第一半导体鳍状物116A的比例更对称。与采用高压的工艺相较，低压可改善形成盖层126所用的沉积工艺的一致性。如此一来，疏离区100I中的盖层126的厚度T4与密集区100D中的盖层126的厚度T5之间的差异可小于约比如约
Figure BDA0002061216780000142
或小于约
Figure BDA0002061216780000143
采用上述低温工艺形成盖层126，可减少疏离区100I与密集区100D之间的盖层126的厚度差异，即可降低疏离-密集的负载效应。
盖层126与第一半导体鳍状物116A的组合可作为后续形成的晶体管中的p型通道，而盖层126与第二半导体鳍状物116B的组合可作为后续形成的晶体管中的n型通道。形成硅锗的第一半导体鳍状物116A，造成p型完全应变通道具有降低的通道电阻与高效迁移率。与其他工艺所形成的半导体鳍状物或包含不同材料的半导体鳍状物相较，第一半导体鳍状物116A可提供良好的漏极诱导能障负载与良好的开启电流-关闭电流(如高开启电流与低漏电流)。形成盖层126于第一半导体鳍状物116A上，可减少硅锗所形成的第一半导体鳍状物116A中的缺陷。
图12A至图21B显示形成实施例装置的多种额外步骤。图12B、图13B、图14B、图15B至图15D、图16B、图17B、图18B、图19B、图20B与图21B显示第一区100A与第二区100B中的结构。举例来说，图12B、图13B、图14B、图15B至图15D、图16B、图17B、图18B、图19B、图20B与图21B所示的结构可用于第一区100A与第二区100B。第一区100与第二区100B的结构中的差异(若存在)将搭配每一图说明。
在图12A与图12B中，形成虚置介电层128于盖层126与浅沟槽隔离区124上。举例来说，虚置介电层128可为氧化硅、氮化硅、上述的组合或类似物，且其形成方法可为依据可接受的技术进行沉积或热成长。虚置栅极层130形成于虚置介电层128上，而遮罩层132形成于虚置栅极层130上。可沉积虚置栅极层130于虚置介电层128上，接着平坦化(如化学机械研磨)虚置栅极层130。可沉积遮罩层132于虚置栅极层130上。虚置栅极层130可为导电材料，比如非晶硅、多晶硅、多晶硅锗、金属的氮化物、金属的硅化物、金属的氧化物或金属。虚置栅极层130的沉积方法可为物理气相沉积、化学气相沉积、溅镀沉积或其他本技术领域中用于沉积导电材料的已知技术。虚置栅极层130的组成可为其他材料，其与隔离区之间具有高蚀刻选择性。举例来说，遮罩层132可包含氮化硅、氮氧化硅或类似物。在此例中，形成单一虚置栅极层130与单一遮罩层132于整个区域(第一半导体鳍状物116A与第二半导体鳍状物116B形成其中的区域)。在一些实施例中，分开的虚置栅极层130与分开的遮罩层132可形成于第一半导体鳍状物116A形成其中的区域中，以及形成于第二半导体鳍状物116B形成其中的区域中。
在图13A与图13B中，可采用可接受的光微影与蚀刻技术图案化遮罩层132以形成遮罩133。通过可接受的蚀刻技术，可将遮罩133的图案转移至虚置栅极层130，以形成虚置栅极131。在一些实施例中，亦可将遮罩133的图案转移至虚置介电层128。虚置栅极131覆盖第一半导体鳍状物116A与第二半导体鳍状物116B的个别通道区。遮罩133的图案可用于物理分隔每一虚置栅极131。虚置栅极层131的纵向方向可实质上垂直于第一半导体鳍状物116A与第二半导体鳍状物116B的纵向方向。
如图13B所示，可形成栅极密封间隔物134于虚置栅极131、虚置介电层128、遮罩133及/或第一半导体鳍状物116A与第二半导体鳍状物116B的露出侧壁上。可在热氧化或沉积后进行非等向蚀刻，以形成栅极密封间隔物134。虽然图13B仅显示一个栅极密封间隔物134，但其可包含多个层状物。
在形成栅极密封间隔物134之后，可进行轻掺杂源极/漏极区(未图示)所用的布植。在具有不同装置形态的实施例中，可形成遮罩如光刻胶于第一区100A上并露出第二区100B，且可布植合适形态(如n型)的杂质至第二区100B中露出的第二半导体鳍状物116B中。接着可移除遮罩。接着可形成遮罩如光刻胶于第二区100B上并露出第一区100A，并可布植合适形态(如p型)的杂质至第一区100A中露出的第一半导体鳍状物116A中。接着可移除遮罩。n型杂质可为磷、砷或类似物，且p型杂质可为硼、二氟化硼或类似物。轻掺杂的源极/漏极区的杂质浓度可介于约1015cm-3至约1016cm-3之间。可进行退火以活化布植的杂质。
在图14A与图14B中，栅极间隔物136形成于沿着虚置栅极131与遮罩133的栅极密封间隔物134上。栅极间隔物136的形成方法可为顺应性地沉积材料，接着非等向蚀刻材料。栅极间隔物136的材料可为氮化硅、碳氮化硅、上述的组合或类似物。栅极间隔物136可包含单层或多层。
在图15A至图15D中，外延的源极/漏极区138形成于第一半导体鳍状物116A与第二半导体鳍状物116B中。由于外延的源极/漏极区138形成于第一半导体鳍状物116A与第二半导体鳍状物116B中，每一虚置栅极131位于个别相邻的一对外延的源极/漏极区138之间。在一些实施例中，外延的源极/漏极区138可延伸至第一半导体鳍状物116A与第二半导体鳍状物116B中。在一些实施例中，栅极间隔物136用于使外延的源极/漏极区138与虚置栅极131隔有一段合适的横向距离，因此外延的源极/漏极区138与最终鳍状场效晶体管中后续形成的栅极之间产生短路。
第一区100A(比如p型金属氧化物半导体区)中外延的源极/漏极区138的形成方法，可为遮罩第二区100B(比如n型金属氧化物半导体区)并蚀刻第一区100A中的第一半导体鳍状物116A的源极/漏极区，以形成凹陷于第一半导体鳍状物116A中。接着外延成长第一区100A中外延的源极/漏极区138于凹陷中。在一些实施例中，外延的源极/漏极区138可延伸穿过第二外延层114与第一外延层106，直到第一区100A中的n型井区102中。外延的源极/漏极区138可包含适用于p型鳍状场效晶体管的可接受的任何材料。举例来说，第一区100A中外延的源极/漏极区138可包含硅锗、硼化硅锗、锗、锗锡或类似物。第一区100A中外延的源极/漏极区138的材料组成的晶格常数，可大于第二外延层114的晶格常数，以产生通道区中的压缩应力，进而增加p型金属氧化物半导体装置所用的空穴迁移率。第一区100A中外延的源极/漏极区138可具有自第一半导体鳍状物116A的个别表面隆起的表面，并可具有晶面。
第二区100B(如n型金属氧化物半导体区)中外延的源极/漏极区138的形成方法可为遮罩第一区100A(如p型金属氧化物半导体区)，并蚀刻第二区100B中的第二半导体鳍状物116B的源极/漏极区，以形成凹陷于第二半导体鳍状物116B中。接着外延成长第二区100B中的外延的源极/漏极区138于凹陷中。外延的源极/漏极区138可包含任何可接受的材料，比如适用于n型鳍状场效晶体管的材料。举例来说，第二区100B中外延的源极/漏极区138可包含硅、碳化硅、碳磷化硅、磷化硅或类似物。第二区100B中外延的源极/漏极区138的材料组成的晶格常数，可小于第一外延层106的晶格常数，以产生拉伸应力于通道区中，进而增加n型金属氧化物半导体装置所用的电子迁移率。第二区100B中外延的源极/漏极区138亦可具有自第二半导体鳍状物116B的个别表面隆起的表面，并可具有晶面。
可布植掺质至外延的源极/漏极区138及/或第一半导体鳍状物116A与第二半导体鳍状物116B，以形成源极/漏极区(与前述形成轻掺杂源极/漏极区所用的工艺类似)，接着进行退火。源极/漏极区的杂质浓度可介于约1019cm-3至约1021cm-3之间。源极/漏极区所用的n型杂质可为前述的任何杂质。在一些实施例中，可在成长时原位掺杂外延的源极/漏极区138。
用于形成外延的源极/漏极区138于第一区100A及第二区100B中的外延工艺，造成外延的源极/漏极区138的晶面向外横向延伸超出第一半导体鳍状物116A与第二半导体鳍状物116B的侧壁。在一些实施例中，这些晶面造成相邻的源极/漏极区138合并，如图15C所示。在其他实施例中，完成外延工艺后的相邻的源极/漏极区138维持分开，如图15D所示。形成于第一半导体鳍状物116A或第二半导体鳍状物116B中的外延的源极/漏极区138可合并(如图15C所示)或分开(如图15D所示)。
在图16A与图16B中，沉积第一层间介电层140于图15A与图15B所示的结构上。第一层间介电层140的组成可为介电材料或半导体材料，且其沉积方法可为合适方法如化学气相沉积、等离子体增强化学气相沉积或可流动的化学气相沉积。介电材料可包含磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃、未掺杂的硅酸盐玻璃或类似物。半导体材料可包含非晶硅、硅锗(SixGe1-x，x可介于近似0至1之间)、纯锗或类似物。亦可采用任何可接受的工艺所形成的其他绝缘材料或半导体材料。在一些实施例中，接点蚀刻停止层(未图示)可位于外延的源极/漏极区138、遮罩133与栅极间隔物136以及第一层间介电层140之间。
在图17A与图17B中，可进行平坦化工艺如化学机械研磨，使第一层间介电层140的上表面与虚置栅极131的上表面齐平。平坦化工艺亦可移除虚置栅极131上的遮罩133，以及沿着遮罩133的侧壁的栅极间隔物136与栅极密封间隔物134的部分。在平坦化工艺之后，虚置栅极131、栅极密封间隔物134、栅极间隔物136、与第一层间介电层140的上表面齐平。综上所述，可由第一层间介电层140露出虚置栅极131的上表面。
在图18A与图18B中，以蚀刻步骤移除虚置栅极131与直接位于虚置栅极131下的虚置介电层128的一部分，即形成凹陷142。在一些实施例中，可由非等向干蚀刻工艺移除虚置栅极131。举例来说，蚀刻工艺可包含采用反应气体的干蚀刻工艺，其可选择性地蚀刻虚置栅极131而不蚀刻第一层间介电层140或栅极间隔物136。每一凹陷露出个别第一半导体鳍状物116A或第二半导体鳍状物116B的通道区。每一通道区位于相邻的一对外延的源极/漏极区138之间。在蚀刻虚置栅极131的移除步骤时，虚置介电层128可作为蚀刻停止层。可在移除虚置栅极131之后，接着移除虚置介电层128。
在图19A与图19B中，形成置换栅极所用的栅极介电层144与栅极146。栅极介电层144顺应性地沉积于凹陷142中，比如沉积在第一半导体鳍状物116A与第二半导体鳍状物116B的上表面与侧壁上，以及沉积在栅极密封间隔物134与栅极间隔物136的侧壁上。栅极介电层144亦可形成于第一层间介电层140的上表面上。在一些实施例中，栅极介电层144包含氧化硅、氮化硅或上述的多层。在一些实施例中，栅极介电层144为高介电常数的介电材料。在这些实施例中，栅极介电层144的介电常数可大于约7.0，其可包含铪、铝、锆、镧、镁、钡、钛、铅或上述的组合的金属氧化物或硅酸盐。栅极介电层144的形成方法可包含分子束沉积、原子层沉积、等离子体增强化学气相沉积或类似方法。
栅极146沉积于栅极介电层144上并填入凹陷142的其余部分。栅极146可为含金属材料如氮化钛、氮化钽、碳化钽、钴、钌、铝、上述的组合或上述的多层。栅极146可包含导电材料的一或多层，比如功函数层147与充填材料148。在填入栅极146之后可进行平坦化工艺，以移除栅极介电层144与栅极146位于第一层间介电层140的上表面上的多余部分。因此栅极146与栅极介电层144的保留部分形成最终鳍状场效晶体管的置换栅极。栅极146与栅极介电层144可一起称作栅极或栅极堆叠。栅极与栅极堆叠可沿着第一半导体鳍状物116A与第二半导体鳍状物116B的通道区侧壁延伸。
可同时形成栅极介电层144于第一区100A与第二区100B中，因此每一区中的栅极介电层144的材料组成相同。可同时形成栅极146，因此每一区中的栅极146的材料组成相同。在一些实施例中，可由不同工艺形成每一区中的栅极介电层144，因此每一区中的栅极介电层144可为不同材料；及/或可由不同工艺形成每一区中的栅极146，因此每一区中的栅极146可为不同材料。在采用不同工艺时，可采用多种遮罩步骤以遮罩并露出合适的区域。
如图19A与图19B所示，形成自对准接点149于每一栅极146上。在形成栅极146之后，可采用一或多道蚀刻工艺移除栅极146的部分(如功函数层147与充填材料148的顶部)。在一些实施例中，一或多道蚀刻工艺亦可移除栅极介电层144的顶部。一旦移除栅极146的顶部，即形成凹陷于栅极介电层144之间。接着形成自对准接点149于移除栅极146的顶部所形成的凹陷中。在后续形成开口的步骤时(设置以完成后续形成的接点，搭配图21A与图21B说明如下)，自对准接点149可保护栅极146。自对准接点149可包含或可为绝缘材料如氧化硅、氮化硅、氮氧化硅、氮碳氧化硅、碳氮化硅、任何合适的介电材料或上述的组合。在一些实施例中，自对准接点149为氮碳氧化硅。自对准接点的形成方法可为化学气相沉积、物理气相沉积、原子层沉积、任何合适的沉积技术或上述的组合，以及后续的平坦化方法如化学机械研磨。
在图20A与图20B中，沉积第二层间介电层150于第一层间介电层140上。在一实施例中，第二层间介电层150为可流动的化学气相沉积法所形成的可流动膜。在一些实施例中，第二层间介电层150的组成为介电材料如磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃、未掺杂的硅酸盐玻璃或类似物，且其沉积方法可为任何合适方法如化学气相沉积与等离子体增强化学气相沉积。
在图21A与图21B中，形成穿过第二层间介电层150与第一层间介电层140的栅极接点152与源极/漏极接点154。可形成源极/漏极接点154所用的开口(未图示)，其穿过第二层间介电层150与第一层间介电层140。可形成栅极接点152所用的开口(未图示)，其穿过第二层间介电层150。可采用可接受的光微影与蚀刻技术形成开口。在形成栅极接点152与源极/漏极接点154之前，可视情况形成硅化物接点(未图示)。硅化物接点可包含钛、镍、钴或铒，且可用于降低栅极接点152与源极/漏极接点154的肖特基能障高度。然而亦可采用其他金属如铂、钯或类似物。可毯覆性地沉积合适的金属层，接着进行退火使金属与其下方的露出硅反应，以进行硅化步骤。接着移除未反应的金属，且移除方法可为选择性蚀刻工艺。栅极接点152与源极/漏极接点154的组成可为导电材料如铝、铜、钨、钴、钛、钽、钌、氮化钛、钛铝、氮化钛铝、氮化钽、碳化钽、镍硅化物、钴硅化物、上述的组合或类似物，但亦可采用任何合适材料。可沉积栅极接点152与源极/漏极接点154的材料至第二层间介电层150与第一层间介电层140中的开口中以填入及/或超填开口，且沉积方法可为溅镀、化学气相沉积、电镀、无电镀或类似方法。一旦填入或超填开口，可采用平坦化工艺如化学机械研磨移除开口之外的任何沉积材料。
栅极接点152物理及电性地连接至栅极146，而源极/漏极接点154物理及电性地连接至外延的源极/漏极区138。图21A与图21B显示栅极接点152与源极/漏极接点154位于相同剖面，然而其他实施例的栅极接点152与源极/漏极接点154可位于不同剖面。此外，图21A与图21B中的栅极接点152与源极/漏极接点154的位置仅用于说明而非局限本发明实施例。举例来说，栅极接点152可垂直对准第一半导体鳍状物116A的一者如图所示，或者位于栅极146上的不同位置。此外，可在形成栅极接点152之前形成源极/漏极接点154、形成栅极接点152之后形成源极/漏极接点154或同时形成栅极接点152与源极/漏极接点154。
如上所述，第一半导体鳍状物116A中包含硅锗材料的第二外延层114，可提供低通道电阻、高效迁移率、改善的开启电流/关闭电流效能与改善的漏极诱发阻障负载的p型完全应变通道。此外，依据上述工艺形成盖层126可避免锗自第一半导体鳍状物116A向外扩散，进而减少疏离-密集负载效应、减少第一半导体鳍状物116A中形成的小翼状物、减少第一半导体鳍状物116A中的弯曲效应并减少第一半导体鳍状物116A的线路边缘粗糙度。如此一来，依据上述方法形成的半导体装置具有改良的效能。
在一实施例中，方法包括外延成长第一半导体层于n型井上；蚀刻第一半导体层以形成第一凹陷；外延成长第二半导体层以填入第一凹陷；蚀刻第二半导体层、第一半导体层与n型井以形成第一鳍状物；形成浅沟槽隔离区以与第一鳍状物相邻；以及形成盖层于第一鳍状物上，且盖层接触第二半导体层，其中形成盖层的步骤包括：进行预清洁工艺以自第二半导体层的露出表面移除原生氧化物；进行升华工艺以产生第一前驱物；以及进行沉积工艺，其中来自第一前驱物的材料沉积于第二半导体层上以形成盖层。在一实施例中，第一半导体层包括硅，第二半导体层包括硅锗，而盖层包括硅。在一实施例中，采用氢氟酸或氨原位进行预清洁工艺。在一实施例中，升华工艺的温度介于50℃至300℃之间。在一实施例中，第一前驱物包括硅烷、乙硅烷或二氯硅烷。在一实施例中，沉积工艺的温度介于200℃至450℃之间。在一实施例中，沉积工艺时在第一鳍状物上流动的氢气流速介于0.2slm至5slm之间。
在另一实施例中，方法包括形成n型井与p型井于基板上；形成第一半导体层于n型井与p型井上，且第一半导体层包括第一半导体材料；蚀刻第一半导体层以形成第一凹陷于n型井上；形成第二半导体层于第一凹陷中，且第二半导体层包括第二半导体材料；蚀刻第一半导体层与第二半导体层以形成第一鳍状物于n型井上，并形成第二鳍状物于p型井上，第一鳍状物包括第二半导体层，且第二鳍状物包括第一半导体层；以及形成盖层于第一鳍状物与第二鳍状物上，且盖层包括第三半导体材料，其中形成盖层的步骤包括：自第二半导体层移除原生氧化物；升华样品以产生前驱物气体；以及自前驱物气体沉积盖层于第一鳍状物与第二鳍状物上。在一实施例中，第一半导体材料具有第一晶格常数，第二半导体材料具有第二晶格常数，而第二晶格常数大于第一晶格常数，且第三半导体材料具有第三晶格常数，而第三晶格常数小于第二晶格常数。在一实施例中，方法还包括平坦化第一半导体层与第二半导体层，使第一半导体层的最顶侧表面与第二半导体层的最顶侧表面齐平。在一实施例中，蚀刻第一半导体层以形成第一凹陷之后，保留第一半导体层的至少一部分于n型井上，且第一鳍状物还包括第一半导体层。在一实施例中，方法还包括在形成盖层之前，先形成浅沟槽隔离区以与第一鳍状物及第二鳍状物相邻，其中盖层形成于第一鳍状物与第二鳍状物的露出部分上。在一实施例中，样品的升华温度介于50℃至300℃之间，且盖层的沉积温度介于200℃至400℃之间。
在又一实施例中，半导体装置包括第一半导体鳍状物，其包括：n型井；第一半导体层，位于n型井上；第二半导体层，位于第一半导体层上；盖层，位于第二半导体层的上表面与侧壁上并接触第二半导体层的上表面与侧壁，盖层包括多晶材料，第一半导体层与第二半导体层包括单晶材料；以及混合层，位于第二半导体层与盖层之间，混合层包括第二半导体层的材料与盖层的材料，且混合层的厚度介于
Figure BDA0002061216780000221
至
Figure BDA0002061216780000222
之间。在一实施例中，第一半导体层包括硅，其中第二半导体层包括硅锗，且其中盖层包括硅。在一实施例中，混合层的渐变锗浓度自盖层朝第二半导体层增加。在一实施例中，半导体装置还包括与第一半导体鳍状物相邻的浅沟槽隔离区，且浅沟槽隔离区接触n型井，其中盖层位于浅沟槽隔离区上。在一实施例中，盖层的厚度介于
Figure BDA0002061216780000223
至
Figure BDA0002061216780000224
之间。在一实施例中，半导体装置还包括第二半导体鳍状物，其包括：p型井；以及第三半导体层，位于p型井上，第三半导体层包括硅，其中第三半导体层的最顶侧表面与第二半导体层的最顶侧表面齐平，且其中第三半导体层的最下侧表面与第一半导体层的最下侧表面齐平。在一实施例中，盖层更接触n型井与第一半导体层的侧壁。
上述实施例的特征有利于本技术领域中技术人员理解本发明实施例。本技术领域中技术人员应理解可采用本发明实施例作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本公开构思与范围，并可在未脱离本公开的构思与范围的前提下进行改变、替换或变动。

Claims (1)

1.一种半导体装置的形成方法，包括：
外延成长一第一半导体层于一n型井上；
蚀刻该第一半导体层以形成一第一凹陷；
外延成长一第二半导体层以填入该第一凹陷；
蚀刻该第二半导体层、该第一半导体层与该n型井以形成一第一鳍状物；
形成一浅沟槽隔离区以与该第一鳍状物相邻；以及
形成一盖层于该第一鳍状物上，且该盖层接触该第二半导体层，其中形成该盖层的步骤包括：
进行一预清洁工艺以自该第二半导体层的露出表面移除原生氧化物；
进行一升华工艺以产生一第一前驱物；以及
进行一沉积工艺，其中来自该第一前驱物的材料沉积于该第二半导体层上以形成该盖层。
CN201910405924.2A 2018-07-31 2019-05-15 半导体装置的形成方法 Pending CN110783195A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862712504P 2018-07-31 2018-07-31
US62/712,504 2018-07-31
US16/276,143 2019-02-14
US16/276,143 US10679995B2 (en) 2018-07-31 2019-02-14 Semiconductor device and method

Publications (1)

Publication Number Publication Date
CN110783195A true CN110783195A (zh) 2020-02-11

Family

ID=69229009

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910405924.2A Pending CN110783195A (zh) 2018-07-31 2019-05-15 半导体装置的形成方法

Country Status (3)

Country Link
US (3) US10679995B2 (zh)
CN (1) CN110783195A (zh)
TW (1) TW202008433A (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10770563B2 (en) 2018-10-24 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and patterning method for multiple threshold voltages
US11854688B2 (en) 2020-02-19 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
DE102020115279B4 (de) 2020-02-19 2024-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zum ausbilden einer halbleitervorrichtung
US11430788B2 (en) * 2020-02-24 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit with latch-up immunity
US11695055B2 (en) 2020-03-03 2023-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation layers for semiconductor devices
KR20220150109A (ko) * 2021-05-03 2022-11-10 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
US20230019633A1 (en) * 2021-07-09 2023-01-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor method and device
US20230369134A1 (en) * 2022-05-10 2023-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101893848B1 (ko) * 2011-06-16 2018-10-04 삼성전자주식회사 수직 소자 및 비-수직 소자를 갖는 반도체 소자 및 그 형성 방법
US8815712B2 (en) 2011-12-28 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial re-growth of semiconductor region
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
US9093530B2 (en) 2012-12-28 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of FinFET
US9559181B2 (en) * 2013-11-26 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET device with buried sige oxide
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US8963258B2 (en) 2013-03-13 2015-02-24 Taiwan Semiconductor Manufacturing Company FinFET with bottom SiGe layer in source/drain
US9159834B2 (en) * 2013-03-14 2015-10-13 International Business Machines Corporation Faceted semiconductor nanowire
US8796666B1 (en) * 2013-04-26 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with strain buffer layer and methods of forming the same
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9548303B2 (en) 2014-03-13 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices with unique fin shape and the fabrication thereof
US9502538B2 (en) * 2014-06-12 2016-11-22 Taiwan Semiconductor Manufacturing Co., Ltd Structure and formation method of fin-like field effect transistor
CN107546108A (zh) * 2014-10-30 2018-01-05 应用材料公司 在低温下生长薄外延膜的方法
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US11018254B2 (en) * 2016-03-31 2021-05-25 International Business Machines Corporation Fabrication of vertical fin transistor with multiple threshold voltages
US10109507B2 (en) * 2016-06-01 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Fluorine contamination control in semiconductor manufacturing process

Also Published As

Publication number Publication date
TW202008433A (zh) 2020-02-16
US20200303378A1 (en) 2020-09-24
US20220302116A1 (en) 2022-09-22
US10679995B2 (en) 2020-06-09
US20200043927A1 (en) 2020-02-06
US11398482B2 (en) 2022-07-26

Similar Documents

Publication Publication Date Title
CN108122777B (zh) 鳍状场效晶体管的形成方法
CN110783195A (zh) 半导体装置的形成方法
US11854901B2 (en) Semiconductor method and device
CN109216195B (zh) 鳍状场效晶体管装置及其形成方法
CN110838488A (zh) 半导体装置与其形成方法
CN110610863B (zh) 半导体装置与其形成方法
CN111223936A (zh) 半导体装置与其形成方法
US11728223B2 (en) Semiconductor device and methods of manufacture
US20240363349A1 (en) Semiconductor device and method of manufacture
US11735664B2 (en) Source/drain regions of FINFET devices and methods of forming same
US20230317831A1 (en) Growth Process And Methods Thereof
CN218498075U (zh) 半导体装置
US11901218B2 (en) Shallow trench isolation forming method and structures resulting therefrom
US11710777B2 (en) Semiconductor device and method for manufacture
US11757020B2 (en) Semiconductor device and method
TWI844225B (zh) 半導體元件形成的方法
CN115513138A (zh) 半导体装置及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20200211