CN110970064A - 存储器单元和用于控制存储器单元的方法 - Google Patents

存储器单元和用于控制存储器单元的方法 Download PDF

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CN110970064A
CN110970064A CN201910934370.5A CN201910934370A CN110970064A CN 110970064 A CN110970064 A CN 110970064A CN 201910934370 A CN201910934370 A CN 201910934370A CN 110970064 A CN110970064 A CN 110970064A
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charge storage
storage transistor
memory cell
substrate
bit line
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杜源
蒋明哲
苏俊杰
刘峻诚
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Kneron Inc
Kneron Taiwan Co Ltd
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Abstract

本发明提供一种存储器单元和用于控制存储器单元的方法。该存储器单元包括第一电荷存储式晶体管及第二电荷存储式晶体管。第一电荷存储式晶体管包括基板，第一端耦接至第一位线，第二端耦接至信号线，控制端耦接至字线，及介电层形成在第一电荷存储式晶体管的基板及第一电荷存储式晶体管的控制端之间。第二电荷存储式晶体管包括基板，第一端耦接至信号线，第二端耦接至第二位线，控制端耦接至该字线，及介电层形成在第二电荷存储式晶体管的基板及第二电荷存储式晶体管的控制端之间。本发明可在应用上有效的缩小集成电路尺寸，并可应用在需更低功耗的集成电路芯片上。

Description

存储器单元和用于控制存储器单元的方法
技术领域
本发明是关于一种存储器单元，尤指一种存储器单元和用于控制存储器单元的方法。
背景技术
静态随机存取存储器(SRAM)是作为芯片上的闪存。传统的SRAM单元通常包括六个晶体管。导致尺寸和功耗无法降低。随着电子设备的进步，需要更低功耗且尺寸更小的集成电路芯片以满足需求。因此，需要开发其他种类的存储器。
在闪存的设备中应用电荷存储式晶体管(charge trap transistor)已是已知的技术。然而，此晶体管不适用于高性能逻辑电路或低成本的技术，因为可能需要额外的光掩膜，更多的工艺复杂性或工作电压不相容的问题。另一方面，在近期，以22nm金属氧化物半导体场效应晶体管(MOSFET)和14nm鳍式场效应晶体管(FinFET)技术制造的电荷存储式晶体管已被开发出来，而该晶体管的应用实质上不会增加工艺复杂性或需要额外光掩膜。因此，电荷存储式晶体管有机会被应用在SRAM等高性能存储器。
发明内容
本发明实施例公开了一种存储器单元，包括第一电荷存储式晶体管及第二电荷存储式晶体管(charge trap transistor)。第一电荷存储式晶体管包括基板，第一端形成在该基板上并耦接至第一位线，第二端形成在基板上并耦接至信号线，控制端耦接至字线及介电层形成在第一电荷存储式晶体管的基板及第一电荷存储式晶体管的控制端之间。第二电荷存储式晶体管包括基板，第一端，形成在该基板上并耦接至信号线，第二端形成在该基板上并耦接至第二位线，控制端耦接至该字线及介电层形成在第二电荷存储式晶体管的基板及第二电荷存储式晶体管的控制端之间。
另一个实施例公开了一种用于控制存储器单元的方法。该方法包括将电荷存储至第一电荷存储式晶体管的介电层或从第一电荷存储式晶体管的介电层释放电荷以改变第一电荷存储式晶体管的阈值电压，并将第一位线的电压与第二位线的电压进行比较以判断在存储器单元中所存储的数据。
本发明可在应用上有效的缩小集成电路尺寸，并可应用在需更低功耗的集成电路芯片上。
附图说明
图1是实施例中存储器单元的示意图。
图2是图1存储器单元的第一电荷存储式晶体管的结构示意图。
图3是图1存储器单元的第二电荷存储式晶体管的结构示意图。
图4是在存储电荷时，施加到第一电荷存储式晶体管的控制端的正电压脉冲的示意图。
图5是在释放电荷时，施加到第一电荷存储式晶体管的控制端的负电压脉冲的示意图。
图6是在存储电荷时，第一电荷存储式晶体管的控制端的栅极电压与对应的漏极电流的示意图。
图7是在释放电荷时，第一电荷存储式晶体管的控制端的栅极电压与对应的漏极电流的示意图。
图8是用于控制图1存储器单元的方法的流程图。
图9是用于控制图1存储器单元的另一方法的流程图。
附图标号
100 存储器单元
110、120 电荷存储式晶体管
112、122 基板
113、123 源极端
114、124 漏极端
115、125 栅极端
116、126 介电层
BL、BLB 位线
SL 信号线
WL 字线
VT1 第一阈值电压
VDD 系统电压
VG 栅极电压
ID 漏极电流
S800至S820、S900至S920 步骤
具体实施方式
图1是实施例中存储器单元100的示意图。存储器单元100包括第一电荷存储式晶体管110和第二电荷存储式晶体管120。图2是图1中第一电荷存储式晶体管110的结构示意图。第一电荷存储式晶体管110具有P型基板112、第一端113、第二端114、控制端115及介电层116。第一端113是N型源极端，形成在基板112上并且耦接至第一位线BL；第二端114是N型漏极端，形成在基板112上并且耦接至信号线SL；控制端115是栅极端，包括具有高κ材料的介电层116，例如HfO2或HfSiOx，并耦接至字线WL。图3是图1中第二电荷存储式晶体管120的结构示意图。第二电荷存储式晶体管120具有P型基板122、第一端123、第二端124、控制端125及介电层126。第一端123是N型源极端，形成在基板122上并且耦接信号线SL；第二端124是N型漏极端，形成在基板122上并且耦接至第二位线BLB；控制端125是栅极端，包括具有高κ材料的介电层126，例如HfO2或HfSiOx，并耦接至字线WL。第一电荷存储式晶体管110具有第一阈值电压，第二电荷存储式晶体管120具有第二阈值电压。
图4是在存储电荷时，施加到第一电荷存储式晶体管110的控制端115的正电压脉冲的示意图。图5是在释放电荷时，施加到第一电荷存储式晶体管110的控制端115的负电压脉冲的示意图。图4及图5的电压脉冲是用在第一电荷存储式晶体管110上进行电荷存储和释放的操作。第一阈值电压由高κ栅极中所存储的电荷量所控制。通过在控制端115上施加正电压脉冲，例如2V脉冲(如图4所示)，电荷可被存储到介电层116，而通过在第一电荷存储式晶体管110的控制端115上施加负电压脉冲，例如-1V脉冲(如图5所示)，电荷可从第一电荷存储式晶体管110的介电层116被释放。
图6是在存储电荷时，第一电荷存储式晶体管110的控制端的栅极电压VG与对应的漏极电流ID(从第二端到第一端)的示意图。图7是在释放电荷时，第一电荷存储式晶体管110的控制端的栅极电压VG与漏极电流ID(从第二端到第一端)示意图。如图所示，存储电荷至栅极会提升第一阈值电压VT1，而由栅极释放电荷则会降低第一阈值电压VT1。
以下描述存储器单元100的操作方法。存储器单元100可通过将电荷存储到第一电荷存储式晶体管110的介电层116来写入数据位。举例而言，通过2V电压脉冲导通字线WL并且在提高信号线SL及第二位线BLB的电压至1.5V的同时对第一位线BL放电使其电压降至0V，此时电流仅流至第一电荷存储式晶体管110，使电荷被存储到第一电荷存储式晶体管110的介电层116而导致第一阈值电压VT1提升。当第一阈值电压VT1提升至高于第二阈值电压时，数据位即判断为1。
存储器单元100另可通过从第一电荷存储式晶体管110的介电层116释放电荷来写入数据位。举例而言，通过用-1V电压脉冲开启字线WL并将第一位线BL设置为浮接同时提升信号线SL和第二位线BLB的电压至2V，使电荷从第一电荷存储式晶体管110的介电层116被释放而导致第一阈值电压VT1下降。当第一阈值电压VT1下降至低于第二阈值时电压，数据位即判断为0。
在读取操作期间，字线WL及信号线SL被充电到系统电压VDD，并对第一位线BL和第二位线BLB放电，使位线BL和BLB的产生差分电压(differential voltage)。差分电压是由第一电荷存储式晶体管110和第二电荷存储式晶体管120中存储的电荷差所导致，而存储在存储器单元100中的数据是通过比较第一位线BL和第二位线BLB的差分电压来判断。当存储器单元100所存储的数据位为0，第一位线BL的电压低于第二位线BLB的电压。当存储器单元100所存储的数据位为1，第一位线BL的电压高于第二位线BLB的电压。
图8是用于控制存储器单元100的方法的流程图。该方法可以包括以下步骤：
S800：在存储电荷操作期间，对第一位线BL放电，并对第二位线BLB和信号线SL充电；
S810：通过向第一电荷存储式晶体管110的控制端施加正电压脉冲，电荷会被存储到第一电荷存储式晶体管110的介电层116，使第一阈值电压VT1提升；
S820：将第一位线BL的电压与第二位线BLB的电压进行比较，以判断存储在存储器单元100中的数据。
图9是用于控制存储器单元100的另一方法的流程图。该方法可以包括以下步骤：
S900：在释放电荷操作期间，将第一位线BL设置为浮接并对信号线SL和第二位线BLB充电；
S910：通过向第一电荷存储式晶体管110的控制端施加负电压脉冲，第一电荷存储式晶体管110的介电层116会释放电荷，使第一阈值电压VT1降低；
S920：将第一位线BL的电压与第二位线BLB的电压进行比较，以判断存储在存储器单元100中的数据。
综上所述，本发明公开的实施例利用电荷存储式晶体管所设计的存储器具有以低功耗和较低的复杂性实现高性能存储器的优点。本发明所述的存储器单元及其操作方式可在应用上有效的缩小集成电路尺寸，并可应用在需更低功耗的集成电路芯片上。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种存储器单元，其特征在于，包括：
一第一电荷存储式晶体管，包括：
一基板；
一第一端，形成在该基板上并耦接至一第一位线；
一第二端，形成在该基板上并耦接至一信号线；
一控制端，耦接至一字线；及
一介电层，形成在该第一电荷存储式晶体管的该基板及该第一电荷存储式晶体管的该控制端之间；及
一第二电荷存储式晶体管，包括：
一基板；
一第一端，形成在该基板上并耦接至一信号线；
一第二端，形成在该基板上并耦接至一第二位线；
一控制端，耦接至该字线；及
一介电层，形成在该第二电荷存储式晶体管的该基板及该第二电荷存储式晶体管的该控制端之间；
其中，当要将一第一逻辑值存储在该存储器单元时，电荷会被存储到该第一电荷存储式晶体管的该介电层，并且当要将一第二逻辑值存储在该存储器单元时，电荷会从该第一电荷存储式晶体管的该介电层被释放。
2.如权利要求1所述的存储器单元，其特征在于，当电荷被存储到该第一电荷存储式晶体管的该介电层时，该第一电荷存储式晶体管的一阈值电压会提升。
3.如权利要求1所述的存储器单元，其特征在于，当从该第一电荷存储式晶体管的该介电层释放电荷时，该第一电荷存储式晶体管的一阈值电压会降低。
4.如权利要求2或3所述的存储器单元，其特征在于，将该第一位线的电压与该第二位线的电压进行比较以判断存储在该存储器单元中的数据。
5.如权利要求1所述的存储器单元，其特征在于，该第一电荷存储式晶体管及该第二电荷存储式晶体管是N型金属氧化物半导体场效应晶体管。
6.如权利要求1所述的存储器单元，其特征在于，该第一电荷存储式晶体管及该第二电荷存储式晶体管是N型鳍式场效应晶体管。
7.一种用于控制存储器单元的方法，其特征在于，该存储器单元包括一第一电荷存储式晶体管及一第二电荷存储式晶体管，该第一电荷存储式晶体管包括一基板，一第一端耦接至一第一位线，一第二端耦接至一信号线，一控制端耦接至一字线，一介电层位于该第一电荷存储式晶体管的该基板与该第一电荷存储式晶体管的该控制端之间，一第二电荷存储式晶体管包括一基板，一第一端耦接至该信号线，一第二端耦接至一第二位线，一控制端耦接至该字线，以及一介电层位于该第二电荷存储式晶体管的该基板与该第二电荷存储式晶体管的该控制端之间，该方法包括：
将电荷存储到该第一电荷存储式晶体管的该介电层以提升该第一电荷存储式晶体管的一阈值电压；及
比较该第一位线的一电压和该第二位线的一电压，以判断存储在该存储器单元中的数据。
8.如权利要求7所述的方法，其特征在于，将电荷存储到该第一电荷存储式晶体管的该介电层以增加该第一电荷存储式晶体管的该阈值电压，包括：
对该第一位线放电；
对该第二位线及该信号线充电；及
对该第一电荷存储式晶体管的该控制端施加正电压脉冲。
9.一种用于控制存储器单元的方法，其特征在于，该存储器单元包括一第一电荷存储式晶体管及一第二电荷存储式晶体管，该第一电荷存储式晶体管包括一基板，一第一端耦接至一第一位线，一第二端耦接至一信号线，一控制端耦接至一字线，一介电层位于该第一电荷存储式晶体管的该基板与该第一电荷存储式晶体管的该控制端之间，一第二电荷存储式晶体管包括一基板，一第一端耦接至该信号线，一第二端耦接至一第二位线，一控制端耦接至该字线，以及一介电层位于该第二电荷存储式晶体管的该基板与该第二电荷存储式晶体管的该控制端之间，该方法包括：
将电荷从该第一电荷存储式晶体管的该介电层释放以降低该第一电荷存储式晶体管的一阈值电压；及
比较该第一位线的一电压和该第二位线的一电压，以判断存储在该存储器单元中的数据。
10.如权利要求9所述的方法，其特征在于，将电荷从该第一电荷存储式晶体管的该介电层释放以降低该第一电荷存储式晶体管的该阈值电压，包括：
浮接该第一位线；
对该第二位线及该信号线充电；及
对该第一电荷存储式晶体管的该控制端施加负电压脉冲。
CN201910934370.5A 2018-09-28 2019-09-29 存储器单元和用于控制存储器单元的方法 Pending CN110970064A (zh)

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