CN110912763A - CAN bus test integrated circuit, test system and test method - Google Patents

CAN bus test integrated circuit, test system and test method Download PDF

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Publication number
CN110912763A
CN110912763A CN201811083206.XA CN201811083206A CN110912763A CN 110912763 A CN110912763 A CN 110912763A CN 201811083206 A CN201811083206 A CN 201811083206A CN 110912763 A CN110912763 A CN 110912763A
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China
Prior art keywords
test
resistor
bus
data line
circuit
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Inventor
刘崇俊
谭天洪
潘文
姚伟
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United Automotive Electronic Systems Co Ltd
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United Automotive Electronic Systems Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40078—Bus configuration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN

Abstract

The invention provides a CAN bus test integrated circuit, a test system and a test method, wherein the CAN bus test integrated circuit divides a test circuit into an output voltage test circuit, an input resistance test circuit and an input capacitance test circuit, and the three test circuits CAN independently perform test work, so that the requirements for measuring different parameters of a CAN bus are met, and the interference among the circuits is reduced. In addition, because the CAN bus test integrated circuit relates to a switch for selecting one from multiple paths, the access circuit CAN be switched according to the test standard requirement and the customer requirement. Therefore, the test circuit for evaluating the signal quality of the CAN bus CAN avoid the problem that a test circuit needs to be designed aiming at each standard or requirement in the prior art, has the characteristics of convenient use, high integration level and wide applicability, and improves the test reliability and the test efficiency.

Description

CAN bus test integrated circuit, test system and test method
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a CAN bus test integrated circuit, a test system and a test method.
Background
The CAN bus is widely applied to the automobile industry, and along with the continuous progress of the technology, the speed of the CAN bus is further improved, so that the application field of the CAN bus is wider. Meanwhile, the performance requirements on the CAN bus such as control, function, communication speed and the like are continuously improved. Therefore, the CAN bus takes a significant amount of time for the developer to test and verify. What is more important is that each test needs to be performed separately for different rates and different terminal configurations in the physical layer of the CAN bus. During testing, the test parameters need to be read by high-precision instrument equipment and brought into a corresponding acceptance standard formula, and the obtained data is calculated to determine whether the requirements of corresponding customers are met. In the test process, engineers need to spend a lot of time making circuits with different configurations to meet the standard test requirements, the configuration circuits are generally connected with resistors, capacitors or diodes by using conducting wires, and the other end of the configuration circuits is an interface capable of being connected to a CAN line. The method for connecting devices in the configuration circuit by using wires has the following defects: the device is easy to bear, and the connection part of the device and the lead is easy to fall off; too many wires are not easy to mark, and great deviation and even errors are easily caused to the test result.
Aiming at the problems existing in the CAN bus test in the prior art, the technical personnel in the field are always seeking a solution.
Disclosure of Invention
The invention aims to provide a CAN bus test integrated circuit, a test system and a test method, which are used for solving the problems of CAN bus test in the prior art.
In order to solve the above technical problem, the present invention provides a CAN bus test integrated circuit, which includes: the output voltage test circuit is used for testing the output voltage parameters of the CAN bus, and the output voltage parameters comprise: the voltage of the upper data line, the voltage of the lower data line, and the differential voltage.
Optionally, in the CAN bus test integrated circuit, the output voltage test circuit includes: the circuit comprises a first branch, a second branch, a third branch and a fourth branch which are sequentially connected in parallel, wherein a first single-pole double-throw switch interface (CANH) and a low-bit data line interface (CANL) are formed at two ends of the first branch, and a first output interface (M1) and a second output interface (M2) are formed at two ends of the fourth branch;
wherein the first branch comprises: the circuit comprises a first resistor (R1), a second resistor (R2), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first toggle switch (S1) and a first single-pole-three-throw switch (S5), wherein the first toggle switch (S1), the first resistor (R1) and the second resistor (R2) are sequentially connected in series; the fixed end of the first single-pole-three-throw switch (S5) is connected with a connecting line between the first resistor (R1) and the second resistor (R2), the movable end of the first single-pole-three-throw switch (S5) is selectively connected with one end of the first capacitor (C1), one end of the second capacitor (C2) or one end of the third capacitor (C3), and the first capacitor (C1), the second capacitor (C2) and the third capacitor (C3) are grounded after being connected in parallel;
the second branch circuit includes: the circuit comprises a third resistor (R3), a fourth resistor (R4), a fourth capacitor (C4), a fifth capacitor (C5), a sixth capacitor (C6), a second toggle switch (S2) and a second single-pole-three-throw switch (S6), wherein the second toggle switch (S2), the third resistor (R3) and the fourth resistor (R4) are sequentially connected in series; the fixed end of the second single-pole-three-throw switch (S6) is connected with a connecting line between the third resistor (R3) and the fourth resistor (R4), the movable end of the second single-pole-three-throw switch (S6) is selectively connected with one end of the fourth capacitor (C4), one end of the fifth capacitor (C5) or one end of the sixth capacitor (C6), and the fourth capacitor (C4), the fifth capacitor (C5) and the sixth capacitor (C6) are grounded after being connected in parallel;
the third branch includes: a fifth resistor (R5) and a third toggle switch (S3), wherein one end of the third toggle switch (S3) is connected with the second toggle switch (S2), the other end of the third toggle switch (S3) is connected with the fifth resistor (R5) in series, and the other end of the fifth resistor (R5) is connected with one end, far away from the third resistor (R3), of the fourth resistor (R4) in the second branch;
the fourth branch includes: the circuit comprises a sixth resistor (R6) and a fourth toggle switch (S4), one end of the fourth toggle switch (S4) is connected with the second toggle switch (S2), the other end of the fourth toggle switch (S4) is connected with the sixth resistor (R6) in series, and the other end of the sixth resistor (R6) is connected with one end, far away from the third resistor (R3), of the fourth resistor (R4) in the second branch.
Optionally, the CAN bus test integrated circuit further includes an input resistance test circuit, configured to obtain input resistance parameters of the CAN bus, where the input resistance parameters include: the input resistance of the high-order data line, the input resistance of the low-order data line and the differential resistance;
the input resistance test circuit includes: the switch comprises a fifth toggle switch (S7), a sixth toggle switch (S8), a first single-pole double-throw switch (S9), a single-pole six-throw switch (S10), a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11) and a twelfth resistor (R12), wherein a third output interface (M3) is formed at the fixed end of the first single-pole double-throw switch (S9);
the sixth resistor (R7), the eighth resistor (R8), the ninth resistor (R9), the tenth resistor (R10), the eleventh resistor (R11) and the twelfth resistor (R12) are connected in parallel and then connected with one end of the sixth toggle switch (S8), and the other end of the sixth toggle switch (S8) forms a low-bit data line interface (CANL); one end of the fifth toggle switch (S7) is connected with one end of the sixth toggle switch (S8), and the other end of the fifth toggle switch (S7) is formed with a high data line interface (CANH); the moving end of the first single-pole double-throw switch (S9) is selectively connected with the fifth toggle switch (S7) or the sixth toggle switch (S8); a power interface (U) is formed at the fixed end of the single-pole six-throw switch (S10), and the movable end of the single-pole six-throw switch (S10) is selectively connected with a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11) or a twelfth resistor (R12).
Optionally, in the CAN bus test integrated circuit, the process of obtaining the input resistance parameter of the CAN bus by the input resistance test circuit includes two cases of testing a terminal-free state and a terminal-containing state.
Optionally, in the CAN bus test integrated circuit, when the input resistance test circuit does not include a terminal in the test, the input resistance parameter of the CAN bus is obtained by using the following calculation formula:
Figure BDA0001802497880000031
Figure BDA0001802497880000032
Figure BDA0001802497880000033
wherein R isin_CAN_HInput resistance, R, for the upper data linein_CAN_LInput resistance, R, for the lower data linediffIs a differential resistance, RtestIs a test resistance selected according to standard requirements; vCAN_H，VCAN_LRespectively the output voltages of the high-bit data line and the low-bit data line in a recessive state obtained by the output voltage test circuit, if the output voltage is not measured, V is enabledCAN_H＝VCAN_L2.5v, U is the voltage of the power supply; v2 and V1 are actual measured voltages of the upper data line and the lower data line respectively; the conditions are satisfied:
6kΩ≤Rin_CAN_H≤50kΩ，6kΩ≤Rin_CAN_L≤50kΩ，ΔRin_CAN≤3％。
optionally, in the CAN bus test integrated circuit, when the input resistance test circuit tests a terminal, the input resistance parameter of the CAN bus is obtained by using the following calculation formula:
Rin_CAN_H＝Rin_CAN_L＝Rin(4)
Figure BDA0001802497880000041
wherein R isin_CAN_HInput resistance, R, for the upper data linein_CAN_LInput resistance, R, for the lower data lineinIs an input resistance, RtestIs a test resistance selected according to standard requirements; vCANThe output voltage of the recessive state obtained by the output voltage test circuit is not measuredThen order VCAN2.5V; u is the voltage of the power supply; v is the actual measured voltage; the conditions are satisfied: r is less than or equal to 6k omegain≤50kΩ。
Optionally, the CAN bus test integrated circuit further includes an input capacitance test circuit, configured to obtain an input capacitance parameter of the CAN bus, where the input capacitance parameter includes: an input capacitance and a differential capacitance;
the input capacitance test circuit includes: the circuit comprises a seventh toggle switch (S11), a second single-pole double-throw switch (S12), a thirteenth resistor (R13) and a diode (D1), wherein a high-order data line interface (CANH) and a fourth output interface (M4) are formed at one end of the seventh toggle switch (S11); a low data line interface (CANL) is formed at the fixed end of the second single-pole double-throw switch (S12), and the movable end of the second single-pole double-throw switch (S12) is selectively connected with the cathode of the diode (D1) or the Ground (GND); one end of the thirteenth resistor (R13) is connected with the cathode of the diode (D1), the other end of the thirteenth resistor (R13) is Grounded (GND), and a power interface (U) is formed at the anode of the diode (D1).
Optionally, in the CAN bus test integrated circuit, the input capacitance test circuit obtains the input capacitance parameter of the CAN bus by using the following calculation formula:
Figure BDA0001802497880000042
Figure BDA0001802497880000043
wherein, the discharge time constant τ is 0.721 ═ t2-t1, t2 is the time taken for the high data line level to drop to 0.2 ×, t1 is the time taken for the high data line level to drop to 0.8 ×; cinIs an input capacitance, CdiffIs a differential capacitance, tau1Calculated discharge time constant, tau, for measuring input capacitance2A discharge time constant calculated for measuring the differential capacitance; satisfies the conditions
40pF≤Cin≤140pF，0pF≤Cdiff≤50pF。
The invention also provides a CAN bus test system which comprises the CAN bus test integrated circuit and test equipment connected with the CAN bus test integrated circuit.
Optionally, in the CAN bus test system, the test device is an oscilloscope.
The invention also provides a CAN bus test method, which is based on the CAN bus test system to carry out CAN bus test and comprises the following steps:
connecting a high-bit data line interface and a low-bit data line interface in a corresponding test circuit in the CAN bus test system with a high-bit data line and a low-bit data line of a tested sample respectively according to the test requirement of the CAN bus; wherein the test circuit comprises: an output voltage test circuit, an input resistance test circuit or an input capacitance test circuit; the test requirements comprise requirements for testing output voltage parameters, input resistance parameters or input capacitance parameters of the CAN bus;
and connecting the output interface in the corresponding test circuit with the test equipment according to the test requirement of the CAN bus.
Optionally, in the CAN bus test method, the voltages of the power supplies are selected to be-2 v and 7v in the test process of the CAN bus test system.
In the CAN bus test integrated circuit, the test system and the test method provided by the invention, the test circuit of the CAN bus test integrated circuit is divided into an output voltage test circuit, an input resistance test circuit and an input capacitance test circuit, and the three test circuits CAN independently perform test work, so that the requirements for measuring different parameters of the CAN bus are met, and the interference among the circuits is reduced. In addition, because the CAN bus test integrated circuit relates to a switch for selecting one from multiple paths, the access circuit CAN be switched according to the test standard requirement and the customer requirement. Therefore, the test circuit for evaluating the signal quality of the CAN bus CAN avoid the problem that a test circuit needs to be designed aiming at each standard or requirement in the prior art, has the characteristics of convenient use, high integration level and wide applicability, and improves the test reliability and the test efficiency.
Drawings
FIG. 1 is a circuit diagram of an output voltage test circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of an input resistance test circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of an input capacitance test circuit according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a CAN bus test system according to an embodiment of the present invention;
fig. 5 is a flowchart of a CAN bus test method according to an embodiment of the invention.
The reference numbers in the figures illustrate:
r1 — first resistance; r2 — second resistance; r3 — third resistance; r4-fourth resistor; r5-fifth resistor; r6-sixth resistance; r7 — seventh resistor; r8 — eighth resistance; r9 — ninth resistor; r10 — tenth resistance; r11 — eleventh resistor; r12 — twelfth resistor; r13 — thirteenth resistor;
c1 — first capacitance; c2 — second capacitance; c3 — third capacitance; c4-fourth capacitance; c5 — fifth capacitance; c6 — sixth capacitance;
s1-a first toggle switch; s2-a second toggle switch; s3-a third toggle switch; s4-a fourth toggle switch; s5-first single pole, triple throw switch; s6-a second single-pole-three-throw switch; s7-a fifth toggle switch; s8-sixth toggle switch; s9 — a first single pole double throw switch; s10-single pole six throw switch; s11-seventh toggle switch; s12 — a second single pole double throw switch;
d1-diode; CANH-high data line interface; m1 — first output interface; m2 — second output interface; m3-third output interface; m4-fourth output interface; GND-ground; a U-power interface; a. b, c, d, e-connection endpoints.
Detailed Description
The present invention provides a CAN bus test integrated circuit, a test system and a test method, which are further described in detail with reference to the accompanying drawings and the specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Certain terms are used throughout the description and claims to refer to particular system components. As one skilled in the art will appreciate, different companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …".
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
Furthermore, each of the embodiments described below has one or more technical features, and thus, the use of the technical features of any one embodiment does not necessarily mean that all of the technical features of any one embodiment are implemented at the same time or that only some or all of the technical features of different embodiments are implemented separately. In other words, those skilled in the art can selectively implement some or all of the features of any embodiment or combinations of some or all of the features of multiple embodiments according to the disclosure of the present invention and according to design specifications or implementation requirements, thereby increasing the flexibility in implementing the invention.
The present invention will be described in more detail with reference to the accompanying drawings, in order to make the objects and features of the present invention more comprehensible, embodiments thereof will be described in detail below, but the present invention may be implemented in various forms and should not be construed as being limited to the embodiments described.
Example one
Referring to fig. 1, fig. 2 and fig. 3, fig. 1 is a circuit diagram of an output voltage test circuit according to an embodiment of the invention; FIG. 2 is a circuit diagram of an input resistance test circuit according to an embodiment of the present invention; FIG. 3 is a circuit diagram of an input capacitance test circuit according to an embodiment of the invention. As shown in fig. 1, the CAN bus test integrated circuit includes: the output voltage test circuit is used for testing the output voltage parameters of the CAN bus, and the output voltage parameters comprise: the voltage of the upper data line, the voltage of the lower data line, and the differential voltage. Specifically, the output voltage test circuit includes: the circuit comprises a first branch, a second branch, a third branch and a fourth branch which are sequentially connected in parallel, wherein a first single-pole double-throw switch interface CANH and a low-bit data line interface CANL are formed at two ends of the first branch, and a first output interface M1 and a second output interface M2 are formed at two ends of the fourth branch;
wherein the first branch comprises: the circuit comprises a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first toggle switch S1 and a first single-pole-three-throw switch S5, wherein the first toggle switch S1, the first resistor R1 and the second resistor R2 are sequentially connected in series; the fixed end of the first single-pole-three-throw switch S5 is connected to a connection line between the first resistor R1 and the second resistor R2, the movable end of the first single-pole-three-throw switch S5 is selectively connected to one end of the first capacitor C1, the second capacitor C2 or the third capacitor C3, and the first capacitor C1, the second capacitor C2 and the third capacitor C3 are grounded after being connected in parallel; the second branch circuit includes: a third resistor R3, a fourth resistor R4, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a second toggle switch S2 and a second single-pole-three-throw switch S6, wherein the second toggle switch S2, the third resistor R3 and the fourth resistor R4 are sequentially connected in series; a fixed end of the second single-pole-three-throw switch S6 is connected to a connection line between the third resistor R3 and the fourth resistor R4, a moving end of the second single-pole-three-throw switch S6 is selectively connected to one end of the fourth capacitor C4, one end of the fifth capacitor C5 or one end of the sixth capacitor C6, and the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6 are grounded after being connected in parallel; the third branch includes: a fifth resistor R5 and a third toggle switch S3, one end of the third toggle switch S3 is connected with the second toggle switch S2, the other end of the third toggle switch S3 is connected with the fifth resistor R5 in series, and the other end of the fifth resistor R5 is connected with one end, far away from the third resistor R3, of the fourth resistor R4 in the second branch; the fourth branch includes: the circuit comprises a sixth resistor R6 and a fourth toggle switch S4, one end of the fourth toggle switch S4 is connected with the second toggle switch S2, the other end of the fourth toggle switch S4 is connected with the sixth resistor R6 in series, and the other end of the sixth resistor R6 is connected with one end, far away from the third resistor R3, of the fourth resistor R4 in the second branch.
When the CAN bus output voltage is tested, recessive and dominant levels need to be tested. The CAN node termination resistances of the samples to be measured are classified into four categories, which are specifically shown in table 1. The measurement process is as follows: firstly, the type of the terminal resistance of the CAN node of the tested sample is determined, then the states of the toggle switches S1, S2, S3 and S4 in the CAN bus test integrated circuit shown in the table 1 are determined according to the states shown in the table 1, and the states of the rest switches (namely, the switches S5 to S10 in the CAN bus test integrated circuit shown in the table 1 and the table 2) are determined according to the requirements of customers. It should be noted that, when performing the recessive level test, the test is performed only according to the case 1 shown in table 1; when the dominant level test is performed, it is necessary to perform the test in case 1 shown in table 1 and case 2 shown in table 2 at the same time.
Table 1: output Voltage test case 1
Figure BDA0001802497880000081
Table 2: output Voltage test case 2
Figure BDA0001802497880000091
The parameters of the elements in the output voltage test circuit are as follows: the first resistor R1 to the second resistor R6 are all testing resistors and can be selected according to the terminal resistance of the tested sample; the capacitance values of the first capacitor C1 and the fourth capacitor C4 are both 4.7 nF; the capacitance values of the second capacitor C2 and the fifth capacitor C5 are both 47 nF; the capacitance values of the third capacitor C3 and the sixth capacitor C6 are both 100 nF.
In the measuring process, the first single-pole three-throw switch S5 and the second single-pole three-throw switch S6 can be selectively connected with corresponding capacitors according to different standards; a high-bit data line interface CANH and a low-bit data line interface CANL of the output voltage test circuit are respectively connected with a high-bit data line CAN _ H and a low-bit data line CAN _ L of the tested sample; the first output interface M1 and the second output interface M2 are respectively connected to two input channels of a testing device (such as an oscilloscope), and then the output voltage test can be performed after the power is turned on. The parameters to be measured in the test are as follows: high bit line voltage VCAN_HVoltage V of low-bit data lineCAN_LDifferential voltage VdiffAnd the voltage of the upper data line and the voltage of the lower data line are summedCAN_H+VCAN_L) Four quantities, the recessive level test only needs to be performed according to Table 1, and the dominant level test also needs to be performed according to condition 2 shown in Table 2diffThe judgment after the test is as follows:
the test judgment basis of the output voltage in the recessive state is as follows:
2V≤VCAN_H≤3V；
2V≤VCAN_L≤3V；
-500mV≤Vdiff≤50mV；
2V≤VCM＝0.5*(VCAN_H+VCAN_L)≤3V
the dominant state output voltage test judgment basis is as follows:
2.75V≤VCAN_H≤4.5V；
0.5V≤VCAN_L≤2.25；
1.5V≤Vdiff(case 1) 3V or less;
1.5V≤Vdiff(case 1) 3V or less;
2V≤VCM＝0.5*(VCAN_H+VCAN_L)≤3V。
as shown in fig. 2, the CAN bus test integrated circuit further includes an input resistance test circuit, configured to obtain input resistance parameters of the CAN bus, where the input resistance parameters include: an input resistance of the high-order data line, an input resistance of the low-order data line, and a differential resistance. Specifically, the input resistance test circuit includes: a fifth toggle switch S7, a sixth toggle switch S8, a first single-pole double-throw switch S9, a single-pole six-throw switch S10, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12, wherein a third output interface M3 is formed at the stationary end of the first single-pole double-throw switch S9;
the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11 and the twelfth resistor R12 are connected in parallel and then connected to one end of the sixth toggle switch S8, and the other end of the sixth toggle switch S8 forms a low-bit data line interface CANL; one end of the fifth toggle switch S7 is connected with one end of the sixth toggle switch S8, and the other end of the fifth toggle switch S7 is formed with a high-order data line interface CANH; the moving end of the first single-pole double-throw switch S9 is selectively connected with the fifth toggle switch S7 or the sixth toggle switch S8; a power interface U is formed at the stationary end of the single-pole six-throw switch S10, and the movable end of the single-pole six-throw switch S10 is selectively connected with a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 or a twelfth resistor R12.
The purpose of the input resistance test circuit test is to measure the resistance to ground of the high-order data line CAN _ H and the low-order data line CAN _ L and the resistance between the high-order data line CAN _ H and the low-order data line CAN _ L, respectively, in the case where the DUT (device under test) is normally connected to power and ground. The process of obtaining the input resistance parameter of the CAN bus by the input resistance test circuit comprises two conditions of testing without a terminal and testing with a terminal, wherein the voltage of a power supply is selected to be-2V and 7V during the two conditions of testing.
The input resistance test circuit tests the parameter to be the input resistance R of the high-order data linein_CAN_HInput resistance R of low-order data linein_CAN_LDifferential resistance RdiffThree quantities. Since the resistance cannot be directly measured, in the test, the R is indirectly calculated by measuring the high-bit data line voltage (marked as V2) and the low-bit data line voltage (marked as V1) of the CAN busin_CAN_H，Rin_CAN_L. During measurement, a test device (such as an oscilloscope) is connected to the position of a third output interface M3 of the input resistance test circuit, as shown in FIG. 2, measurement of a high-data line voltage and a low-data line voltage (corresponding to V2 and V1) is switched by toggling a first single-pole double-throw switch S9, the single-pole double-throw switch S10 can select test resistances (namely R7, R8, R9, R10, R11 or R12) according to different standard requirements, and the connection end points of the selectable test resistances of the single-pole six-throw switch S10 are a, b, c, d or e.
When the input resistance test circuit does not contain a terminal, the input resistance parameters of the CAN bus are obtained by adopting the following calculation formula:
Figure BDA0001802497880000111
Figure BDA0001802497880000112
Figure BDA0001802497880000113
in the formulae (1), (2) and (3), Rin_CAN_HInput resistance, R, for the upper data linein_CAN_LInput resistance, R, for the lower data linediffIs a differential resistance, RtestIs a test resistance selected according to standard requirements; vCAN_H，VCAN_LRespectively the output voltages of the high-bit data line and the low-bit data line in a recessive state obtained by the output voltage test circuit, if the output voltage is not measured, V is enabledCAN_H＝VCAN_LU is the voltage of the power supply, preferably-2 v and 7 v; v2 and V1 are actual measured voltages of the upper data line and the lower data line respectively; the conditions are satisfied:
6kΩ≤Rin_CAN_H≤50kΩ，6kΩ≤Rin_CAN_L≤50kΩ，ΔRin_CAN≤3％。
before testing the input resistance containing the terminal, the high-order data line CANH and the low-order data line interface CANL need to be shorted, namely S7 and S8 in fig. 2 are closed at the same time, at this time, the high-order data line CAN _ H and the low-order data line CAN _ L have the same resistance to ground, and since CAN _ H and CAN _ L are shorted together, the delta Rin_CANTherefore, when the input resistance test circuit tests the terminal, the input resistance parameters of the CAN bus are obtained by adopting the following calculation formula:
Rin_CAN_H＝Rin_CAN_L＝Rin(4)
Figure BDA0001802497880000114
in the formulae (4) and (5), Rin_CAN_HInput resistance, R, for the upper data linein_CAN_LInput resistance, R, for the lower data lineinIs an input resistance, RtestIs a test resistance selected according to standard requirements; vCANIf the output voltage is not measured, V is set for the output voltage in the recessive state obtained by the output voltage test circuitCAN2.5V; u is the voltage of the power supply, preferably-2 v and 7 v; v is the actual measured voltage; the conditions are satisfied: r is less than or equal to 6k omegain≤50kΩ。
As shown in fig. 3, the CAN bus test integrated circuit further includes an input capacitance test circuit, configured to obtain an input capacitance parameter of the CAN bus, where the input capacitance parameter includes: an input capacitance and a differential capacitance;
the input capacitance test circuit includes: a seventh toggle switch S11, a second single-pole double-throw switch S12, a thirteenth resistor R13 and a diode D1, wherein a high-order data line interface CANH is formed at one end of the seventh toggle switch S11; a low data line interface CANL is formed at the fixed end of the second single-pole double-throw switch S12, and the movable end of the second single-pole double-throw switch S12 is selectively connected with the cathode of the diode D1 or the ground GND; one end of the thirteenth resistor R13 is connected to the cathode of the diode D1, the other end of the thirteenth resistor R13 is grounded to GND, and the anode of the diode D1 is formed with a power interface U.
The input capacitance test circuit obtains input capacitance parameters of the CAN bus by adopting a calculation formula as follows:
Figure BDA0001802497880000121
Figure BDA0001802497880000122
in equations (6) and (7), the discharge time constant τ is 0.721 × t2-t1, t2 is the time taken for the high data line level to drop to 0.2 × high data line level, and t1 is the time taken for the high data line level to drop to 0.8 × high data line level; cinIs an input capacitance, CdiffIs a differential capacitance, tau1Calculated discharge time constant, tau, for measuring input capacitance2A discharge time constant calculated for measuring the differential capacitance; satisfy the condition 40pF ≤ Cin≤140pF，0pF≤Cdiff≤50pF。
When testing an input capacitor, firstly, a DUT (device under test) is prohibited from sending a message, namely TX is pulled up to 5V, a terminal resistor is removed, a signal generator is connected, the signal generator outputs a square wave with the frequency of 10kHz, Rtest is selected to be 6k omega, and the input capacitor C needs to be respectively inputinAnd a differential capacitor CdiffThe test is performed with the difference that whether the low-level data line is connected during the testThe mouth CANL is shorted to ground.
Preferably, after the test circuit design is completed, a device with high reliability needs to be selected and connected to a corresponding position, and in order to prevent the device from being damaged due to direct exposure, the PCB needs to be packaged. Because there are a plurality of change over switches in the whole integrated circuit, in order to facilitate the operation, CAN consider to encapsulate CAN bus test integrated circuit in a casing to set up control panel on the casing, control panel piles up and carries out accurate sign to the function of each switch.
Example two
Please refer to fig. 4, which is a schematic structural diagram of a CAN bus test system in the present embodiment. As shown in fig. 4, the CAN bus test system includes the CAN bus test integrated circuit and a test device connected to the CAN bus test integrated circuit. Preferably, the test equipment is an oscilloscope.
EXAMPLE III
Correspondingly, the embodiment also provides a CAN bus test method. The CAN bus test method according to the present embodiment will be described in detail with reference to fig. 1 to 5.
Firstly, executing a step S1, and respectively connecting a high-bit data line interface and a low-bit data line interface in a corresponding test circuit in the CAN bus test system with a high-bit data line and a low-bit data line of a tested sample according to the test requirement of the CAN bus; wherein the test circuit comprises: an output voltage test circuit, an input resistance test circuit or an input capacitance test circuit; the test requirements include a requirement for testing an output voltage parameter, an input resistance parameter, or an input capacitance parameter of the CAN bus.
Next, step S2 is executed to connect the output interface of the corresponding test circuit with the test equipment according to the test requirement of the CAN bus.
Specifically, if the output voltage of the CAN bus is required to be tested, a high-bit data line interface CANH and a low-bit data line interface CANL of an output voltage test circuit in the CAN bus test system are respectively connected with a high-bit data line CAN _ H and a low-bit data line CAN _ L of a sample to be tested; the first output interface M1 and the second output interface M2 of the output voltage test circuit are connected to two input channels of the test equipment.
If the input resistance of the CAN bus is required to be tested, a high-bit data line interface CANH and a low-bit data line interface CANL of an input resistance testing circuit in the CAN bus testing system are respectively connected with a high-bit data line CAN _ H and a low-bit data line CAN _ L of a tested sample; the third output interface M3 of the input resistance test circuit is connected to the test equipment.
If the input capacitance of the CAN bus is required to be tested, a high-bit data line interface CANH and a low-bit data line interface CANL of an input capacitance testing circuit in the CAN bus testing system are respectively connected with a high-bit data line CAN _ H and a low-bit data line CAN _ L of a tested sample; the fourth output interface M4 of the input capacitance test circuit is connected to the test equipment.
The CAN bus test method is verified to be successfully applied to CAN and CANFD tests of UD8 and XCU according to GWM, SAIC, ISO and other standards, and the test method and the test result are fully approved by customers, so that the CAN bus test method has high popularization commercial value.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the CAN bus test system disclosed in the second embodiment, since the CAN bus test integrated circuit disclosed in the first embodiment is adopted, the description is relatively simple, and relevant points CAN be obtained by referring to part of the description of the embodiments.
For the CAN bus test method disclosed by the embodiment, the structure disclosed by the embodiment corresponds to that disclosed by the embodiment, so that the description is relatively simple, and relevant points CAN be referred to the structural part for description.
In summary, the CAN bus test integrated circuit of the present invention has the following advantages:
(1) the test circuit is divided into an output voltage test circuit, an input resistance test circuit and an input capacitance test circuit in a modularized manner, and the three test circuits CAN independently perform test work, so that the requirements for measuring different parameters of a CAN bus are met, and the interference among the circuits is reduced.
(2) The invention relates to a multi-channel one-selection switch, so that an access circuit can be switched according to test standard requirements and customer requirements to meet multiple standards and customer requirements, the problem that a test needs to be designed for each standard or requirement in the prior art is effectively solved, and the test efficiency is effectively improved.
(3) The invention uniformly packages the designed CAN bus test integrated circuit, accurately describes the functions of each selector switch on the front panel of the packaging equipment, is convenient for fast switching during actual test and further improves the test efficiency.
(4) The CAN bus test integrated circuit CAN be widely applied to various working conditions of CAN bus test, has better universality, avoids the problem that a test circuit needs to be redesigned in each test, and CAN play a role in reducing cost and improving efficiency.
(5) The CAN bus test integrated circuit CAN be integrated in a portable test box, CAN be suitable for various test environments such as laboratories, vehicles, external fields and the like, and has very good popularization value and commercial value.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (12)

1. A CAN bus test integrated circuit, comprising: the output voltage test circuit is used for testing the output voltage parameters of the CAN bus, and the output voltage parameters comprise: the voltage of the upper data line, the voltage of the lower data line, and the differential voltage.
2. The CAN bus test integrated circuit of claim 1, wherein the output voltage test circuit comprises: the circuit comprises a first branch, a second branch, a third branch and a fourth branch which are sequentially connected in parallel, wherein a first single-pole double-throw switch interface (CANH) and a low-bit data line interface (CANL) are formed at two ends of the first branch, and a first output interface (M1) and a second output interface (M2) are formed at two ends of the fourth branch;
wherein the first branch comprises: the circuit comprises a first resistor (R1), a second resistor (R2), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first toggle switch (S1) and a first single-pole-three-throw switch (S5), wherein the first toggle switch (S1), the first resistor (R1) and the second resistor (R2) are sequentially connected in series; the fixed end of the first single-pole-three-throw switch (S5) is connected with a connecting line between the first resistor (R1) and the second resistor (R2), the movable end of the first single-pole-three-throw switch (S5) is selectively connected with one end of the first capacitor (C1), one end of the second capacitor (C2) or one end of the third capacitor (C3), and the first capacitor (C1), the second capacitor (C2) and the third capacitor (C3) are grounded after being connected in parallel;
the second branch circuit includes: the circuit comprises a third resistor (R3), a fourth resistor (R4), a fourth capacitor (C4), a fifth capacitor (C5), a sixth capacitor (C6), a second toggle switch (S2) and a second single-pole-three-throw switch (S6), wherein the second toggle switch (S2), the third resistor (R3) and the fourth resistor (R4) are sequentially connected in series; the fixed end of the second single-pole-three-throw switch (S6) is connected with a connecting line between the third resistor (R3) and the fourth resistor (R4), the movable end of the second single-pole-three-throw switch (S6) is selectively connected with one end of the fourth capacitor (C4), one end of the fifth capacitor (C5) or one end of the sixth capacitor (C6), and the fourth capacitor (C4), the fifth capacitor (C5) and the sixth capacitor (C6) are grounded after being connected in parallel;
the third branch includes: a fifth resistor (R5) and a third toggle switch (S3), wherein one end of the third toggle switch (S3) is connected with the second toggle switch (S2), the other end of the third toggle switch (S3) is connected with the fifth resistor (R5) in series, and the other end of the fifth resistor (R5) is connected with one end, far away from the third resistor (R3), of the fourth resistor (R4) in the second branch;
the fourth branch includes: the circuit comprises a sixth resistor (R6) and a fourth toggle switch (S4), one end of the fourth toggle switch (S4) is connected with the second toggle switch (S2), the other end of the fourth toggle switch (S4) is connected with the sixth resistor (R6) in series, and the other end of the sixth resistor (R6) is connected with one end, far away from the third resistor (R3), of the fourth resistor (R4) in the second branch.
3. The CAN bus test integrated circuit of claim 1, further comprising an input resistance test circuit to obtain input resistance parameters for a CAN bus, the input resistance parameters comprising: the input resistance of the high-order data line, the input resistance of the low-order data line and the differential resistance;
the input resistance test circuit includes: the switch comprises a fifth toggle switch (S7), a sixth toggle switch (S8), a first single-pole double-throw switch (S9), a single-pole six-throw switch (S10), a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11) and a twelfth resistor (R12), wherein a third output interface (M3) is formed at the fixed end of the first single-pole double-throw switch (S9);
the sixth resistor (R7), the eighth resistor (R8), the ninth resistor (R9), the tenth resistor (R10), the eleventh resistor (R11) and the twelfth resistor (R12) are connected in parallel and then connected with one end of the sixth toggle switch (S8), and the other end of the sixth toggle switch (S8) forms a low-bit data line interface (CANL); one end of the fifth toggle switch (S7) is connected with one end of the sixth toggle switch (S8), and the other end of the fifth toggle switch (S7) is formed with a high data line interface (CANH); the moving end of the first single-pole double-throw switch (S9) is selectively connected with the fifth toggle switch (S7) or the sixth toggle switch (S8); a power interface (U) is formed at the fixed end of the single-pole six-throw switch (S10), and the movable end of the single-pole six-throw switch (S10) is selectively connected with a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11) or a twelfth resistor (R12).
4. The CAN bus test integrated circuit of claim 3, wherein the input resistance test circuit obtaining the input resistance parameter of the CAN bus comprises testing both unterminated and unterminated.
5. The CAN bus test integrated circuit of claim 4, wherein the input resistance test circuit obtains the input resistance parameter of the CAN bus using the following calculation formula when the test circuit does not include a terminal:
Figure FDA0001802497870000021
Figure FDA0001802497870000022
Figure FDA0001802497870000023
wherein R isin_CAN_HInput resistance, R, for the upper data linein_CAN_LInput resistance, R, for the lower data linediffIs a differential resistance, RtestIs a test resistance selected according to standard requirements; vCAN_H，VCAN_LRespectively the output voltages of the high-bit data line and the low-bit data line in a recessive state obtained by the output voltage test circuit, if the output voltage is not measured, V is enabledCAN_H＝VCAN_L2.5v, U is the voltage of the power supply; v2 and V1 are actual measured voltages of the upper data line and the lower data line respectively; the conditions are satisfied:
6kΩ≤Rin_CAN_H≤50kΩ，6kΩ≤Rin_CAN_L≤50kΩ，ΔRin_CAN≤3％。
6. the CAN bus test integrated circuit of claim 4, wherein when the input resistance test circuit tests a terminal, the input resistance parameters of the CAN bus are obtained using the following calculation formula:
Rin_CAN_H＝Rin_CAN_L＝Rin(4)
Figure FDA0001802497870000031
wherein R isin_CAN_HInput resistance, R, for the upper data linein_CAN_LInput resistance, R, for the lower data lineinIs an input resistance, RtestIs a test resistance selected according to standard requirements; vCANIf the output voltage is not measured, V is set for the output voltage in the recessive state obtained by the output voltage test circuitCAN2.5V; u is the voltage of the power supply; v is the actual measured voltage; the conditions are satisfied: r is less than or equal to 6k omegain≤50kΩ。
7. The CAN bus test integrated circuit of claim 1, further comprising an input capacitance test circuit to obtain input capacitance parameters for a CAN bus, the input capacitance parameters comprising: an input capacitance and a differential capacitance;
the input capacitance test circuit includes: the circuit comprises a seventh toggle switch (S11), a second single-pole double-throw switch (S12), a thirteenth resistor (R13) and a diode (D1), wherein a high-order data line interface (CANH) and a fourth output interface (M4) are formed at one end of the seventh toggle switch (S11); a low data line interface (CANL) is formed at the fixed end of the second single-pole double-throw switch (S12), and the movable end of the second single-pole double-throw switch (S12) is selectively connected with the cathode of the diode (D1) or the Ground (GND); one end of the thirteenth resistor (R13) is connected with the cathode of the diode (D1), the other end of the thirteenth resistor (R13) is Grounded (GND), and a power interface (U) is formed at the anode of the diode (D1).
8. The CAN bus test integrated circuit of claim 7, wherein the input capacitance test circuit obtains the input capacitance parameter of the CAN bus using the following calculation formula:
Figure FDA0001802497870000032
Figure FDA0001802497870000033
wherein, the discharge time constant τ is 0.721 ═ t2-t1, t2 is the time taken for the high data line level to drop to 0.2 ×, t1 is the time taken for the high data line level to drop to 0.8 ×; cinIs an input capacitance, CdiffIs a differential capacitance, tau1Calculated discharge time constant, tau, for measuring input capacitance2A discharge time constant calculated for measuring the differential capacitance; satisfy the condition 40pF ≤ Cin≤140pF，0pF≤Cdiff≤50pF。
9. A CAN bus test system, which comprises the CAN bus test integrated circuit of any one of claims 1 to 8, and a test device connected to the CAN bus test integrated circuit.
10. The CAN bus test system of claim 9, wherein the test device is an oscilloscope.
11. A CAN bus test method for performing CAN bus test based on the CAN bus test system according to claim 9, the CAN bus test method comprising the steps of:
connecting a high-bit data line interface and a low-bit data line interface in a corresponding test circuit in the CAN bus test system with a high-bit data line and a low-bit data line of a tested sample respectively according to the test requirement of the CAN bus; wherein the test circuit comprises: an output voltage test circuit, an input resistance test circuit or an input capacitance test circuit; the test requirements comprise requirements for testing output voltage parameters, input resistance parameters or input capacitance parameters of the CAN bus;
and connecting the output interface in the corresponding test circuit with the test equipment according to the test requirement of the CAN bus.
12. The CAN bus test method of claim 11 wherein the power supply voltage selected for use during the CAN bus test system test is-2 v and 7 v.
CN201811083206.XA 2018-09-17 2018-09-17 CAN bus test integrated circuit, test system and test method Pending CN110912763A (en)

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