US20110156730A1

US20110156730A1 - Chip-based prober for high frequency measurements and methods of measuring

Info

Publication number: US20110156730A1
Application number: US13/040,304
Authority: US
Inventors: Edward R. Pillai; Erik J. Breiland; Ullrich R. Pfeiffer
Original assignee: Individual
Current assignee: GlobalFoundries Inc
Priority date: 2006-11-03
Filing date: 2011-03-04
Publication date: 2011-06-30
Also published as: CN101173970B; CN101173970A; US7956628B2; US20080106277A1

Abstract

A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 11/556,262 filed Nov. 3, 2006, now pending, the entire contents of which are incorporated herein by reference.

BACKGROUND OF INVENTION

The present disclosure relates to chip-based probers for high frequency measurements and methods of measuring. More particularly, the present disclosure relates to chip-based probers and methods of using.
The use of test equipment such as vector network analyzers (VNA) is becoming increasingly important during the design of integrated circuit (IC) devices and other electronic components. Here, the test equipment is used for modeling and characterization of a particular device-under-test (DUT).
Measurements of the device-under-test at high frequency require very precise calibration. Unfortunately, the interface devices (e.g., cables, connectors, probers, etc) that interface or connect the device-under-test to the test equipment can make parasitic contributions (e.g., capacitive effects, inductive effects, signal attenuation, etc.) that distort the signal being measured.
In order to account for the parasitic contributions of the interface devices, it is becoming common to perform a calibration that principally moves the measurement reference plane from the test equipment to the device-under-test, effectively bypassing the unwanted effects of the interface devices. One known calibration technique uses a set of electrical standards to move the measurement reference plane to the device-under-test. Here, an open circuit, a short circuit, and 50 Ohm Load standard are measured and the results are used to solve a set of simultaneous equations, whose solution is able to identify the error term needed to move the measurement reference plane.
Generally, the measurement of the device-under-test is carried out using either connectors or radio frequency (RF) probers at an interface of the device-under-test. In both cases, external calibration standards are measured in order to be able to move the reference plane of measurement to the device-under-test from the testing equipment.
Unfortunately, the use of RF probers has several shortcomings. For example, the cost of RF probers can be excessive and the probers themselves are very fragile and can be damaged easily. The RF probers are also limited to a finite number of calibration standards, typically including short, open, and load. Further, the behavior of RF probers can change with frequency and the load can start to look like a short, degrading the calibration. In addition, the large number of times the RF probers is contacted and removed for each of the calibration standards adds uncertainty and leads to calibration inaccuracy as well as reduction in probers lifetime due to the fragile nature of the RF probers.
Moreover, it has been determined that even after calibration with RF probers, some unaccounted parasitic effects in the probers and/or connector can degrade the calibration at high frequency.
Accordingly, there is a continuing need for chip-based probers that overcome, alleviate, and/or mitigate one or more of the aforementioned and other drawbacks and deficiencies of prior art chip-based probers for high frequency measurements.

BRIEF DESCRIPTION OF THE INVENTION

A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.
A method of measuring a device-under-test is also provided. The method includes using a plurality of programmable terminations integrated in a chip-based prober to measure a high frequency measurement of the device-under-test.
A method of calibrating a chip-based prober is also provided, which includes digitally selecting one of a plurality of calibration standards resident on a circuit of the chip-based prober.
A circuit to reduce parasitics of programmable termination in a chip-based prober is provided. The circuit includes at least two two biploar transistors in parallel.
The above-described and other features and advantages of the present disclosure will be appreciated and understood by those skilled in the art from the following detailed description, drawings, and appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of an exemplary embodiment of a chip-based prober according to the present disclosure;

FIG. 2 is a sectional view of the chip-based prober of FIG. 1;

FIG. 3 is a bottom view of the chip-based prober of FIG. 1

FIG. 4 illustrates the chip-based prober of FIG. 1 during characterization on the chip-based prober terminations;

FIG. 5 illustrates the chip-based prober of FIG. 1 in use with a two-port vector network analyzer while measuring a four-port device-under-test;

FIG. 6 illustrates an exemplary embodiment of a circuit diagram of the chip-based prober of FIG. 1 and a corresponding Smith chart of impedances; and

FIG. 7 illustrates an alternate exemplary embodiment of a circuit diagram of the chip-based prober of FIG. 1 and a corresponding Smith chart of impedances.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the drawings and in particular to FIGS. 1 through 3, an exemplary embodiment of a chip-based prober according to the present disclosure, generally referred to by reference numeral 10, is shown. Advantageously, chip-based prober 10 uses a programmable termination chip as a non-RF probe.
Chip-based prober 10 includes a DC voltage and control connector 12 in electrical communication with a probe tip 14. Probe tip 14 includes a plurality of probe contact pads 24. In the illustrated embodiment, pads 24 are arranged in a typical ground-signal-ground (GSG) configuration. Of course, it is contemplated by the present disclosure for probe tip 14 to have pads 24 of any desired configuration.
Accordingly, chip-based prober 10 does not need a high cost RF connector. Rather, connector 12 is in electrical communication with a chip carrier 16 and a programmable termination chip 18. In an exemplary embodiment, chip carrier 16 is a printed circuit board. Chip 18 includes a plurality of calibration standards resident thereon, where the desired calibration standard is digitally selectable via connector 12.
Chip 18 includes a plurality of terminations (not shown) interconnected with connector 12 and board 16 through connections 20. Preferably, connections 20 are provided by a simple connection system such as, but not limited to, controlled collapsed chip connections (C4), pin connections, and others. Additionally, chip 18 is interconnected with tip 14 by way of a through wafer via 22.
In this manner, chip-based prober 10 is a low cost chip based non-RF prober that can be used to selectively replace the prior art high cost RF probes used in high frequency measurements. For example, chip-based prober 10 finds use in high frequency measurements such as, but not limited to, detection of Scattering parameters (S-parameters) and Time Domain Reflectometry (TDR).
In addition, chip-based prober 10 uses more than the typical number of calibration standards, which are designed on chip 18 and are switchable digitally in order to calibrate and measure up to frequencies of 110 GHz and beyond.
Chip 18 allows the plurality of terminations of chip-based prober 10 to be selectively programmable so that S-parameters can easily be measured with very high accuracy at millimeter-wave (mmWave) frequencies. Chip 18 also allows the terminations to be integrated into chip-based prober 10 so that S-parameters can easily be measured with very high accuracy at mmWave frequencies. Preferably, probe tip 14 is directly attached to chip 18 by through wafer vias 22.
An exemplary embodiment of a method 30 for characterizing chip-based prober 10 according to the present disclosure is shown in FIG. 4. Here, chip-based prober 10 is characterized as different calibration standards are switched in to chip 18. During method 30, chip-based prober 10 is connected in electrical communication to a vector network analyzer (VNA) 32 and an RF test prober 34 across a through-line 36. Chip-based prober 10 is measured by RF test prober 32 to characterize the prober terminations, including parasitics.
More particularly, the electrical path from C4 connections 20 to the calibration standard on chip 18 have a parasitic associated with it. Before measurement of a device-under-test, method 30 can be used to characterize the parasitic associated with chip-based prober 10. For example, VNA 32 and RF prober 34 can be used to measure chip-based prober 10, while its standards are switched in, across through-line 36 to characterize the probe's parasitic so that the parasitic becomes a known term in addition to the terminations on chip themselves.
Advantageously, chip-based prober 10 can be used in conjunction with standard RF probes in the measurement of two-port and four-port devices-under-test (DUT). In this manner, chip-based prober 10 can take the place of one or more of the more costly and less accurate RF probes.
For example, when measuring a two-port DUT one RF prober and one chip-based prober 10 can be used along with one two-port VNA. Here, the second RF prober typically used in prior art measurements can be replaced with chip-based prober 10.
Further, chip-based prober 10 can be used during measurement of a four-port DUT 40 as shown in FIG. 5. Typically, measurement of a four-port DUT 40 requires two, two-port VNA's, which is cost prohibitive. Advantageously, chip-based prober 10 enables the measurement of four-port DUT 40 with a single two-port VNA 32.
Here, two RF probes 34 and two chip-based probers 10 are needed for four-port measurement. Accordingly, chip-based prober 10 enables the use of the less costly two-port VNA when performing four-port measurement, which can be a significant saving.
During measurement of a device-under-test as shown in FIG. 5, RF probers 34 are placed on each port of the two-port VNA 32, in turn, while chip-based probers 10 are placed on the other port of the VNA, in turn. When using chip-based probers 10, several measurements can be taken with several terminating standards by digitally selecting the desired standard in the chip-based prober, giving a whole series of automatic measurements. Once the series of measurements have been taken, an algorithm can then be used to produce a highly accurate DUT measurement matrix up to frequencies of 110 GHz and beyond.
It should be recognized that chip-based prober 10 is illustrated in FIG. 5 by way of example in use with a single two-port VNA. However, it is contemplated by the present disclosure for chip-based prober 10 to find use in any measurement configuration (n-port) including a two-port measurement.
As discussed above, chip 18 of chip-based prober 10 includes a plurality of calibration standards, which are designed on and are switchable digitally. Referring now to FIG. 6, an exemplary embodiment of a circuit 42 on chip 18 is shown. Circuit 42 is configured to allow one of a plurality of calibration standards to be digitally selected. Additionally, FIG. 6 provides a corresponding Smith chart 44 illustrating the resulting impedances available from circuit 42.
Apart from the usual short, open and load several other circuit 42 includes impedances additional impedances that are all selectable digitally. Circuit 42 is designed to switch in different standards and to obtain impedances that don't meet until very high frequency. By keeping the impedances apart as shown in Smith chart 44, greater accuracy in the characterization of chip-based prober 10 is attainable as compared to prior art probes.
In the embodiment illustrated in FIG. 6, circuit 42 includes at least two biploar transistors 46 in parallel and a resistor 48. Here, the desired impedance is digitally selectable through the control of transistors 46 and resistor 48 via connector 12. Of course, it is contemplated by the present disclosure for circuit 42 as many transistors 46 as are desired for a particular application or use.
In the embodiment of circuit 42 illustrated in FIG. 7, the circuit includes at least two biploar transistors 46 in series. Preferably, one of the bipolar transistors is scaled in size, so as to provide a different on-resistance as compared to the other bipolar transistor. It has been found by the present disclosure that circuit 42, in this embodiment, provides terminations that show very little parasitic effects and on-chip wires, e.g. in the connection of the resistor with the bipolar devices are avoided.
Of course, it should be noted that circuit 42 is illustrated by way of example only having biploar transistors 46. However, it is contemplated by the present disclosure for one or more of transistors 46 to be field effect transistors (FET) such as, but not limited to, n-FET transistors, p-FET transistors, PNP transistors, and other types of transistors that are resident on chip 18.
During characterization of chip-based prober 10 discussed above, the extra impedances provided by circuit 42 allow for obtaining several extra simultaneous equations to identify the calibration error terms of chip-based prober 10 and, thus, enables one to keep calibration impedances away from each other on the Smith chart and attain calibration and measurement up to frequencies of 110 GHz.
Additionally, digital selection of the impedances through circuit 42 means that chip-based prober 10 does not have to be attached and reattached during characterization method 30. Thus, characterization method 30 avoids the uncertainty in the calibration and probe-aging present with prior art prober characterization methods. Preferably, chip-based prober 10 use power from DC voltage and control connector 12 for switching in the on-chip standards.
Once the measurements are complete, an algorithm can be implemented to extract the DUT four-port data up to very high frequencies. In this manner, chip-based prober 10, at a minimum, enables four-port measurement of S-parameters of a device-under-test up to 110 GHz and, in some embodiments into mmWave frequencies.
While the present disclosure has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the scope thereof. Therefore, it is intended that the present disclosure not be limited to the particular embodiment(s) disclosed as the best mode contemplated, but that the disclosure will include all embodiments falling within the scope of the appended claims.

Claims

1. A circuit to reduce parasitics of programmable termination in a chip-based prober, comprising at least two biploar transistors in parallel.

2. The circuit as in claim 1, wherein the circuit is configured to measure up to mmWave frequencies.

3. The circuit as in claim 1, further comprising a resistor.

4. The circuit as in claim 1, wherein one of said at least two bipolar transistors is scaled in size to provide a different on-resistance as compared to another of said at least two bipolar transistors.

5. The circuit as in claim 1, further comprising a programmable termination chip.

6. The circuit as in claim 5, wherein said programmable termination chip comprises a plurality of controlled collapsed chip connections.

7. The circuit as in claim 6, further comprising a voltage and control connector interconnected with said plurality of controlled collapsed chip connections.

8. The circuit as in claim 6, wherein said plurality of calibration standards are digitally selectable via said voltage and control connector.

9. The circuit as in claim 5, wherein said plurality of calibration standards are configured to calibrate and measure up to frequencies of about 110 GHz.

10. The circuit as in claim 1, wherein said plurality of calibration standards are configured to calibrate and measure up to millimeter-wave frequencies.