CN110911364A - 具有集成式陶瓷衬底的嵌入式裸片封装 - Google Patents
具有集成式陶瓷衬底的嵌入式裸片封装 Download PDFInfo
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- CN110911364A CN110911364A CN201910872979.4A CN201910872979A CN110911364A CN 110911364 A CN110911364 A CN 110911364A CN 201910872979 A CN201910872979 A CN 201910872979A CN 110911364 A CN110911364 A CN 110911364A
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Abstract
本申请涉及具有集成式陶瓷衬底的嵌入式裸片封装。封装式电子装置和集成电路包含陶瓷材料或其它导热电绝缘衬底,其具有第一侧上的图案化导电特征,以及第二侧上的导电层。所述IC另外包含安装到所述衬底的半导体裸片,所述半导体裸片包含导电接触结构和电子组件,其中电绝缘层合结构围封所述半导体裸片、所述框架和所述热转移结构。具有导电结构的重布层电连接到所述导电接触结构。
Description
技术领域
本申请涉及裸片封装,且更具体地,涉及具有集成式陶瓷衬底的嵌入式裸片封装。
背景技术
集成电路和封装式电子装置往往是由具有一或多个电子组件的基于半导体的裸片或芯片生产而成。可用的有各种封装类型,包含SMT封装,其具有线接合到引线框的芯片触点和具有安装到衬底的裸片的倒装芯片球栅阵列(FC-BGA)装置,例如印刷电路板(PCB),其又具有用于焊接到用户电路板的导电垫或导电球。嵌入式裸片封装过程在高电压、高功率密度应用中提供优点,有时使用镀铜结构替换接合线或焊料凸块并且抑止封装电感以促进高开关频率操作。可使用散热器(heat spreader)控制裸片温度,例如将铜直接镀覆于裸片上以将裸片连接到外部散热片(heat sink)。然而,热循环或表面安装处理可归因于铜和裸片之间的热膨胀系数(CTE)失配而使裸片机械张紧,并且导致裸片开裂。将铜柱阵列插入于裸片和散热器之间需要附加处理和成本并且抑制散热。
发明内容
所描述实例提供具有陶瓷或其它导热电绝缘衬底的封装式电子装置和集成电路。所述装置还包含安装到所述衬底的半导体裸片,以及包封半导体裸片的一部分和电绝缘导热衬底的一部分的电绝缘层合结构。散热片可安装到导热电绝缘衬底以抽取热量远离半导体裸片。在一个实例中,导热电绝缘衬底提供足够接近所述裸片的热膨胀系数(CTE)的CTE以缓解或避免通到所述裸片的机械应力和在热循环或表面安装处理期间所引起的裸片开裂。在一个实例中,所述装置还包含具有电连接到导电接触结构的导电结构的重布层。
实例方法包含将半导体裸片附接到电绝缘导热衬底上的导电特征,以及形成电绝缘层合结构以封装所述半导体裸片的一部分和所述电绝缘衬底的一部分。在一个实例中,所述电绝缘导热衬底包含陶瓷材料。在一个实例中,所述方法包含将所述裸片和框架附接到载体结构,例如胶粘带,形成所述电绝缘层合结构以封装所述框架的部分以及所述半导体裸片和所述电绝缘衬底的所述部分,以及在形成所述电绝缘层合结构之后移除所述载体结构。在一个实例中,所述方法还包含形成具有电连接到所述半导体裸片的导电接触结构的导电结构的重布层(RDL)结构,以及将散热片安装到电绝缘衬底。
附图说明
图1是集成电路封装式微电子装置的部分截面侧视图,其具有转移来自半导体裸片的顶侧的热量的陶瓷衬底和提供通到裸片的电子组件的连接的重布层结构。
图2是具有安装到陶瓷衬底的散热片的另一集成电路封装式微电子装置的部分截面侧视图。
图3是制造封装式微电子装置的方法的流程图。
图4-12是经历根据图3的方法的制造处理的微电子装置的部分截面侧视图和俯视平面图。
图13是图1和2的封装式微电子装置中的实例半导体裸片的部分截面侧视图。
具体实施方式
在图式中,相同参考编号贯穿全文指代相同元件,且各种特征不必按比例绘制。在以下论述和权利要求书中,术语“包含(including、includes)”、“具有(having、has)”、“带有(with)”或其变化形式意图以类似于术语“包括(comprising)”的方式为包含性的,且因此应被解译为意指“包含但不限于……”。同样,术语“耦合(couple/couples)”意在包含间接或直接电或机械连接或其组合。举例来说,如果第一装置耦合到第二装置或与第二装置耦合,那么所述连接可经由直接电连接,或经由一或多个介入装置和连接的间接电连接。
图1示出封装式电子装置100。在一个实例中,装置100是具有多个互连电子组件的集成电路(IC)。在另一实例中,封装式电子装置100包含单个电子组件。封装式电子装置100包含具有电绝缘导热衬底104的热转移结构102。在一个实例中,衬底104包含陶瓷材料,例如氧化铝材料(例如,Al2O3、氧化铝)、氮化铝(AlN)、氮化硅(Si3N4)、烧制或烧结氧化锆陶瓷(例如,CZ6、CZ8、CZ9、AZ-25、AZ-67、AZ-93、CZR、CZRy、ZTA、ZTA-A3、ZTA-90和/或氧化锆增韧氧化铝(例如,ZTA、ZTA-02、ZTA-14、ZTA-20)中的一或多种。衬底104具有具导电特征106的第一侧105(例如,图1中的底侧),以及具导电层108的第二(例如,顶部)侧107。在一个实例中,第一侧105包含多个图案化导电特征106,不过并非所有可能实施方案都如此要求。在一个实例中,导电特征106和导电层108镀铜于衬底104的相应侧105和107上,并且使用掩模蚀刻或其它合适的图案化处理经图案化。此外,在所说明实例中,一或多个导电特征106提供与装置100的一或多个半导体裸片的电子电路的电互连,而导电层108可使用热界面材料(例如,焊料、热脂膏、间隙垫等,图1中未示出)附接到外部散热片以促进装置100的一或多个半导体裸片的冷却。
图1中的封装式电子装置100还包含半导体裸片110。在所说明实例中,装置100包含两个半导体裸片110。在其它实例中,装置100可包含单个半导体裸片110。如下文结合图13进一步论述,在一个实例中,半导体裸片110包含一或多个电子组件。在所说明实例中,个别裸片110各自包含安装到衬底104的第一侧105上的导电特征106的第一侧111(例如,顶侧),以及具有导电接触结构122的第二(例如,底部)侧113。在一个实例中,裸片110的第一侧111包含经由焊料112焊接到导电特征106的一或多个导电特征。此外,在一个实例中,裸片110的导电接触结构122电连接到裸片110的一或多个电子组件。在一个实例中,如下文结合图13进一步说明和描述,导电接触结构122是制造于半导体衬底上的金属化结构的导电特征,以提供通到形成于所述半导体衬底上和/或中的一或多个电子组件的电互连。另外,裸片110可包含第一侧111上的导电结构以促进焊接到热转移结构102的导电特征106。在一个实例中,这提供用于经由热转移结构102移除来自裸片110的一或多个电子组件的热量的热冷却通道。
图1的装置100还包含框架114,以及包封半导体裸片110的至少一部分以及框架114的一部分和热转移结构102的一部分的电绝缘层合结构116。框架114可以是为经组装封装式装置100提供机械刚度和支撑的任何合适材料,例如FR4。在一个实例中,导电接触结构122是裸片110上的用于电互连的垫。在一个嵌入式裸片封装实例中,导电接触结构122是适用于后续镀覆处理以镀覆图1中的重布层(RDL)结构118的铜特征121的薄铜晶种层。
在所说明实例中,封装式电子装置100另外包含用于在一或多个裸片110的一或多个导电接触结构122与用户系统(未示出)之间提供电连接性的RDL结构118。图1中的实例重布层结构118包含电绝缘隔离材料120,以及电连接到导电接触结构122的一或多个导电结构121、124、126。
图1中的实例RDL结构118中的导电结构包含顶部镀铜特征(例如,迹线)121,其镀覆到裸片110的下侧上的一或多个导电接触结构122的部分上。RDL结构118还包含导电通孔或电镀通孔126,其在隔离材料120的顶侧与底侧之间延伸并且提供顶侧导电接触结构122中的至少一些到底侧导电接触结构124的电连接。在一个实例中,导电结构121、124、126镀铜或镀铝。在一个实施方案中,底侧导电接触结构124能够焊接到用户印刷电路板(未示出)以将一或多个裸片110的电路电连接到主机电路。
图2示出另一集成电路封装式微电子装置200,其包含如上文所描述的图1的装置100中的热转移结构102、第一和第二半导体裸片110、框架114、RDL结构118和电绝缘层合结构116。图2中的封装式装置200还包含安装到热转移结构102的导电层108的散热片202。在此实例中,散热片202有助于抽取热量穿过导热衬底104远离裸片110以增强装置200中的功率密度。在这点上,直接耦合的铜散热器结构具有大约16的的热膨胀系数(CTE),而裸片110的半导体衬底的CTE通常低得多(例如,遭到硅为大约3的CTE)。导热衬底104具有与直接耦合的铜散热器相比更接近裸片110的CTE的CTE。因此,导热衬底104缓和或避免通到裸片的机械应力以及在热循环或表面安装处理期间所引起的裸片开裂。在一个实例中,衬底104是具有大约4到5的CTE的氮化铝陶瓷材料,其相对接近裸片110的半导体衬底的CTE。
图3示出用于制造封装式电子装置的过程或方法300。在一个实施方案中,方法300可用于制造上文所描述的装置100、200。方法300包含在302处制造电绝缘导热衬底。302处的制造包含在衬底的第一侧上形成一或多个图案化导电特征,并且在衬底的第二侧上形成导电层。在302处可使用任何适合的制造处理,例如直接敷铜(DBC)衬底处理、绝缘金属衬底(IMS)处理、直接敷铝(DBA)处理等。图4示出在图3中的302处制造的热转移结构102的实例。图4中的结构102包含具有上部第一侧105和下部第二侧107的陶瓷衬底104。结构102包含第一侧105上的一或多个导电特征106(例如,镀覆且图案化铜导体),以及在衬底104的第二侧107上提供导电层的镀覆且图案化铜108。在其它实例中,导电特征106和108可为铝,并且可通过镀敷或沉积随后进行图案化、直接接合或其它制造技术来制造。在一个实例中,一或多个导电特征106提供用于电路的活动连接。在此实例中,导电层108提供用于例如散热片的热管理组件的互连,以抽取热量远离连接的裸片。
方法300另外包含图3中的304处的裸片附接处理,其将半导体裸片110附接到电绝缘衬底104上的导电特征106。图5说明其中执行表面安装焊接过程500的一个实例,其将第一和第二裸片结构110附接到衬底104的第一侧105上的对应导电特征106。图6示出具有焊接到衬底104的导电特征106的裸片110的结构的俯视图。图5中的实例处理包含执行表面安装焊接过程500,其将裸片110的第一侧111上的导电特征焊接到衬底104的第一侧105上的导电特征106。在一个实例中,表面安装附接过程500回焊焊料112以形成裸片110的导电结构与衬底104的导电特征106之间的电连接。
过程300在图3中继续进行306处的嵌入式裸片封装过程,其使用绝缘衬底104和一或多个附接的裸片110。嵌入式裸片封装过程306包含在308处将框架和裸片110的第二侧113附接到载体。图7示出包含执行取放式附接过程700的实例,所述取放式附接过程700将框架114和裸片110附接到胶粘带载体702(例如,胶带)。在一个实施方案中,所述附接包含框架114的腔中的一或多个裸片110和28胶带载体702的倒装附接。
在图3中的310处,所述过程另外包含形成电绝缘层合结构以围封半导体裸片的一部分、框架的一部分和电绝缘衬底104的一部分。图8说明其中执行层合过程800的一个实例,其形成至少部分地包封半导体裸片110的一部分、框架114的一部分和衬底104的一部分的电绝缘层合结构116。在一个实例中,使用真空沉积将电绝缘层合结构116层合于载体702上的裸片110上方,使得其在裸片110中的每一个中和周围回流并且填充所有间隙空间。在倒装芯片附接到载体702之后,此层116在互连垫106和111中和周围流动并且同时包埋裸片110,以将裸片110永久性接合于嵌入式裸片结构内。在一个实例中,如图8中所示,处理800覆盖衬底104的顶侧107和导电层108,其中电绝缘层合结构116延伸到框架114上方的非零厚度802。
执行如图9所示的移除过程900,其在形成电绝缘层合结构116之后在图3中的312处移除胶粘带载体结构702。在一个实例中,方法300另外包含在314处移除层合结构116的顶侧的一部分。图10示出包含执行等离子体蚀刻过程1000的一个实例,其移除层合结构116的顶侧的一部分以暴露衬底104的顶侧107上的导电层108。在所说明实例中,等离子体蚀刻过程1000移除层合结构116的一部分以留下如图10中所示在框架114上方具有一厚度1002的结构116。在其它实例中,举例来说,在不使用附加散热片结构的情况下或在层合结构116最初形成为暴露衬底104的顶侧107上的导电层108的顶部的一厚度的情况下,省略314处的等离子体蚀刻移除处理。
在一个实例中,312处的胶粘带载体的移除(或314处的包含的任何等离子蚀刻)完成嵌入式裸片封装处理306,且如图9和/或10中所示的装置100准备好安装于用户电路板(未示出)上。在此实施方案中,裸片110的导电接触结构122暴露并且从如图9和10中所示的装置结构的底部向外延伸。
在另一实例中,过程300另外包含作为裸片封装处理306的部分在316处形成重布层(RDL)结构。图11示出其中执行过程1100的实例,其形成RDL结构118以提供半导体裸片110的导电接触结构122的外部电连接性。实例RDL结构118包含通过电连接到半导体裸片110的接触结构122的图案化镀铜结构121、124、126形成的导电结构。在一个实例中,316处的RDL结构形成包含执行在图10中示出的结构的底部镀覆或以其它方式沉积铜迹线结构121的一或多个镀覆过程1100。在一个实例中,使用镀覆过程1100使用半导体裸片110的导电接触结构122镀覆结构121,其为开始形成迹线结构121的镀覆过程的争论层。接着使用镶嵌或其它沉积过程形成me铜通孔结构126,其至少部分地接触镀铜迹线结构121中的一或多个。在此实例中,RDL制造处理1100另外包含沉积或施用内建材料(例如,隔离材料)121,随后在如图11和1中所示的结构的底部镀覆或以其它方式沉积第二铜迹线结构124。此实例提供RDL结构118的暴露的下部导电特征124,其从衬底120向下延伸以允许焊接到用户电路板(未示出)。
还参考图12,在某些实例中,方法300还包含在318处将散热片安装到衬底104,以通到热转移结构102的导电层108。图12说明一个实例封装式电子装置200。在此实例中,执行散热片附接过程1200,其将散热片结构202附接到衬底104的顶侧107的导电层108的暴露部分。图12的实例包含RDL结构118。在其它实施方案中,可省略RDL结构118。
图13示出图1和2的封装式微电子装置100、200中的实例半导体裸片110的另外细节。图13的实例裸片110包含安置于半导体衬底1302上或中的多个电子组件1301(例如,金属氧化物半导体(MOS)晶体管)。虽然实例裸片110是具有多个组件1301的集成电路,但其它微电子装置实施方案可包含单个电子组件。在一个实例中,半导体衬底1302是硅晶片、绝缘体上硅(SOI)衬底或其它半导体结构。隔离结构1303安置于衬底1302的上表面或侧部的选择部分上。在一些实例中,隔离结构1303可为浅沟槽隔离(STI)特征或场氧化物(FOX)结构。裸片110还包含安置于衬底1302上方的多层金属化结构1304、1306。金属化结构包含形成于衬底1302上方的第一电介质结构层1304,以及多层级上部金属化结构1306。在一个实例中,第一电介质1304结构层是安置于组件1301和衬底1302的上表面上方的前金属电介质(PMD)层。在一个实例中,第一电介质结构层1304包含沉积于组件1301、衬底1302和隔离结构1303上方的二氧化硅(SiO2)。
图13的实例裸片110包含具有第一层1308的6层上部金属化结构1306,其在本文中被称作层间或层间电介质(ILD)层。可在不同实施方案中使用不同数目个层。在一个实例中,第一ILD层1308和上部金属化结构1306的其它ILD层由二氧化硅(SiO2)或其它合适的电介质材料形成。在某些实施方案中,在两个阶段中形成多层上部金属化结构1306的个别层,包含金属内电介质(IMD,未示出)子层和覆盖在IMD子层上的ILD子层。个别IMD和ILD子层可由任何适合的一或多种电介质材料形成,例如基于SiO2的电介质材料。钨或其它导电触点1310延伸穿过第一电介质结构层1304的选择性部分。第一ILD层1308和上部金属化结构1306中的后续ILD层包含形成于下伏层的顶表面上的导电金属化互连结构1312,例如铝。在此实例中,第一层1308和后续ILD层还包含导电通孔1313,例如钨,其提供从个别层的金属化特征1312到上覆的金属化层的电连接。图13的实例包含安置于第一层1308上方的第二层1314。ILD层1308包含导电互连结构1312和通孔1313。所说明的结构包含具有对应电介质层1315、1316和1317的其它金属化层级,以及最上部或顶部金属化层1318。在此实例中,个别层1315-1318包含导电互连结构1312和相关联的通孔1313。衬底1302、电子组件1301、第一电介质结构层1304和上部金属化结构1306形成具有上侧或表面1321的晶片或裸片1320。在一个实例中,金属化结构1306的上侧1321形成晶片或裸片1320的上侧。
顶部金属化层1318包含两个实例导电特征1319,例如最上部铝通孔。导电特征1319包含最上部金属化层1318的顶部处的晶片或裸片1320的上侧1321处的侧部或表面。可提供任何数目个导电特征1319。导电特征1319中的一或多个可与电子组件1301电耦合。在一个实例中,上部ILD电介质层1318被例如氮化硅(SiN)、氮氧化硅(SiOxNy)或二氧化硅(SiO2)的一或多个钝化层1323(例如,保护性覆层(PO)和/或钝化层)覆盖。在一个实例中,一或多个钝化层1323包含一或多个开口,其暴露导电特征1319的一部分以允许特征1319电连接到对应接触结构。
在图13的实例中,裸片110包含两个导电接触结构122。接触结构122从金属化结构1306的上侧1321向外(例如,沿着图13中的“Y”方向向上)延伸。个别接触结构122与导电特征1319中的对应者电耦合。在一个实例中,个别接触结构122包含从金属化结构1306的上侧1321向外延伸的导电晶种层,例如铜。在一个实例中,接触结构122包含钛(Ti)或钛钨(TiW)。
所公开的实例提供低应力、热增强型电隔离封装技术和封装式电子装置设备,其对于大功率、应力灵敏封装例如具有高功率密度和压电特性的氮化镓(GaN)裸片110具有特定益处。所公开的实例有助于从一或多个半导体裸片110到封装的顶侧的导热的热流路径,而不管是否包含顶部安装的散热片,同时保持裸片110处的低机械应力并且在某些实例中通过使用RDL结构118达成低寄生电感。陶瓷衬底和其它电绝缘导热热转移结构102提供与硅、氮化镓或其它半导体裸片结构110的良好CTE匹配,这有助于减小裸片/衬底界面处的机械应力。现有技术未尝试将陶瓷衬底集成到嵌入式封装制造过程中,并且替代地,使用阵列铜通孔减缓通到裸片(例如,GaN系统)的机械应力。然而,这类通孔阵列将显著成本和复杂性添加到制造过程流。所公开的实例提供改进的热性能,其可包含陶瓷衬底上的厚铜层,以提供促进热耗散的有利热转移结构102,同时提供用于顶侧散热片特征的电隔离。所公开的解决方案不需要用于散热片附接的单独热界面材料(TIM),并且允许在单个共享散热片下方安装多个裸片结构110(例如,半桥、全桥等)。所公开的实例提供可扩展到电力转换电路中的多相脚架构解决方案,例如包含在陶瓷衬底上形成多相脚电路以用于电力模块应用。所公开的实例将具有多相脚的陶瓷衬底集成于容易制造的嵌入式封装过程流中,并且通过显著的裸片应力减小。
上述实例仅说明本公开的各种方面的若干可能的实施例,其中所属领域的其他技术人员在阅读和理解本说明书和附图之后将构想出等效变化和/或修改。对所描述的实施例的修改是可能的,且在权利要求书的范围内的其它实施例是可能的。
Claims (20)
1.一种封装式电子装置,其包括:
热转移结构,其包含具有导电特征的电绝缘导热衬底;
半导体裸片,其安装到所述电绝缘导热衬底的所述导电特征,所述半导体裸片包含导电接触结构,以及电连接到所述导电接触结构的电子组件;
框架,和
电绝缘层合结构,其围封所述半导体裸片的一部分、所述框架的一部分和所述热转移结构的一部分。
2.根据权利要求1所述的封装式电子装置,其中所述电绝缘衬底包含陶瓷材料。
3.根据权利要求2所述的封装式电子装置,其中所述电绝缘衬底包含氧化铝、氮化铝、氮化硅、烧制或烧结的氧化锆陶瓷或氧化锆增韧氧化铝。
4.根据权利要求2所述的封装式电子装置,其另外包括具有电连接到所述导电接触结构的导电结构的重布层RDL结构。
5.根据权利要求4所述的封装式电子装置,其另外包括安装到所述热转移结构的所述导电层的散热片。
6.根据权利要求2所述的封装式电子装置,其另外包括安装到所述热转移结构的所述导电层的散热片。
7.根据权利要求1所述的封装式电子装置,其另外包括具有电连接到所述导电接触结构的导电结构的重布层RDL结构。
8.根据权利要求7所述的封装式电子装置,其另外包括安装到所述热转移结构的所述导电层的散热片。
9.根据权利要求1所述的封装式电子装置,其另外包括安装到所述热转移结构的所述导电层的散热片。
10.根据权利要求1所述的封装式电子装置,其中所述半导体裸片包含:
半导体衬底,其中所述电子组件安置于所述半导体衬底上或中;和
金属化结构,其安置于所述半导体衬底上方,其中所述导电结构从所述金属化结构向外延伸。
11.一种用于制造封装式电子装置的方法,所述方法包括:
将半导体裸片附接到电绝缘导热衬底上的导电特征;和
形成电绝缘层合结构以围封所述半导体裸片的一部分和所述电绝缘导热衬底的一部分。
12.根据权利要求11所述的方法,其另外包括:
将所述裸片和框架附接到载体结构;
形成所述电绝缘层合结构以围封所述框架的部分以及所述半导体裸片和所述电绝缘衬底的所述部分;和
在形成所述电绝缘层合结构之后移除所述载体结构。
13.根据权利要求12所述的方法,其中所述载体结构是胶粘带。
14.根据权利要求11所述的方法,其另外包括:
形成具有电连接到所述半导体裸片的导电接触结构的导电结构的重布层RDL结构。
15.根据权利要求14所述的方法,其另外包括:
将散热片安装到所述电绝缘导热衬底。
16.根据权利要求11所述的方法,其另外包括:
将散热片安装到所述电绝缘导热衬底。
17.根据权利要求11所述的方法,其中所述电绝缘导热衬底包含陶瓷材料。
18.一种集成电路IC,其包括:
热转移结构,其包含具有导电特征的电绝缘导热衬底;
半导体裸片,其安装到所述电绝缘导热衬底的所述导电特征,所述半导体裸片包含导电接触结构,以及电连接到所述导电接触结构的电子组件;
电绝缘层合结构,其围封所述半导体裸片的一部分和所述热转移结构的一部分;和
重布层RDL结构,其具有电连接到所述导电接触结构的导电结构。
19.根据权利要求18所述的IC,其另外包括安装到所述热转移结构的所述导电层的散热片。
20.根据权利要求18所述的IC,其中所述电绝缘导热衬底包含陶瓷材料。
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