CN110896591A

CN110896591A - Flexible circuit board, chip package including the same, and electronic device including the chip package

Info

Publication number: CN110896591A
Application number: CN201910864755.9A
Authority: CN
Inventors: 李甸真; 尹亨珪; 郑惠营
Original assignee: LG Innotek Co Ltd
Current assignee: LG Innotek Co Ltd
Priority date: 2018-09-12
Filing date: 2019-09-12
Publication date: 2020-03-20
Anticipated expiration: 2039-09-12
Also published as: KR20200030411A; JP7431537B2; US11089682B2; CN110896591B; TWI815963B; US20200084888A1; TW202023333A; JP2020043343A

Abstract

According to an embodiment, a flexible circuit board includes: a first substrate; a second substrate disposed on the first substrate and including an opening; a first conductive pattern part disposed on a bottom surface of the first substrate; a second conductive pattern part disposed on a top surface of the second substrate; a third conductive pattern part disposed between the first substrate and the second substrate; an upper protective layer partially disposed on the second conductive pattern part and including a first open region, wherein the third conductive pattern part includes: a first inner lead pattern part disposed in the opening of the second substrate; and a first extension pattern part connected to the first inner lead pattern part, the second conductive pattern part including: a second inner lead pattern part disposed in the first opening region of the upper protective layer; and a second extension pattern part connected to the second inner lead pattern part, and the number of the first inner lead pattern parts is greater than the number of the second inner lead pattern parts.

Description

Flexible circuit board, chip package including the same, and electronic device including the chip package

Cross Reference to Related Applications

This application claims priority from korean patent application No.10-2018-0109253 (filed on 12/9/2018) based on 35u.s.c.119 and 35u.s.c.365, the entire contents of which are incorporated herein by reference.

Technical Field

Embodiments relate to a flexible circuit board, a chip package including the flexible circuit board, and an electronic device including the chip package.

Background

In detail, according to the flexible circuit board, the chip package of the flexible circuit board, and the electronic device including the chip package, different types of chips may be mounted on different layers of one substrate in the flexible circuit board.

Recently, various electronic products have become thin, compact, and lightweight. Accordingly, various studies have been made on mounting semiconductor chips in a narrow area of an electronic device at high density.

In the mounting scheme, since a chip-on-film (COF) scheme uses a flexible substrate, the COF scheme may be applied to a flat panel display as well as a flexible display. In other words, the COF scheme is focused on that the COF scheme can be applied to various wearable electronic devices. In addition, since the COF scheme can realize fine pitches, the COF scheme can be used to realize a Quad High Definition (QHD) display having high resolution due to an increase in the number of pixels.

COF is a scheme of mounting a semiconductor chip on a flexible circuit board in the form of a thin film. For example, the semiconductor chip may be an Integrated Circuit (IC) chip or a large scale integrated circuit (LSI) chip.

However, the COF flexible circuit board cannot be directly connected between the display panel and the main board.

In other words, at least two printed circuit boards are required between the display panel and the main board.

An electronic apparatus having a display unit requires a plurality of printed circuit boards, so that the thickness of the electronic apparatus may increase. In addition, the size of the printed circuit board may be a limitation for miniaturization of electronic devices. In addition, the joint failure of the printed circuit board may deteriorate the reliability of the electronic apparatus.

Therefore, a new flexible circuit board that can solve these problems is required.

Disclosure of Invention

Embodiments provide a flexible circuit board capable of mounting a plurality of chips on one substrate, a chip package including the flexible circuit board, and an electronic device including the chip package.

In addition, embodiments provide a flexible circuit board capable of mounting a plurality of chips on different layers of one substrate, a chip package including the flexible circuit board, and an electronic device including the chip package.

Technical objects to be achieved by the proposed embodiments are not limited to the above technical objects, and other technical objects not described will be clearly understood from the following description by those skilled in the art to which the proposed embodiments belong.

According to one embodiment, a flexible circuit board includes: a first substrate; a second substrate disposed on the first substrate and including an opening; a first conductive pattern part disposed on a bottom surface of the first substrate; a second conductive pattern part disposed on a top surface of the second substrate; a third conductive pattern part disposed between the first substrate and the second substrate; and an upper protective layer partially disposed on the second conductive pattern part and including a first open region, wherein the third conductive pattern part includes: a first inner lead pattern part disposed in the opening of the second substrate; and a first extension pattern part connected to the first inner lead pattern part, the second conductive pattern part including: a second inner lead pattern part disposed in the first opening region of the upper protective layer; and a second extension pattern part connected to the second inner lead pattern part, and the number of the first inner lead pattern parts is greater than the number of the second inner lead pattern parts.

In addition, the width of the first inner lead pattern part may be smaller than the width of the second inner lead pattern part.

In addition, the width of the first extended pattern part may be smaller than the width of the second extended pattern part.

In addition, the pitch between the first inner lead pattern parts may be smaller than the pitch between the second inner lead pattern parts.

In addition, the interval between the first extended pattern portions may be smaller than the interval between the second extended pattern portions.

In addition, at least one of the first to third conductive pattern parts may include: a conductive pattern layer; and a plating layer disposed on the conductive pattern layer and including tin.

In addition, the conductive pattern layer of at least one of the first to third conductive pattern parts may include: a first conductive pattern comprising nickel and chromium; a second conductive pattern disposed on the first conductive pattern and including copper; and a third conductive pattern disposed on the second conductive pattern and including copper.

In addition, the flexible circuit board may further include: at least one first via (via) passing through the first substrate and connecting the first conductive pattern to the third conductive pattern; and at least one second via passing through the second substrate and connecting the second conductive pattern and the third conductive pattern, wherein each of the first and second vias may include: a first via layer provided on an inner wall of a through hole (via hole) formed through the first substrate or the second substrate and containing palladium; and a second via layer disposed in the first via layer to fill the via, and comprising copper.

In addition, the first substrate may have a thickness thicker than that of the second substrate.

In addition, the flexible substrate may further include a lower protective layer partially disposed under the first conductive pattern part and including a third opened region, wherein the first conductive pattern part may include first and second outer lead pattern parts exposed through the third opened region.

In addition, the second conductive pattern part may further include a third inner lead pattern part exposed through the second opening region of the upper protective layer, and the total number of the second and third inner lead pattern parts may be less than the number of the first inner lead pattern parts.

Meanwhile, according to one embodiment, a chip package includes a flexible circuit board, wherein the flexible circuit board includes: a first substrate; a second substrate disposed on the first substrate and including an opening; a first conductive pattern part disposed on a bottom surface of the first substrate; a second conductive pattern part disposed on a top surface of the second substrate; a third conductive pattern part disposed between the first substrate and the second substrate; and an upper protective layer partially disposed on the second conductive pattern part and including a first open region, the third conductive pattern part including: a first inner lead pattern part disposed in the opening of the second substrate; and a first extension pattern part connected to the first inner lead pattern part, the second conductive pattern part including: at least one second inner lead pattern part disposed in the first opening region of the upper protective layer; and a second extended pattern portion connected to the second inner lead pattern portion, the first connection portion and the first chip being disposed on the first inner lead pattern portion, the second connection portion and the second chip being disposed on the second inner lead pattern portion, and the number of terminals included in the first chip being greater than the number of terminals included in the second chip.

In addition, the first chip may include a driving IC chip, and the second chip may include at least one of a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor.

In addition, the second conductive pattern part may further include a third inner lead pattern part exposed through the second opening region of the upper protective layer, the third connection part and the third chip may be disposed on the third inner lead pattern part, and the total number of terminals included in the second chip and the third chip may be less than the number of terminals included in the first chip.

Further, according to one embodiment, an electronic device includes: a flexible circuit board, the flexible circuit board comprising: a first substrate; a second substrate disposed on the first substrate and including an opening; a first conductive pattern part disposed on a bottom surface of the first substrate; a second conductive pattern part disposed on a top surface of the second substrate; a third conductive pattern part disposed between the first substrate and the second substrate; an upper protective layer partially disposed on the second conductive pattern part and including a first opening region and a second opening region; and a lower protective layer partially disposed under the first conductive pattern part and including a third opened region, wherein the third conductive pattern part includes: a first inner lead pattern part disposed in the opening of the second substrate; and a first extension pattern part connected to the first inner lead pattern part, the second conductive pattern part including: a second inner lead pattern part disposed in the first opening region of the upper protective layer; a third inner lead pattern part disposed on the second opening region of the upper protective layer; and a second extended pattern part connected to at least one of the second and third inner lead pattern parts, the first conductive pattern part including first and second outer lead pattern parts exposed through the third opening region, and the number of the first inner lead pattern parts being greater than the number of the second inner lead pattern parts, the electronic device further including: a display panel connected to the first outer lead pattern part; and a main board connected to the second outer lead pattern part.

According to one embodiment, a flexible circuit board includes: a first substrate; a second substrate disposed on the first substrate; a first conductive pattern part disposed on a bottom surface of the first substrate; a second conductive pattern part disposed on a top surface of the second substrate; and a third conductive pattern part disposed between the first substrate and the second substrate. Each of the first to third conductive pattern portions may include: a wiring pattern layer; a first plating layer; and a second plating layer. In addition, a protective layer may be formed in one region of each of the first and second conductive pattern parts to form a protective part, and the protective part may not be provided in a region other than the one region. The plurality of regions where the protective portion is not provided may be a first opening region and a second opening region. In other words, the first open region may be formed on the first substrate, and the second open region may be formed on the second substrate. The second plating layer in the first open region may have a different tin (Sn) content than the second plating layer in the second open region.

The first connection portion may be disposed on the first opening region, and the first chip may be disposed on the first connection portion. The first connection portion may electrically connect the second conductive pattern portion to the first chip.

The second connection part may be disposed on the second opening region, and the second chip may be disposed on the second connection part. The second connection portion may electrically connect the second conductive pattern portion to the second chip. In other words, in the present invention, the second substrate exposes the first opening region where the first chip is disposed from the upper region of the first substrate. In addition, a second opening region where no protection portion is provided may be formed on the second substrate.

In addition, the number of terminals included in the first chip may be greater than the number of terminals included in the second chip. In other words, a first chip having a large number of terminals may be disposed on the first opening region, and a second chip having a smaller number of terminals than the first chip may be disposed on the second opening region.

Accordingly, embodiments may provide a flexible circuit board chip package in which different types of first and second chips are mounted on a single flexible circuit board, so that reliability may be improved.

In addition, according to another embodiment, the flexible circuit board may directly connect the display panel to the main board. Accordingly, the size and thickness of the flexible circuit board that transmits signals generated from the display panel to the main board can be reduced.

In addition, in the flexible circuit board according to the embodiment, the through hole in the first substrate and the through hole in the second substrate can be efficiently formed. In other words, in the flexible circuit board according to the embodiment, the number of through holes may be reduced to about 1/2 as compared to the case where the first chip is disposed on the second substrate.

Accordingly, in the flexible circuit board, the chip package including the flexible circuit board, and the electronic device including the chip package according to the embodiment, a space for other components and/or a battery space can be enlarged. In addition, since it is not necessary to connect a plurality of printed circuit boards, convenience of processes and reliability of electrical connection can be improved.

Accordingly, the flexible circuit board, the chip package including the flexible circuit board, and the electronic device including the chip package according to the embodiment may be suitable for an electronic device having a high resolution display unit.

Drawings

Fig. 1a is a sectional view showing an electronic apparatus having a display unit including a conventional printed circuit board.

Fig. 1b is a sectional view illustrating a state in which the printed circuit board of fig. 1a is bent.

Fig. 1c is a plan view illustrating a state in which the printed circuit board of fig. 1a is bent.

Fig. 2a is a cross-sectional view illustrating an electronic device having a display unit including a flexible circuit board according to an embodiment.

Fig. 2b is a sectional view illustrating a state in which the flexible circuit board of fig. 2a is bent.

Fig. 2c is a plan view illustrating a state in which the flexible circuit board of fig. 2a is bent.

Fig. 3a is a sectional view illustrating a multi-layer flexible circuit board according to another embodiment.

Fig. 3b is a cross-sectional view illustrating a chip package including the multi-layer flexible circuit board of fig. 3 a.

Fig. 4a is a sectional view illustrating a multi-layer flexible circuit board according to still another embodiment.

Fig. 4b is a sectional view illustrating a multi-layer flexible circuit board according to still another embodiment.

Fig. 5a is a cross-sectional view illustrating a chip package including a multi-layer flexible circuit board according to still another embodiment.

Fig. 5b is a cross-sectional view illustrating a chip package including a multi-layer flexible circuit board according to still another embodiment.

Fig. 6 is a view illustrating a detailed structure of a conductive pattern part and a via hole included in the multi-layer flexible circuit board of fig. 3 a.

Fig. 7 is an enlarged cross-sectional view illustrating one region of a multi-layer flexible circuit board according to an embodiment.

Fig. 8 is a plan view illustrating a first substrate included in the multi-layer flexible circuit board of fig. 3 a.

Fig. 9 is a bottom view illustrating a first substrate included in the multi-layer flexible circuit board of fig. 3 a.

Fig. 10a and 10b are plan views schematically showing the chip package of fig. 3b including a multi-layer flexible circuit board.

Fig. 11a and 11b to fig. 13a and 13b are views illustrating a process of manufacturing the chip package of fig. 3b including the multi-layer flexible circuit board by using the multi-layer flexible circuit board of fig. 3 a.

Fig. 14, 15, 16a, 16b, 16c, 17, 18 are views showing various electronic devices including a flexible circuit board.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical idea of the present invention is not limited to some embodiments to be described below, but may be implemented in various other forms, and one or more components of the embodiments may be selectively combined and replaced to be used within the scope of the technical idea of the present invention.

In addition, unless specifically defined and described explicitly, terms (including technical terms and scientific terms) used in embodiments of the present invention may be construed as meanings that can be generally understood by those of ordinary skill in the art to which the present invention pertains, and meanings of commonly used terms (e.g., terms defined in dictionaries) may be interpreted in consideration of contextual meanings of the related art. Also, terms used in the embodiments of the present invention are used to illustrate the embodiments, and are not intended to limit the present invention.

In this specification, the singular form may also include the plural form unless the context clearly indicates otherwise, and when described as "at least one (or one or more) of A, B and C", it may include one or more of all combinations that may be combined with A, B and C. In addition, in describing the components of embodiments of the present invention, terms such as first, second, A, B, (a) and (b) may be used.

These terms are only used to distinguish one element from another element, and the nature, sequence, order, and the like of the respective elements are not limited by these terms. In addition, when it is described that one component is "connected", "coupled", or "coupled" to another component, it should be construed that not only is directly connected, coupled, or coupled to the other component, but also can be "connected", "coupled", or "coupled" through another component between the one component and the other component.

In addition, when it is described that "upper (upper)" or "lower (lower)" of each component is formed or disposed, it is to be understood that two components are in direct contact with each other and one or more other components are formed or disposed between the two components. In addition, when it is expressed as "upper (upper)" or "lower (lower)", it may refer to a downward direction as well as an upward direction with respect to one component.

Referring to fig. 1a to 1c, a printed circuit board according to a comparative example will be described.

An electronic device including a display unit requires at least two printed circuit boards to transmit signals of a display panel to a main board.

At least two printed circuit boards may be included in the electronic device including the display unit according to the comparative example.

The electronic apparatus including the display unit according to the comparative example may include a first printed circuit board 10 and a second printed circuit board 20.

The first printed circuit board 10 may be a Flexible Printed Circuit Board (FPCB). In detail, the first printed circuit board 10 may be a Chip On Film (COF) flexible printed circuit board. The first printed circuit board 10 may be a COF flexible printed circuit board on which the first chip C1 is mounted. In more detail, the first printed circuit board 10 may be a COF flexible printed circuit board for arranging a driving IC chip.

The second printed circuit board 20 may be a flexible printed circuit board. In detail, the second printed circuit board 20 may be a flexible printed circuit board for arranging the second chip C2 having a type different from that of the first chip C1. In this case, the second chip C2 may be a chip other than the driving IC chip, and may refer to various chips arranged on the flexible printed circuit board for electrical connection, such as a chip other than the driving IC chip, a semiconductor device, and a socket (socket). The second printed circuit board 20 may be a flexible printed circuit board for arranging a plurality of second chips C2. For example, the second printed circuit board 20 may be a flexible printed circuit board for arranging a plurality of second chips C2a and C2b of different types.

Since the second printed circuit board 20 is provided as a flexible printed circuit board, the second printed circuit board 20 may be thicker than the first printed circuit board 10 as a COF flexible printed circuit board.

The first printed circuit board 10 and the second printed circuit board 20 may have different thicknesses from each other. The thickness of the second printed circuit board 20 may be greater than that of the first printed circuit board 10. For example, the first printed circuit board 10 may have a thickness of about 20 to 100 μm. The second printed circuit board 20 may have a thickness of about 100 to 200 μm. For example, the total thickness t1 of the first printed circuit board 10 and the second printed circuit board may be 200 μm to 250 μm.

In the electronic apparatus having the display unit according to the comparative example, since the first printed circuit board and the second printed circuit board are required between the display panel and the main board, the total thickness of the electronic apparatus may increase. In detail, since the electronic apparatus having the display unit according to the comparative example requires the first printed circuit board and the second printed circuit board to be vertically stacked, the overall thickness of the electronic apparatus may increase.

The first printed circuit board 10 and the second printed circuit board 20 may be formed through different processes. For example, the first printed circuit board 10 may be manufactured by a roll-to-roll process (roll-to-roll process). The second printed circuit board 20 may be manufactured by a sheet scheme.

The first printed circuit board 10 and the second printed circuit board 20 may be provided with different types of chips, and pitches between conductive pattern portions for connecting the respective chips may be different from each other. For example, the pitch of the conductive pattern parts provided on the second printed circuit board 20 may be greater than the pitch of the conductive pattern parts provided on the first printed circuit board 10. For example, the pitch of the conductive pattern portions provided on the second printed circuit board 20 may be 100 μm or more, and the pitch of the conductive pattern portions provided on the first printed circuit board 10 may be less than 100 μm.

In detail, when the first printed circuit board 10 having the conductive pattern portions arranged at the fine pitch is manufactured by the roll-to-roll process, the process efficiency may be improved and the process cost may be reduced. Meanwhile, since it is difficult to process the second printed circuit board 20 having the conductive pattern portions arranged at the pitch of 100 μm or more in the roll-to-roll process, a sheet process is generally used.

Since the first and second printed circuit boards according to the comparative example are formed through processes different from each other, process efficiency may be reduced.

Further, in the chip package including the flexible circuit board according to the comparative example, since it is difficult to arrange different types of chips on one substrate, separate first and second printed circuit boards are required.

Further, in the chip package including the flexible circuit board according to the comparative example, it is difficult to connect different types of chips on one substrate.

In other words, conventionally, the first printed circuit board and the second printed circuit board may be disposed between the display panel and the main board.

In order to control, process or transmit the R, G, B signal generated from the display panel 30, the first printed circuit board 10 may be connected to the second printed circuit board 20, and the second printed circuit board 20 may be connected to the main board 40.

One end of the first printed circuit board 10 may be connected to the display panel 30. The display panel 30 may be connected to the first printed circuit board 10 by an adhesive layer 50.

The other end of the first printed circuit board 10 opposite to the one end may be connected to the second printed circuit board 20. The first printed circuit board 10 may be connected to the second printed circuit board 20 through an adhesive layer 50.

One end of the second printed circuit board 20 may be connected to the first printed circuit board 10, and the other end of the second printed circuit board 20 opposite to the one end may be connected to the main board 40. The second printed circuit board 20 may be connected to the main board 40 by an adhesive layer 50.

The electronic apparatus having the display unit according to the comparative example may require separate adhesive layers 50 between the display panel 30 and the first printed circuit board 10, between the first printed circuit board 10 and the second printed circuit board 20, and between the second printed circuit board 20 and the main board 40. In other words, since the electronic apparatus having the display unit according to the comparative example requires a plurality of adhesive layers, the reliability of the electronic apparatus may be reduced due to defective connection of the adhesive layers. In addition, the adhesive layer disposed between the first printed circuit board 10 and the second printed circuit board 20 vertically connected to each other may increase the thickness of the electronic apparatus.

Referring to fig. 1b and 1c, the first printed circuit board 10, the second printed circuit board 20, the display panel 30, and the main board 40 accommodated in the electronic apparatus according to the comparative example will be described.

Fig. 1b is a sectional view showing a state in which the printed circuit board of fig. 1a is bent, and fig. 1c is a bottom plan view of fig. 1 b.

The display panel 30 and the main board 40 may be opposite to each other. The first printed circuit board 10 including the bent region may be disposed between the display panel 30 and the main board 40 facing each other.

One region of the first printed circuit board 10 may be bent, and the first chip C1 may be disposed in the non-bent region.

In addition, the second printed circuit board 20 may face the display panel 30. The second chip C2 may be disposed in the non-bent region of the second printed circuit board 20.

Referring to fig. 1c, since the comparative example requires a plurality of substrates, a length L1 in one direction may be the sum of the lengths of the first and second printed

circuit boards

10 and 20. The length L1 of the first printed circuit board 10 and the second printed circuit board 20 in one direction may be the sum of the length of the short side of the first printed circuit board 10 and the length of the short side of the second printed circuit board 20. For example, the length L1 of the first and second printed

circuit boards

10 and 20 in one direction may be 30 to 40 mm. However, the length L1 of the first printed circuit board 10 and the second printed circuit board 20 in one direction may vary depending on the type of chip to be mounted and the type of electronic device.

Since the electronic apparatus according to the comparative example requires a plurality of printed circuit boards, a space for mounting other components or a space for disposing the battery 60 may be reduced.

Recently, electronic devices such as smartphones have additionally been provided with components having various functions to enhance convenience or security of users. For example, an electronic device such as a smartphone or a smartwatch may be equipped with a plurality of camera modules (dual camera modules), or additionally provided with components having various functions such as iris recognition and Virtual Reality (VR). Therefore, it is important to secure a space for installing the additional components.

In addition, various electronic devices including wearable devices require an increase in battery space in order to improve user convenience.

Therefore, since the printed circuit board used in the existing electronic device is replaced with one printed circuit board, the importance of securing a space for mounting a new component or securing a space for enlarging the size of the battery is increased.

In the electronic apparatus according to the comparative example, different types of first and second chips may be disposed on the first and second printed

circuit boards

10 and 30, respectively. Therefore, the thickness of the adhesive layer 50 between the first printed circuit board 10 and the second printed circuit board 30 and the thickness of the second printed circuit board 30 may increase the thickness of the electronic device.

In addition, a battery space or a space for mounting other components may be reduced by the size of the second printed circuit board 30.

Furthermore, joint failure in the first and second printed circuit boards may reduce the reliability of the electronic device.

In order to solve the above-described problems, embodiments may provide a flexible circuit board having a novel structure capable of mounting a plurality of chips on one substrate, a chip package including the flexible circuit board, and an electronic device including the chip package. The same reference numerals in the embodiment and the comparative example denote the same components, and a repetitive description of the above comparative example will be omitted.

Referring to fig. 2a to 2c, an electronic device including a flexible circuit board according to an embodiment will be described.

The electronic device according to the embodiment may use one printed circuit board to transmit signals of the display panel to the main board. The printed circuit board included in the electronic device including the display unit according to the embodiment may be one flexible printed circuit board. Accordingly, the flexible printed circuit board 100 may be bent between the display unit and the main board facing each other to connect the display unit to the main board.

In detail, the flexible circuit board 100 according to the embodiment may be one substrate for arranging a plurality of chips of different types.

The flexible printed circuit board 100 according to the embodiment may be a substrate for arranging different types of the first and second chips C1 and C2.

The thickness t2 of the flexible printed circuit board 100 according to the embodiment may be 20 μm to 100 μm. For example, the thickness t2 of the flexible printed circuit board 100 may be 30 μm to 80 μm. For example, the thickness t2 of the flexible printed circuit board 100 may be 50 μm to 75 μm. However, the thickness of the flexible circuit board 100 according to the embodiment may be designed in various sizes according to the type of a chip to be mounted, the type of an electronic device, and the number of layers of a substrate constituting the flexible circuit board 100.

In this case, when the thickness t2 of the flexible circuit board 100 is less than 20 μm, the flexible circuit board 100 may be broken when the flexible circuit board 100 is bent (or bent), and the breakage may occur due to heat generated from a mounted chip or the like.

The thickness t2 of the flexible printed circuit board 100 according to the embodiment may include a thickness of about 1/5 to 1/2 of the thickness t1 of the first and second printed circuit boards according to the comparative example. In other words, the thickness t2 of the flexible printed circuit board 100 according to the embodiment may include a thickness of about 20% to 50% of the thickness t1 of the first and second printed circuit boards according to the comparative example. For example, the thickness t2 of the flexible printed circuit board 100 according to the embodiment may include a thickness of about 25% to 40% of the thickness t1 of the first and second printed circuit boards according to the comparative example. For example, the thickness t2 of the flexible printed circuit board 100 according to the embodiment may include a thickness of about 25% to 35% of the thickness t1 of the first and second printed circuit boards according to the comparative example.

Since the electronic apparatus having the display unit according to the embodiment may be formed of one flexible circuit board 100 between the display panel and the main board, the overall thickness of the electronic apparatus may be reduced. In detail, since the electronic device having the display unit according to the embodiment requires a single-layer printed circuit board, the overall thickness of the electronic device may be reduced.

In addition, according to the embodiment, the adhesive layer 50 between the first printed circuit board and the second printed circuit board, which is included in the comparative example, may be omitted, and thus the total thickness of the chip package including the flexible circuit board and the electronic apparatus including the chip package may be reduced.

In addition, according to the embodiment, since the adhesive layer 50 between the first printed circuit board and the second printed circuit board can be omitted, problems caused by adhesive failure can be solved, so that the reliability of the electronic apparatus can be improved.

In addition, a bonding process for the printed circuit board may be omitted, so that process efficiency may be improved and process costs may be reduced.

In addition, since the substrates that have been managed in a separate process are processed in one process, process efficiency and product yield may be improved.

The flexible circuit board 100 according to an embodiment may include a bending region and a non-bending region. Since the flexible printed circuit board 100 according to the embodiment includes the bending region, and the display panel 30 and the main board 40 facing each other may be connected to each other.

The non-bent region of the flexible circuit board 100 according to the embodiment may face the display panel 30. The first chip C1 and the second chip C2 may be disposed on the non-bent region of the flexible circuit board 100 according to the embodiment. Accordingly, the flexible circuit board 100 according to the embodiment may be able to stably mount the first chip C1 and the second chip C2.

Fig. 2c is a bottom plan view of fig. 2 b.

Referring to fig. 2c, since one substrate is required according to the embodiment, the length L2 in one direction may be the length of one substrate. The length L2 of the flexible circuit board 100 in one direction according to the embodiment may be the length of the short side of the flexible circuit board 100 according to the embodiment. For example, the length L2 of the flexible printed circuit board 100 in one direction may be 10mm to 50 mm. For example, the length L2 of the flexible printed circuit board 100 in one direction may be 10mm to 30 mm. For example, the length L2 of the flexible printed circuit board 100 in one direction may be 15mm to 25 mm. However, the embodiment is not limited thereto, and may be designed in various sizes according to the type and/or number of chips to be arranged and the type of electronic device. According to the embodiment, a plurality of chips are mounted on one substrate, and thus the length of the flexible circuit board can be reduced to 50mm or less. When the length of the flexible circuit board is 10mm or less, the degree of freedom in design of chips to be mounted may be reduced, and the interval between the chips may be narrow, which may affect the mutual electrical characteristics of the chips.

The length L2 of the flexible circuit board 100 in one direction according to the embodiment may include a length of about 50% to 70% of the length L1 of the first and second printed circuit boards in one direction according to the comparative example. For example, the length L2 of the flexible circuit board 100 in one direction according to the embodiment may include a length of about 55% to 70% of the length L1 of the first and second printed circuit boards in one direction according to the comparative example. The length L2 of the flexible circuit board 100 in one direction according to the embodiment may include a length of about 60% to 70% of the length L1 of the first and second printed circuit boards in one direction according to the comparative example.

Accordingly, in the embodiment, the size of the chip package including the flexible circuit board 100 in the electronic device may be reduced, so that a space for disposing the battery 60 may be enlarged. In addition, the planar area of the chip package including the flexible circuit board 100 according to the embodiment may be reduced, so that a space for mounting other components can be secured.

Hereinafter, the flexible circuit board 100 and the chip package thereof according to the embodiment will be described with reference to the accompanying drawings.

Hereinafter, a multi-layer flexible printed circuit board according to a preferred embodiment will be described.

Fig. 3a is a sectional view illustrating a multi-layer flexible circuit board according to another embodiment, fig. 3b is a sectional view illustrating a chip package including the multi-layer flexible circuit board of fig. 3a, fig. 4a is a sectional view illustrating a multi-layer flexible circuit board according to still another embodiment, fig. 4b is a sectional view illustrating a multi-layer flexible circuit board according to still another embodiment, fig. 5a is a sectional view illustrating a chip package including a multi-layer flexible circuit board according to still another embodiment, fig. 5b is a sectional view illustrating a chip package including a multi-layer flexible circuit board according to still another embodiment, and fig. 6 is a view illustrating a detailed structure of a conductive pattern part and a through hole included in the multi-layer flexible circuit board of fig. 3 a.

Referring to fig. 3a, 3b, 4a, 4b, 5a, 5b, 6 and 7, a multi-layer flexible printed circuit board according to an embodiment of the present invention will be described.

Fig. 3a, 3b, 4a, 4b, 5a and 5b are various cross-sectional views illustrating a multi-layered flexible printed circuit board according to an embodiment, focusing on mounting a first chip and a second chip and connecting a display panel and a main board. In other words, fig. 3a, 3b, 4a, 4b, 5a, and 5b are views for describing various cross-sectional structures of the third conductive pattern part for mounting the first chip, the second conductive pattern part for mounting the second chip, and the first conductive pattern part for connecting the display panel to the main board. In the above description, the display panel and the main board are described as being connected to the first conductive pattern part, but this is one embodiment, and the positions of the outer leads connected to the display panel and the main board may be variously changed. This will be described in detail below with reference to the accompanying drawings.

Referring to fig. 3a, 3b, 4a, 4b, 5a and 5b, the multi-layer flexible printed circuit board 100 according to the embodiment may be a three-layer flexible printed circuit board having three electrode pattern parts.

In the present invention, the flexible circuit board 100 may be a multi-layer flexible circuit board on which the conductive pattern portions CP are respectively disposed on the surfaces of a plurality of substrates.

To this end, the multi-layer flexible circuit board 100 according to the embodiment may include: a substrate 110 including a first substrate 111 and a second substrate 112; and a wiring pattern layer 120 disposed on a bottom surface of the first substrate 111, disposed on a top surface of the second substrate 112, disposed between the first substrate 111 and the second substrate 112.

In addition, the plating layer 130 and the protective layer 140 may be disposed on the wiring pattern layer 120 disposed on the bottom surface of the first substrate 111, and the wiring pattern layer 120 disposed on the top surface of the second substrate 112.

In the flexible circuit board 100 according to the embodiment, the wiring pattern layer 120 may be formed on the first substrate 111, and the second substrate 112 may be disposed on the first substrate 111 to cover the wiring pattern layer 120. Accordingly, after the wiring pattern layer 120, the plating layer 130, and the protective layer 140 are disposed on the top surface of the second substrate 112, the wiring pattern layer 120, the plating layer 130, and the protective layer 140 may be disposed on the bottom surface of the first substrate 111.

In addition, the flexible circuit board 100 according to the embodiment may have a source material in which a metal layer is formed on the upper/lower portion of the first substrate 111, wherein the metal layer formed on the upper/lower portion of the first substrate 111 may be patterned to form the wiring pattern layer 120 on the upper/lower portion of the first substrate 111, and the second substrate 112 may be disposed on the first substrate 111 to cover the wiring pattern layer 120. Accordingly, after the wiring pattern layer 120 is formed on the top surface of the second substrate 112, the plating layer 130 and the protective layer 140 may be disposed on the top and bottom surfaces of the substrate.

The wiring pattern layer 120 may be formed on the top surface of the first substrate 111, the bottom surface of the first substrate 111, and the top surface of the second substrate 112.

Each wiring pattern layer 120 may include a metal material having excellent conductivity. In more detail, the wiring pattern layer 120 may include copper (Cu). However, the embodiment is not limited thereto, and the wiring pattern layer 120 may include at least copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo), gold (Au), titanium (Ti) metals, and alloys thereof.

The wiring pattern layer 120 may have a thickness of 1 μm to 15 μm. For example, the wiring pattern layer 120 may have a thickness of 1 μm to 10 μm. For example, the wiring pattern layer 120 may have a thickness of 2 μm to 10 μm.

When the thickness of the wiring pattern layer 120 is less than 1 μm, the resistance of the wiring pattern layer may increase. When the thickness of the wiring pattern layer 120 is greater than 10 μm, it may be difficult to realize a fine pattern.

The plating layer 130 may be disposed on the wiring pattern layer 120. The plating layer 130 may include a first plating layer 131 and a second plating layer 132.

The first plating layer 131 may be disposed on the wiring pattern layer 120, and the second plating layer 132 may be disposed on the first plating layer 131. The first and second plating layers 131 and 132 may be formed as two layers on the wiring pattern layer 120 to prevent whisker formation. Therefore, a short circuit can be prevented from occurring between the patterns of the wiring pattern layer 120. In addition, since two plating layers are provided on the wiring pattern layer 120, the bonding characteristics with the chip can be improved. When the wiring pattern layer includes copper (Cu), the wiring pattern layer may not be directly bonded to the first chip C1, and a separate bonding process may be required. Meanwhile, when the plating layer disposed on the wiring pattern layer includes tin (Sn), the surface of the plating layer may be a pure tin layer, and thus the plating layer may be easily bonded to the first chip C1. In this case, the wire connected to the first chip C1 can be easily connected to the pure tin layer only by heat and pressure, so that the accuracy of chip wire bonding and the convenience of the manufacturing process can be improved.

The region where the first plating layer 131 is disposed may correspond to the region where the second plating layer 132 is disposed. In addition, the area where the first plating layer 131 is disposed may correspond to the area where the second plating layer 132 is disposed.

The plating layer 130 may include tin (Sn). For example, the first and second plating layers 131 and 132 may include tin (Sn).

For example, the wiring pattern layer 120 may be formed of copper (Cu), and the first and second plating layers 131 and 132 may be formed of tin (Sn). When the plating layer 130 contains tin, since tin (Sn) has excellent corrosion resistance, the wiring pattern layer 120 can be prevented from being oxidized.

Meanwhile, the material of the plating layer 130 may have lower conductivity than the material of the wiring pattern layer 120. The plating layer 130 may be electrically connected to the wiring pattern layer 120.

The first and second plating layers 131 and 132 are formed of the same material, i.e., tin (Sn), but may be formed through separate processes.

When the manufacturing process of the flexible circuit board according to the embodiment includes a heat treatment process such as heat curing, copper (Cu) of the wiring pattern layer 120 or tin (Sn) of the plating layer 130 may be diffused. In detail, the curing of the protective layer 140 may cause diffusion of copper (Cu) of the wiring pattern layer 120 or tin (Sn) of the plating layer 130.

Therefore, as the diffusion concentration of copper (Cu) decreases from the surface of the first plating layer 131 to the second plating layer 132, the copper (Cu) content may continuously decrease. Meanwhile, the tin (Sn) content may continuously increase from the surface of the first plating layer 131 to the second plating layer 132. Accordingly, the uppermost portion of the plating layer 130 may include a pure tin layer.

In other words, at least a part of the plating layer 130 may be an alloy of tin and copper due to a chemical reaction at the lamination interface of the wiring pattern layer 120 and the plating layer 130. The thickness of the alloy of tin and copper may be increased after curing the protective layer 140 on the plating layer 130, as compared to the thickness of the alloy of tin and copper after forming the plating layer 130 on the wiring pattern layer 120.

The alloy of tin and copper contained in at least a portion of the plating layer 130 may have the chemical formula Cu_xSn_yWherein 0 is<x+y<12. For example, in the above chemical formula, the sum of x and y can be represented as 4. ltoreq. x + y. ltoreq.11. For example, the alloy of tin and copper included in the plating layer 130 may include Cu₃Sn and Cu₆Sn₅At least one of (1). In detail, the first plating layer 131 may be an alloy layer of tin and copper.

In addition, the first and second plating layers 131 and 132 may have different tin and copper contents from each other. The first plated layer 131, which is in direct contact with the copper wiring pattern layer, may have a greater copper content than the second plated layer 132. This will be described in detail below. The plating layer according to the embodiment may prevent electrochemical migration resistance (electrochemical migration resistance) due to diffusion of Cu/Sn, thereby preventing defective wire connection due to metal growth.

However, the embodiment is not limited thereto, and the plating layer 130 may include one of a Ni/Au alloy, gold (Au), nickel immersion gold (ENIG), a Ni/Pd alloy, and an Organic Solderability Preservative (OSP).

The first and second plated

layers

131 and 132 may have thicknesses corresponding to each other or different thicknesses from each other. The total thickness of the first and second plating layers 131 and 132 may be 0.3 to 1 μm. The total thickness of the first and second plating layers 131 and 132 may be 0.3 to 0.7 μm. The total thickness of the first and second plating layers 131 and 132 may be 0.3 to 0.5 μm. The plating layer of one of the first and second plating layers 131 and 132 may have a thickness of 0.05 μm to 0.15 μm or less. For example, the first plating layer 131 and

the plating layer of one of the second plating layers 132 may have a thickness of 0.07 μm to 0.13 μm or less.

The protective layer 140 may be partially disposed on the wiring pattern layer 120. For example, the protective layer 140 may be disposed on the plating 130 on the wiring pattern layer 120. The protective layer 140 may cover the plating layer 130 to prevent the wiring pattern layer 120 and the plating layer 130 from being damaged or separated due to oxidation.

The protective layer 140 may be partially disposed in an area other than an area where the wiring pattern layer 120 and/or the plating layer 130 are electrically connected to the display panel 30, the main board 40, the first chip C1, or the second chip C2.

Accordingly, the protective layer 140 may partially overlap the wiring pattern layer 120 and/or the plating layer 130.

The area of the protective layer 140 may be smaller than that of the substrate 110. The protective layer 140 may be disposed in a region other than the end portion of the substrate, and may include a plurality of open regions.

The protective layer 140 may include an open region having a hole-like shape. In this case, the opening region may be a region for opening a region where the chip is disposed. In addition, the opening region may be a region exposing an opening formed in the substrate.

The protective layer 140 may include an insulating material. The protective layer 140 may include various materials that may be applied and heated to be cured to protect the surface of the conductive pattern part. The protective layer 140 may be a resist layer. For example, the protective layer 140 may be a solder resist layer containing an organic polymer material. For example, the protective layer 140 may include an epoxy acrylate based resin. In detail, the protective layer 140 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acryl-based monomer, and the like. However, the embodiment is not limited thereto, and the passivation layer 140 may be one of a photoresist layer, a cap layer, and a polymer material.

The protective layer 140 may have a thickness of 1 μm to 20 μm. The protective layer 140 may have a thickness of 1 μm to 15 μm. For example, the thickness of the protective layer 140 may be 5 μm to 20 μm. When the thickness of the protective layer 140 is greater than 20 μm, the thickness of the flexible circuit board may increase. When the thickness of the protective layer 140 is less than 1 μm, the reliability of the conductive pattern part included in the flexible circuit board may be reduced.

Hereinafter, the bottom surface of the first substrate 111 and the top surface of the second substrate 112 may be referred to as the top and bottom surfaces of the substrate 110, or one surface and the other surface of the substrate 110.

In other words, the upper wiring pattern layer, the upper plating layer, and the upper protective layer may be disposed on one surface of the substrate 110 according to the embodiment, and the lower wiring pattern layer, the lower plating layer, and the lower protective layer may be disposed on the other surface opposite to the one surface. In addition, a central wiring pattern layer may be disposed inside the substrate 110, i.e., between the first substrate 111 and the second substrate 112.

In addition, when the flexible circuit board 100 according to the embodiment has a source material in which a metal layer is formed on the upper/lower portion of the first substrate 111, the metal layer formed on the upper/lower portion of the first substrate 111 is patterned to form the wiring pattern layer 120 on the upper/lower portion of the first substrate 111, the second substrate 112 is disposed on the first substrate 111 to cover the wiring pattern layer 120, thus, the wiring pattern layer 120 is formed on the top surface of the second substrate 112, the thickness of the upper wiring pattern layer may be different from the thickness of the central wiring pattern layer and the thickness of the lower wiring pattern layer, and the thickness of the upper wiring pattern layer may be smaller than the thickness of the central wiring pattern layer and the thickness of the lower wiring pattern layer, because the wiring pattern layer 120 is formed on the top surface of the second substrate 112 separately from the source material.

The upper wiring pattern layer may include a metal material corresponding to the metal material of the central wiring pattern layer and the lower wiring pattern layer. Therefore, process efficiency can be improved. However, the embodiment is not limited thereto, and the upper wiring pattern layer may include other conductive materials.

The thickness of the upper wiring pattern layer, the thickness of the central wiring pattern layer, and the thickness of the lower wiring pattern layer may correspond to each other. Therefore, process efficiency can be improved. Meanwhile, since the upper and lower wiring pattern layers are disposed on the outer surface of the substrate, the upper and lower wiring pattern layers are exposed to the outside, and the central wiring pattern layer is protected by the first and

second substrates

111 and 112.

Therefore, the plating and the protective layer may be provided on the upper wiring pattern layer and the lower wiring pattern layer, and the plating and the protective layer may not be provided on the central wiring pattern layer. In this case, the upper plating layer may be provided on the upper wiring pattern layer, and the lower plating layer may be provided on the lower wiring pattern layer. Since the upper and lower plating layers are applied, adhesion with a chip mounted on a flexible circuit board or adhesion with a display and a main board connected to the flexible circuit board can be easily performed, and electrical characteristics can be improved.

Meanwhile, the upper plating layer may include a metal material corresponding to that of the lower plating layer. Therefore, process efficiency can be improved. However, the embodiment is not limited thereto, and the upper plating layer may include other conductive materials.

The thickness of the upper plating layer may correspond to the thickness of the lower plating layer. Therefore, process efficiency can be improved.

The substrate 110 may include a plurality of through holes (holes). The penetration holes of the substrate 110 may be formed separately or simultaneously by a mechanical process or a chemical process. For example, the through hole of the substrate 110 may be formed through a drilling process or an etching process. For example, the through-hole of the substrate may be formed by a stamping and desmear (desmear) process using a laser. The desmear process may be a process of removing polyimide stains attached to the inner side surfaces of the through-holes. The inner surface of the polyimide substrate may have an inclined surface like a straight line through the desmear process.

In this case, the through-hole may be formed through both the first substrate 111 and the second substrate 112 constituting the substrate 110, may be formed through only the first substrate 111, and may be formed through only the second substrate 112. In this case, the through-hole may also be referred to as a through-hole.

The wiring pattern layer 120, the plating layer 130, and the protective layer 140 may be disposed on the substrate 110. In detail, the wiring pattern layer 120, the plating layer 130, and the protective layer 140 may be sequentially disposed on both surfaces of the substrate 110. The wiring pattern layer 120 may be provided between the first substrate 111 and the second substrate 112 constituting the substrate 110.

The wiring pattern layer 120 may be formed by at least one of evaporation, plating, and sputtering.

For example, a wiring layer for forming a circuit may be formed by electroplating after sputtering. For example, the wiring layer for forming the circuit may be a copper plating layer formed by electroless plating. Alternatively, the wiring layer may be a copper plating layer formed by electroless plating and by electrolytic plating.

Next, after laminating the dry film on the wiring layer, patterned wiring layers may be formed on both surfaces (i.e., top and bottom surfaces) of the flexible circuit board through exposure, development, and etching processes. Thus, the wiring pattern layer 120 can be formed.

The conductive material may be filled in the vias V1, V2, V3, V4, V5, and V6 formed through the substrate 110. The conductive material filled in the via hole may be a conductive material corresponding to or different from the conductive material of the wiring pattern layer 120. For example, the conductive material filled in the via hole may include at least copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo), gold (Au), titanium (Ti) metals, and alloys thereof. The electrical signal of the second conductive pattern part CP2 on the top surface of the second substrate 112 may be transmitted to the third conductive pattern part CP3 between the first substrate 111 and the second substrate and to the first conductive pattern part CP1 on the bottom surface of the first substrate 111 through the conductive material filled in the through hole.

Next, a plating layer 130 may be formed on the wiring pattern layer 120 constituting the first, second, and third conductive pattern parts CP1, CP2, and CP 3. In this case, the plating layer 130 may be formed only on a partial area of the wiring pattern layer 120, or may be formed on the entire area of the wiring pattern layer 120. In addition, the plating layer 130 may be formed only on the first and second conductive pattern parts.

Thereafter, the protection part PP may be screen-printed on the first and second conductive pattern parts CP1 and CP 2.

Accordingly, the first, second, and third conductive pattern parts CP1, CP2, and CP3 may further include a plating layer 130 in addition to the wiring pattern layer 120. However, a portion of the third conductive pattern part CP3 may include only the wiring pattern layer 120, and the remaining portion may include the plating 130 in addition to the wiring pattern layer 120. In this case, the remaining portion may be an inner lead portion corresponding to a region of the third conductive pattern part CP3 where the first chip C1 is mounted.

Hereinafter, the relationship between the plating 130 and the wiring pattern layer 120 constituting the first, second, and third conductive pattern parts CP1, CP2, and CP3 will be described. In this case, the wiring pattern layer of the first conductive pattern part CP1 may be referred to as a lower wiring pattern layer, the wiring pattern layer constituting the second conductive pattern part CP2 may be referred to as an upper wiring pattern layer, and the wiring pattern layer constituting the third conductive pattern part CP3 may be referred to as a central wiring pattern layer.

Meanwhile, each of the first to third conductive pattern parts may include a lead pattern region and an extension region. The third conductive pattern part may include a first inner lead pattern part and a first extension pattern part. In this case, the first inner lead pattern part may be a portion exposed through the opening of the second substrate. In addition, the first extension pattern part may be a portion covered by the second substrate except for the first inner lead pattern part. In addition, the second conductive pattern part may include a second inner lead pattern part and a second extension pattern part. In this case, the second inner lead pattern part may be a portion exposed through the opened region of the opening. In addition, the second extension pattern part may be a portion covered by the protective layer except for the second inner lead pattern part. In addition, the first conductive pattern part may include an outer lead pattern part and a third extension pattern part. In this case, the outer lead pattern part may be a portion exposed through the opening region of the protective layer. In addition, the third extension pattern part may be a portion covered by the protective layer except the outer lead pattern part.

The areas of the upper and lower wiring pattern layers 120 and 120 may correspond to or be different from the area of the plating layer 130. The area of the first plated layer 131 may correspond to or be different from the area of the second plated layer 132.

Referring to fig. 3a, the areas of the upper and lower wiring pattern layers 120 and 120 may correspond to the area of the plating 130. The area of the first plated layer 131 may correspond to the area of the second plated layer 132.

Referring to fig. 4a and 4b, the areas of the upper and lower wiring pattern layers 120 and 120 may be different from the area of the plating 130.

Referring to fig. 4a, the area of the first plated layer 131 may correspond to the area of the second plated layer 132. In addition, the area of each of the first and second plating layers 131 and 132 may be smaller than the area of the upper and lower wiring pattern layers 120 and 120. In other words, the first and second plating layers 131 and 132 may be selectively formed only on exposed regions exposed to the outside in the surfaces of the upper and lower wiring pattern layers 120 and 120. Therefore, since the plating layer required for facilitating connection with the chip is provided only at the connection portion with the chip, the amount of the plating layer is reduced, so that the material cost can be reduced.

Referring to fig. 4b, the areas of the upper and lower wiring pattern layers 120 and 120 may correspond to the area of the first plating layer 131. The area of the first plated layer 131 may be different from the area of the second plated layer 132. For example, the area of the first plated layer 131 may be larger than the area of the second plated layer 132.

In this case, the first plated layer 131 may be formed to facilitate bonding between the wiring pattern layer and the second plated layer 132. In addition, the second plating layer 132 may be formed to facilitate bonding with a chip. In this case, when plating is performed only once on the wiring pattern layer, the material of the wiring pattern layer may penetrate into the plating layer. In addition, the penetration of the material of the wiring pattern layer may reduce the adhesion between the chip and the plating layer, resulting in adhesive failure. However, in the present invention, the first plating layer is formed in the inner lead region for mounting the chip. Therefore, the penetration of the material of the wiring pattern layer can proceed to the surface of the first plating layer. Thereafter, a second plating layer is further formed on the first plating layer, so that the material of the wiring pattern layer that has penetrated into the first plating layer may not penetrate into the second plating layer. Therefore, only the pure plating layer may be present on the surface of the second plating layer adhered to the chip, so that the adhesion with the chip may be improved.

Referring to fig. 7, the area of the upper wiring pattern layer 120 on the top surface of the second substrate 112 is different from the area of the plating layer 130, and the area of the lower wiring pattern layer 120 on the bottom surface of the first substrate 111 may correspond to the area of the plating layer 130. Accordingly, the pattern design is complicated for the top surface for mounting the chip, and is relatively simple for the bottom surface attached to the panel or the main board as compared with the top surface, so that the process efficiency can be improved. In addition, cracks of the plating layer on the top surface on the outer portion of the substrate when the substrate is bent can be reduced.

The protective layer 140 may be in direct contact with the substrate 110, in direct contact with the wiring pattern layer 120, in direct contact with the first plating layer 131, or in direct contact with the second plating layer 132.

Referring to fig. 3a, a first plating layer 131 may be disposed on the upper and lower wiring pattern layers 120 and 120, a second plating layer 132 may be formed on the first plating layer 131, and a protective layer 140 may be partially disposed on the second plating layer 132.

In addition, referring to fig. 4a, the protective layer 140 may be partially disposed on the upper and lower wiring pattern layers. In addition, the first and second plating layers 131 and 132 may be disposed in regions on the upper and lower wiring pattern layers other than the region where the protective layer is disposed.

In addition, referring to fig. 4b, the first plating 131 may be disposed on the upper and lower wiring pattern layers 120 and 120, and the protective layer 140 may be partially disposed on the first plating 131. The second plating layer 132 may be disposed in an area on the plating layer 131 other than the area where the protective layer 140 is disposed.

The first plating layer 131 contacting the bottom surface of the protective layer 140 may be an alloy layer of copper and tin. The second plating layer 132, which is in contact with the side surface of the protective layer 140, may include pure tin. Therefore, the protective layer can be prevented from being separated due to the formation of the cavity between the protective layer 140 and the first plating layer 131, and whisker formation can be prevented, so that the adhesiveness of the protective layer can be improved. Accordingly, the embodiment may provide an electronic device including two plating layers, thereby improving reliability.

Further, when only the tin plating 131 as a single layer is provided on the upper and lower wiring pattern layers 120 and the protective layer 140 is provided on one tin plating 131, since the tin plating 131 is heated during thermal curing of the protective layer 140, copper may be diffused in the tin plating 131. Therefore, the tin plating layer 131 may be an alloy layer of tin and copper, so that the first chip having the gold bump may not be securely mounted. Therefore, the plating layer 130 according to the embodiment requires the first and second plating layers 131 and 132 in which the tin concentration continuously increases with increasing distance from the substrate.

Referring to fig. 6, the upper wiring pattern layer 120, the central wiring pattern layer 120, and the lower wiring pattern layer 120 may include a plurality of layers. In addition, each of the upper, central, and lower wiring pattern layers 120, 120 may include a first wiring pattern layer 121, a second wiring pattern layer 122, and a third wiring pattern layer 133. In addition, the first plated layer 131 may be provided on at least a partial area of the top surface of the third wiring pattern layer 133.

The first wiring pattern layer 121 may be disposed on the surfaces of the first substrate 111 and the second substrate 112. The first wiring pattern layer 121 may be a metal seed layer for improving adhesion between the substrate 110 and the second wiring pattern 122. In this case, the metal seed layer may be formed by sputtering. The metallic seed layer may comprise nickel and chromium. In other words, the first wiring pattern layer 121 may be an alloy layer of nickel and chromium. Preferably, the first wiring pattern layer 121 may be nickel and chromium in the ratio of nickel: chromium 8: 2 are mixed with each other.

In addition, a second wiring pattern layer 122 and a third wiring pattern layer 123 may be formed on the first wiring pattern layer 121. The second wiring pattern layer 122 may be formed on the first wiring pattern layer 121. The second wiring pattern layer 122 may be formed by sputtering. The second wiring pattern layer 122 may contain copper.

The second wiring pattern layer 122 and the third wiring pattern layer 123 may be formed by processes corresponding to each other or different from each other.

In other words, as described above, the second wiring pattern layer 122 may be formed by sputtering copper at a thickness of 0.1 μm to 0.5 μm. The second wiring pattern layer 122 may be disposed on the surfaces of the first substrate 111 and the second substrate 112. The third wiring pattern layer 123 may be formed by copper plating on the second wiring pattern layer 122. In this case, since the thickness of the second wiring pattern layer 122 is thin, wiring formation for signal transmission may not be efficiently performed, and thus the third wiring pattern layer 123 may be further formed on the second wiring pattern layer 122.

In other words, since the first wiring pattern layer 121 is formed by sputtering, the first wiring pattern layer 121 has excellent adhesion with the substrate 110 or the metal seed layer, however, the manufacturing cost is high and the manufacturing time is long. Therefore, the third wiring pattern layer 123 is formed on the second wiring pattern layer 122 by plating, so that the manufacturing cost can be reduced and the manufacturing time can be shortened.

Meanwhile, a via pattern layer may also be formed in the via hole. In this case, the via pattern layer may include a first via pattern layer V1-2 and a second via pattern layer V1-2.

The first via hole pattern layer V1-2 may be formed on the inner wall of the via hole formed through the first substrate 111 and the second substrate 112. The first via pattern layer V1-2 may be formed on the inner wall of the through-hole to make contact with the first and

second substrates

111 and 112. The first via pattern layer V1-2 may be formed by sputtering. Alternatively, the first via hole pattern layer V1-2 may be formed by electroplating. The first via pattern layer V1-2 may be a metallic seed layer including palladium. In this case, since the first via hole pattern layer V1-2 is thin, the inner side surfaces of the via holes may be spaced apart from each other. The second via pattern layer V1-2 is formed to fill the via. The second via pattern layer V1-2 may be formed by electroplating a metal containing copper. In this case, the second via pattern layer V1-2 may be formed together with the third wiring pattern layer 123 by filling the inside of the via during electroplating of the third wiring pattern layer 123. Accordingly, embodiments may provide a flexible circuit board and an electronic device including the same, which may prevent voids from being formed in through holes and thus may improve reliability.

Referring to fig. 7, a plurality of protective layers 140 may be disposed on the top surface of the second substrate 112. The protective layer may include a first protective layer 141 and a second protective layer 142.

For example, the first protective layer 141 may be partially disposed on the top surface of the second substrate 112, and the upper wiring pattern layer 120 may be disposed on an area other than an area where the protective layer 141 is disposed.

The second protective layer 142 may be disposed on the protective layer 141. The second protective layer 142 may cover the first protective layer 141 and the upper wiring pattern layer 120, and may be disposed in an area larger than the first protective layer 141.

The protective layer 142 may be disposed on a region corresponding to the protective layer 141 while surrounding the top surface of the first protective layer 141. The width of the second protective layer 142 may be greater than the width of the protective layer 141. Accordingly, the bottom surface of the second protective layer 142 may be in contact with the upper wiring pattern layer 120 and the first protective layer 141. Therefore, the second protective layer 142 can alleviate stress concentration at the interface between the first protective layer 141 and the wiring pattern layer 120. Accordingly, film separation or cracks that may occur when the flexible circuit board according to the embodiment is bent may be reduced.

The plating layer 130 constituting the second conductive pattern part CP2 may be disposed in an area other than the area where the second protective layer 142 is disposed. In detail, the first plating layer 131 is disposed on the upper wiring pattern layer 120 in an area other than an area where the second protective layer 142 is disposed, and the second plating layer 132 may be sequentially disposed on the first plating layer 131.

The lower wiring pattern layer 120 may be disposed on the bottom surface of the first substrate 111. The plating layer 130 may be disposed on the lower wiring pattern layer 120. The protective layer 140 may be partially disposed on the plating layer 130.

Meanwhile, the first substrate 111 and the second substrate 112 may have different thicknesses from each other.

The first substrate 111 may be a flexible substrate. Accordingly, the first substrate 111 may be partially bent. In other words, the first substrate 111 may include a flexible plastic. For example, the first substrate 111 may be a Polyimide (PI) substrate. However, the embodiment is not limited thereto, and the first substrate 111 may be a substrate formed of a polymer material such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN). Accordingly, the flexible circuit board including the first substrate 111 may be used for various electronic devices having a bent display device. For example, since the flexible circuit board including the first substrate 111 has excellent flexibility, the flexible circuit board including the first substrate 111 may be suitable for mounting a semiconductor chip of a wearable electronic device. In detail, the embodiments may be applicable to an electronic device including a bent display.

The first substrate 111 may be an insulating substrate. In other words, the first substrate 111 may be an insulating substrate for supporting various wiring patterns.

The first substrate 111 may have a thickness of 5 μm to 75 μm. For example, the first substrate 111 may have a thickness of 10 μm to 50 μm. For example, the first substrate 111 may have a thickness of 30 μm to 40 μm.

The second substrate 112 may be disposed on the first substrate 111. In this case, the second substrate 112 may be disposed on the first substrate 111 to cover a portion of the third conductive pattern part CP3 disposed on the first substrate 111. Preferably, the second substrate 112 may have an opening exposing at least a portion of an upper region of the first substrate 111. In this case, the opening may form the first opening region OA1 together with the upper protective layer.

In this case, the second substrate 112 may be formed of liquid Polyimide (PI). In other words,

the first substrate 111 may serve as a core, and the second substrate 112 may be supported by the first substrate 111 and formed by coating liquid polyimide on the first substrate 111. In this case, the thickness of the second substrate 112 may be different from that of the first substrate 111. For example, the thickness of the second substrate 112 may be less than

The thickness of the first substrate 111. In this case, the first substrate 111 and the second substrate 112 may constitute the substrate 110. In this case, the liquid polyimide is applied after the first and third conductive pattern parts CP1 and CP3 are patterned on the surface of the first substrate 111. In this case, the liquid polyimide may have a uniform thickness according to the thickness of the support portion on the lower portion. Therefore, the temperature of the molten metal is controlled,

the first substrate 111 has a prescribed thickness to serve as a support portion for forming the second substrate 112, and the first substrate 111 may serve as a support, and thus the second substrate 112 may have a thickness smaller than that of the first substrate 111. Therefore, the material cost can be reduced.

The second substrate 112 may have a thickness of 2 μm to 75 μm. For example, the first substrate 111 may have a thickness of 5 μm to 50 μm.

In the case where the second substrate 112 is less than 2 μm, the third conductive pattern part CP3 may be exposed, or cracks may be generated in forming the second substrate 112 due to the height of the third conductive pattern part CP 3. Meanwhile, when the second substrate 112 is greater than 75 μm, the total thickness of the substrates may become thick, and it may take a long time to form the through-holes in the second substrate 112, so that process efficiency may be reduced.

Hereinafter, a connection relationship between the first chip C1, the second chip C2, the display panel 30, and the main board 40 mounted on the multi-layer flexible printed circuit board 100 according to the embodiment will be described with reference to fig. 3a, 3b, 4a, 4b, 5a, and 5 b.

The multi-layer flexible circuit board 100 according to the embodiment may include: a substrate 100 including a first substrate 111 and a second substrate 112 having a through-hole; a lower wiring pattern layer 120 disposed on the bottom surface of the first substrate 111; an upper wiring pattern layer 120 disposed on the top surface of the second substrate 112; a central wiring pattern layer 120 provided between the first substrate 111 and the second substrate 112; a first plating layer 131 provided on the wiring pattern layer 120; a second plated layer 132 disposed on the first plated layer 131; and a protective layer 140 partially disposed on the second plating layer 132.

In this case, the region where the protective layer 140 is disposed on the first and

second substrates

111 and 112 may be the protective part PP. In addition, the first and second conductive pattern parts CP1 and CP2 may be exposed to the outside in an area other than the protection part PP. In other words, in an opening region of the protective layer or a region where the protective part is not provided on the first and second conductive pattern parts, the first and second conductive pattern parts CP1 and CP2 may be electrically connected to the second chip C2, the display panel 30, and the main board 40, directly or indirectly.

In addition, as described above, the second substrate 112 may have an opening exposing a region to which the first chip C1 is attached from the upper region of the first substrate 111. Further, the opening may vertically overlap with the opening region of the protective layer. Therefore, the region to which the first chip C1 is attached from the upper region of the first substrate 111 may be exposed through the opening of the second substrate 112 and the opening region of the protective layer. In addition, in a region where the second substrate 112 and the protective layer are not disposed, the third conductive pattern part CP3 may be directly connected to the first chip C1.

In other words, in the multi-layer flexible circuit board of the embodiment, the inner lead pattern part connected to the first chip C1 and the inner lead pattern part connected to the at least one second chip C2 may be disposed on different layers. In this case, the first chip C1 may have more terminals than the second chip C2. In other words, a plurality of chips may be disposed on the multi-layer flexible printed circuit board. In this case, a first chip having the largest number of terminals among the chips may be disposed on the first substrate 111, and at least one second chip other than the first chip may be disposed on the second substrate 112. Preferably, the first chip C1 may be a driving IC chip. In addition, the at least one second chip C2 may be one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor.

More preferably, a plurality of second chips may be disposed on the second substrate 112. In this case, the total number of terminals of the first chip C1 disposed on the first substrate 111 may be greater than the total number of terminals of the second chip disposed on the second substrate 112. As described above, in the present invention, the first chip C1 having the largest number of terminals is disposed on the first substrate 111, and thus the overlapping arrangement of the channel wirings formed between the first substrate 111 and the second substrate 112 can be minimized. In addition, since the first chip C1 having the largest number of terminals is formed on the first substrate 111, the number of through holes formed to connect the first chip C1 may be minimized, and thus process efficiency may be improved. Further, since the first chip C1 having the largest number of terminals is formed on the first substrate 111, the first inner leads and the first extended portions (third conductive pattern portions) occupying the largest number of inner leads and extended portions are formed in the central wiring pattern layer, so that design autonomy of the upper and lower wiring pattern layers can be increased.

Meanwhile, the lead pattern part and the test pattern part of the multi-layer flexible circuit board according to the embodiment may not overlap the protection part. In other words, the lead pattern part and the test pattern part may refer to the first conductive pattern part CP1, the second conductive pattern part CP2, and the third conductive pattern part CP3 located in the opening area not covered by the protective layer, and may be classified into the lead pattern part and the test pattern part according to their functions.

The lead pattern portion may refer to a conductive pattern portion for connecting the first chip, the second chip, the display panel, or the main board.

The test pattern part may refer to a conductive pattern part for inspecting a defective product of the flexible circuit board and the chip package including the flexible circuit board according to the embodiment.

The lead pattern part may be divided into an inner lead pattern part and an outer lead pattern part according to its position. One region of the third conductive pattern part CP3 relatively close to the first chip C1 and not overlapping with the protective layer may be denoted as a first inner lead pattern part. One region of the second conductive pattern part CP2 relatively close to the second chip C2 and not overlapping with the protective layer may be denoted as a second inner lead pattern part. One region of the first conductive pattern part CP1 relatively distant from the first and second chips C1 and C2 and not overlapping the protective layer may be denoted as an outer lead pattern part.

The multi-layer flexible printed circuit board 100 according to the embodiment may include a first inner lead pattern part I1 and a second inner lead pattern part I2. The first inner lead pattern part I1 may be a part of the third conductive pattern part CP3 disposed on the first substrate 111. In addition, the second inner lead pattern part I2 may be a part of the second conductive pattern part CP2 disposed on the second substrate 112.

In addition, the first inner lead pattern part I1 may include a first sub-first inner lead pattern part I1a, a second sub-first inner lead pattern part I1b, and a third sub-first inner lead pattern part I1 c.

In addition, the second inner lead pattern part I2 may include a first sub-second inner lead pattern part I2a, a second sub-second inner lead pattern part I2b, a third sub-second inner lead pattern part I3a, and a fourth sub-second inner lead pattern part I3 b. In this case, the number of the second inner lead patterns I2 may correspond to the number of the second chips C2 disposed on the second substrate 112. In other words, as the number of the second chips C2 disposed on the second substrate 112 increases, the number of the second inner lead pattern sections I2 may increase.

In addition, the multi-layer flexible printed circuit board 100 according to the embodiment may include an outer lead pattern part O1. In this case, the outer lead pattern part O1 may include a first sub-first outer lead pattern part O1a and a second sub-first outer lead pattern part O1 b. The first sub-first outer lead pattern part O1a may be a lead pattern part to which one of the display panel and the main board is connected, and the second sub-first outer lead pattern part O1b may be a lead pattern part to which the remaining one of the display panel and the main board is connected.

In this case, as shown in fig. 3a, 3b, 4a and 4b, both the first sub-first outer lead pattern O1a and the second sub-first outer lead pattern O1b may be provided on the bottom surface of the first substrate 111. In other words, both the display panel 30 and the main board 40 may be connected below the first substrate 111.

Alternatively, as shown in fig. 5a, both the first sub-first outer lead pattern part O1a and the second sub-first outer lead pattern part O1b may be provided on the top surface of the second substrate 112. In other words, both the display panel 30 and the main board 40 can be connected above the second substrate 112.

Alternatively, as shown in fig. 5b, the first sub-first outer lead pattern part O1a may be disposed on the bottom surface of the first substrate 111. In addition, the second sub-first outer lead pattern part O1b may be disposed on the top surface of the second substrate 112. In other words, the display panel 30 may be connected below the first substrate 111, and the main board 40 may be connected above the second substrate 112.

In addition, although not shown in the drawings, at least a portion of the third conductive pattern part CP3 disposed on the top surface of the first substrate 111 may form at least one of the first sub-first outer lead pattern part O1a and the second sub-first outer lead pattern part O1 b. Accordingly, at least one of the display panel 30 and the main board 40 may be connected between the first substrate 111 and the second substrate 112.

Meanwhile, when the first chip C1 and the second chip C2 are disposed on the top surface of the first substrate 111 and the top surface of the second substrate 112, respectively, among the plurality of arrangements of the display panel 30 and the main board 40, the arrangement shown in fig. 3b is most preferable. The following description will therefore focus on the arrangement shown in fig. 3 b.

In addition, the multi-layered flexible printed circuit board 100 according to the embodiment may include a first test pattern part T1 and a second test pattern part T2.

The first inner lead pattern part I1 may be disposed on the first substrate 111 of the multi-layer flexible printed circuit board according to the embodiment. In addition, the second inner lead pattern part I2 may be disposed on the second substrate 112. In addition, the first outer lead pattern part O1 may be disposed under the first substrate 111. In addition, the first and second test pattern parts T1 and T2 may be further disposed under the first substrate 111.

The first chip C1 may be attached to the first inner lead pattern part I1 of the multi-layer flexible printed circuit board 100 according to the embodiment through the first connection part 70. In other words, the first chip C1 may be connected to the first sub-first inner lead pattern part I1a, the second sub-first inner lead pattern part I1b, and the third sub-first inner lead pattern part I1C through the first connection 70.

The first connection part 70 may include a first sub-first connection part 71, a second sub-first connection part 72, and a third sub-first connection part 73 according to the position and/or function thereof.

The first chip C1 disposed on the first substrate 111 of the multi-layer flexible circuit board according to the embodiment may be electrically connected to the first sub-first inner lead pattern part I1a through the first sub-first connection part 71.

The first sub-first inner lead pattern I1a may transmit an electrical signal to the first via hole V1 along the top surface of the first substrate 111. In addition, the first via hole V1 may be electrically connected to the first sub-first outer lead pattern part O1 a. In other words, the first sub-first inner lead pattern portion I1a may exchange signals with the first sub-first outer lead pattern portion O1 a.

Meanwhile, the display panel 30 may be connected to the first sub-first outer lead pattern part O1a through the adhesive layer 50. Accordingly, a signal transmitted from the first chip may be transmitted to the display panel 30 via the first sub-first inner lead pattern part I1a and the first sub-first outer lead pattern part O1 a.

In addition, the first chip C1 may be electrically connected to the second sub-first inner lead pattern part I2 through the second sub-first connection part 72.

The second sub-first inner lead pattern part I1b disposed on the top surface of the first substrate 111 may transmit an electrical signal to the first test pattern part T1 adjacent to the second through hole V2 along the bottom surface of the first substrate 111 through the conductive material filled in the second through hole V2 disposed under the second sub-first inner lead pattern part I1 b.

The first test pattern part T1 may check the malfunction of the electrical signal that may be transmitted through the second via V2. For example, the accuracy of the signal transmitted to the second sub-first inner lead pattern part I1b may be confirmed through the first test pattern part T1. In detail, when a voltage or a current is measured at the first test pattern part T1, the occurrence or the position of a short circuit or an electrical short circuit of the conductive pattern part disposed between the first chip and the display panel may be confirmed, so that the reliability of the product may be improved.

In addition, the second sub-first inner lead pattern I1b disposed on the top surface of the first substrate 111 may be electrically connected to the second sub-first outer lead pattern O1b along the bottom surface of the first substrate 111 by the conductive material filled in the third through hole V3.

Meanwhile, the main board 40 may be connected to the second sub-first outer lead pattern portion O1b through an adhesive layer 50. Accordingly, a signal transmitted from the first chip may be transmitted to the main board 40 via the second sub-first inner lead pattern part I1b and the second sub-first outer lead pattern part O1 b.

According to an embodiment, the first chip C1 may be electrically connected to the third sub-first inner lead pattern part I1C through the third sub-first connection part 73.

The third sub-first inner lead pattern I1c disposed on the top surface of the first substrate 111 may be connected to the first sub-second inner lead pattern I2a or the third sub-second inner lead pattern I3a by a metal material filled in the fourth through hole V4 or a metal material filled in the fifth through hole. Accordingly, the first chip C1 may be electrically connected to the at least one second chip C2 through the third sub-first inner lead pattern I1C.

The second test pattern part T2 may check the malfunction of the electrical signal that may be transmitted through the third via V3. For example, the accuracy of the signal transmitted to the second sub-first outer lead pattern part O1b may be confirmed through the second test pattern part T2. In detail, when a voltage or a current is measured at the second test pattern part T2, the occurrence or the position of a short circuit or an electrical short circuit of the conductive pattern part disposed between the first chip and the main board 40 may be confirmed, so that the reliability of the product may be improved.

Meanwhile, the first sub-second chip C2a may be connected to the first sub-second inner lead pattern part I2a through the first sub-second connection part 81. In addition, the first sub-second chip C2a may be connected to the second sub-second inner lead pattern part I2b through the second sub-second connection part 82. In addition, the second sub-second chip C2b may be connected to the third sub-second inner lead pattern part I3a through the first sub-third connection part 91. In addition, the second sub-second chip C2b may be connected to the fourth sub-second inner lead pattern part I3b through the second sub-third connection part 92.

In addition, the second sub-first outer lead pattern part 01b may be connected to the second sub-second inner lead pattern part I2b through the third and fourth through holes V3 and V4. In addition, the second sub-first outer lead pattern O1b may be connected to the fourth sub-second inner lead pattern I3b through the fifth and sixth through holes V5 and V6.

Meanwhile, hereinafter, a manufacturing process of a chip package including the multi-layer flexible circuit board as described above will be described.

First, the first substrate 111, the second substrate 112, and the conductive pattern part CP and the protective layer 140 are arranged to prepare a multi-layer flexible printed circuit board as shown in fig. 3 a.

In this case, the protective layer 140 may include the first opening region OA1 and the second opening region OA 2. In addition, the first opening region OA1 may be an opening vertically overlapping with an opening formed in the second substrate 112. Accordingly, at least a portion of the third conductive pattern part disposed on the top surface of the first substrate 111 may be exposed.

In other words, the second plating layer 132 constituting the third conductive pattern part CP3 provided on the first substrate may be exposed in the opening. In this case, the opening may be referred to as a first opening region OA 1. Hereinafter, for convenience of explanation, a portion exposed through the opening of the second substrate 112 is referred to as a first opening region OA 1. In addition, the second plating layer 132 of the second conductive pattern part CP2 disposed on the second substrate 112 may be exposed in the second opening area OA 2.

A manufacturing process of a chip package after manufacturing the multi-layer flexible circuit board as described above will be described by a first step of arranging the first chip C1 in the multi-layer flexible circuit board and a second step of arranging the second chip C2 in the multi-layer flexible circuit board.

First, the arrangement of the first chip C1 on the flexible circuit board according to the embodiment will be described.

The first connection part 70 may be disposed in the first opening area OA1 of the flexible circuit board according to the embodiment.

The second plating layer 132 of the third conductive pattern part CP3 in the first opening area OA1 may have a tin (Sn) content of 50 atomic% or more. In the first opening area OA1, the second plated layer 132 of the third conductive pattern part CP3 may include a pure tin layer. For example, the second plating layer 132 of the third conductive pattern part CP3 in the first opening area OA1 may have a tin (Sn) content of 70 atomic% or more. For example, the second plating layer 132 of the third conductive pattern part CP3 in the first opening area OA1 may have a tin (Sn) content of 90 atomic% or more. For example, the tin (Sn) content of the second plating layer 132 of the third conductive pattern part CP3 in the first opening area OA1 may be 95 atomic% or more. For example, the second plating layer 132 of the third conductive pattern part CP3 in the first opening area OA1 may have a tin (Sn) content of 98 atomic% or more. When the tin (Sn) content of the second plating layer 132 of the third conductive pattern part CP3 in the first opening region OA1 is less than 50 atomic%, it may be difficult to connect the second plating layer 132 of the third conductive pattern part CP3 and the first chip C1 through the connection part 70. In detail, when the tin (Sn) content of the second plating layer 132 of the third conductive pattern part CP3 in the first opening area OA1 is less than 50 atomic%, it may be difficult to perform connection through bonding of the second plating layer 132 and the first chip C1 through the connection part 70.

The first connection portion 70 may include gold (Au). The first connection portion 70 may be a gold projection.

In order to dispose one first chip C1 on the flexible circuit board according to the embodiment, a plurality of first connection portions 70 may be provided between the first chip C1 and the second plating layer 132 of the third conductive pattern part CP 3.

Since the second plating layer 132 of the third conductive pattern part CP3 in the first opening area OA1 has a tin (Sn) content of 50 atomic% or more, the second plating layer 132 may have excellent adhesion characteristics with the first connection part 70 including gold (Au). The chip package including the multi-layer flexible printed circuit board according to the embodiment may have excellent electrical connection between the first chip C1 and the conductive pattern through the first connection part 70, so that reliability may be improved.

Next, the arrangement of the second chip C2 on the multilayer flexible circuit board according to the embodiment will be described.

The second connection part 80 is disposed in the second opening area OA2 of the multi-layered flexible printed circuit board according to the embodiment.

In order to dispose the second chip C2 on the multi-layer flexible circuit board according to the embodiment, heat may be selectively supplied only to a portion corresponding to the region where the second connection portion 80 is disposed through a mask (not shown). In detail, the embodiment may selectively supply heat to the region where the second connection part 80 for connecting the second chip C2 is disposed through a selective reflow process.

In detail, in the multi-layer flexible printed circuit board according to the embodiment, even when the second chip C2 is disposed after the first chip C1 is mounted, partial heat supply may be performed through a selective reflow process.

In other words, in the manufacturing process according to the embodiment, the first opening regions OA may be prevented from being exposed to heat by the mask. Accordingly, the second plating layer disposed in the first opening area OA may be prevented from being denatured from the pure tin layer to the alloy layer of tin and copper due to heat supply. Therefore, even when the first chip C1 and the second chip C2, which are different from each other, are mounted on one multi-layer flexible printed circuit board 100, the tin (Sn) content of the second plating layer 132 in the first opening region may be 50 atomic% or more, and thus the assembly of the driving IC chip may be excellent.

Meanwhile, the holes of the mask may be disposed in the region corresponding to the second opening region OA 2. Therefore, the plating layer exposed by heat in the second opening areas OA2 may be denatured into an alloy layer of tin and copper.

In detail, a portion of the second plating layer 132 in the second opening regions OA2 exposed due to heat through the holes of the mask may undergo further tin/copper diffusion. Accordingly, the content of tin (Sn) in the second plating layer 132 may be less than 50 atomic% in the second opening area OA 2. In the second opening regions OA2, the second plating layer 132 may be an alloy layer of copper (Cu) and tin (Sn).

The second connection portion 80 may include a metal other than gold (Au). Therefore, even when the second plating layer 132 disposed under the second connection portion 80 is not a pure tin layer, the second connection portion 80 may have excellent assembly performance with the second chip C2. In addition, since the second connection part 80 may include a metal other than gold (Au), the manufacturing cost may be reduced.

For example, the second connection portion 80 may include at least one of copper (Cu), tin (Sn), aluminum (Al), zinc (Zn), indium (In), lead (Pb), antimony (Sb), bismuth (bi), silver (Ag), and nickel (Ni).

The second connection portion 80 may be a solder bump. The second connection portion 80 may be a solder ball. The solder balls may melt at the temperature of the reflow process.

In order to dispose one second chip C2 on the flexible circuit board according to the embodiment, a plurality of second connection portions 80 may be provided between the second chip C2 and the second plating layer 132.

At the temperature of the reflow process, the second chip C2 may have excellent bondability with the second plating layer 132 on the second opening region OA2 through the second connection parts 80.

In the multi-layer flexible printed circuit board according to the embodiment, the connection of the first chip C1 may be excellent through the first connection part 70 in the first opening region, while the connection of the second chip C2 may be excellent through the second connection part 80 in the second opening region.

The flexible printed circuit board according to the embodiment may include plated layers having different Sn contents in the first and second opening regions OA1 and OA2, and thus, the assembly performance of the first chip C1 may be excellent, and at the same time, the assembly performance of the second chip C2 may be excellent.

As in the comparative example, when the first chip is mounted on the first printed circuit board, the second chip is mounted on the second printed circuit board, and the first printed circuit board having the first chip and the second printed circuit board having the second chip are bonded to each other by the adhesive layer, problems due to thermal denaturation of the first chip may not occur.

However, when the first chip and the second chip different from each other are mounted on one substrate as in the embodiment, the second plating layer is denatured by heat in the first opening region of the protective layer to connect the first chip, and therefore there is such a problem that it is difficult to assemble the first chip through the first connection portion.

To solve such a problem, the inventors sequentially disposed the first chip and the second chip on the multi-layer flexible circuit board through a selective reflow process. Accordingly, in a multi-layered flexible printed circuit board and a chip package including the same, the tin content of the second plating layer in the first open area may be different from the tin content of the second plating layer in the second open area. Therefore, in the chip package including the multi-layer flexible circuit board according to the embodiment, excellent electrical connection of the first chip C1 and the second chip C2, which are different from each other, can be achieved.

The second plating layer including the pure tin layer in the first opening region may enable the first chip as the driving IC chip to be stably mounted through the first connection portion including gold (Au). Further, the second plating layer including the alloy layer of copper and tin in the second opening region may enable a second chip, which is at least one of a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor, to be stably mounted through the second connection portion including a metal other than gold (Au).

Therefore, in the multi-layer flexible printed circuit board and the chip package including the same according to the embodiment, different types of the first chip and the second chip may be mounted on one flexible printed circuit board with excellent yield.

In addition, a plurality of conventional printed circuit boards may be replaced with one multi-layer flexible circuit board, and thus the multi-layer flexible circuit board for connecting the display panel and the main board may be minimized and may be thin.

Therefore, in the electronic device including the multilayer flexible circuit board of the embodiment, various functional units such as a camera module, an iris recognition module, and the like can be easily mounted. In addition, in an electronic device including the multilayer flexible circuit board of the embodiment, a battery space can be enlarged.

In addition, the multi-layer flexible circuit board may be manufactured through a roll-to-roll process, and the chip may be mounted on the multi-layer flexible circuit board through a selective reflow process, so that convenience of a manufacturing process and manufacturing yield may be improved.

In the multi-layer flexible printed circuit board according to the embodiment, the display panel 30 may be disposed on the other surface of the first substrate 111 opposite to the one surface on which the first chip C1 is disposed, so that a degree of freedom in design may be improved. In addition, since the display panel is disposed on the other surface opposite to the one surface on which the second chip is mounted, heat dissipation can be effectively performed. Therefore, the reliability of the flexible circuit board according to the embodiment may be improved.

In addition, embodiments provide the multi-layer flexible circuit board so that signals according to high resolution can be efficiently transmitted.

Further, in an embodiment, in a multilayer structure including the first substrate 111 and the second substrate 112, the second substrate 112 may be formed to expose at least a portion of an upper region of the first substrate 111. In other words, the second substrate 112 may have an opening exposing at least a portion of the upper region of the first substrate 111. In addition, the first chip C1 may be disposed on the first substrate 111 exposed through the opening of the second substrate 112, and at least one second chip C2 is disposed on the second substrate 112. In this case, the first chip C1 is a chip having the largest number of terminals among a plurality of chips provided on the multilayer flexible printed circuit board. Preferably, the first chip C1 may be a driving IC chip. In addition, the second chip C2 having a relatively small number of terminals may be disposed on the second substrate 112. Therefore, in the embodiment, the number of connection wirings (including a wiring pattern layer and a via) for connecting the first chip C1 may be minimized, and thus the volume of the flexible circuit board may be minimized. In addition, in the embodiment, most of the design portion of the first chip C1, which occupies the largest part of the wiring design of the double-sided flexible circuit board, may be applied as it is, and thus, the design time may be minimized.

Fig. 8 is a plan view illustrating the first substrate 111 of fig. 3a, and fig. 9 is a bottom view illustrating the first substrate 111 of fig. 3 a.

Fig. 8 and 9 are top and bottom views illustrating the first substrate 111 in the multi-layer flexible circuit board according to the embodiment, focusing on the third conductive pattern part for arranging the first chip.

Referring to fig. 8 and 9, the multi-layer flexible circuit board 100 of the embodiment may be provided at both outer sides thereof with a notch hole (recess) formed in a longitudinal direction of the multi-layer flexible circuit board 100 for convenience of manufacturing or processing. Accordingly, the first substrate 111 may be wound or unwound through the perforation in a roll-to-roll scheme.

The first substrate 111 may be defined as an inner region IR and an outer region OR based on a cut portion shown by a dotted line.

In the inner region IR of the first substrate 111, a conductive pattern part for connecting the first chip, the display panel, and the main board may be provided. Meanwhile, a conductive pattern part for connecting the second chip may be disposed in the inner region IR of the top surface of the second substrate 112.

Since a portion forming the perforation of the first substrate 111 may be cut off and a chip may be disposed on the first substrate, the first substrate 111 may be processed into a chip package including the flexible circuit board 100 and an electronic device including the chip package.

Referring to fig. 8, in the top surface of the flexible circuit board 100, the first sub-first inner lead pattern part I1a, the second sub-first inner lead pattern part I1b, and the third sub-first inner lead pattern part I1c, which are one region of the third conductive pattern part CP3, may be exposed to the outside through the first opening region OA1 of the overcoat layer 140 and the opening of the second substrate 112.

Referring to fig. 9, in the bottom surface of the flexible circuit board 100, the first sub-first outer lead pattern part O1a and the second sub-first outer lead pattern part O1b, which are one region of the first conductive pattern part CP1, may be exposed to the outside through the third opening region OA3 of the overcoat layer 140.

Referring to fig. 3b and 10a and 10b, 11a and 11b, 12a and 12b, 13a and 13b, and fig. 14, a chip package including a first chip C1 and a second chip C2 on a multi-layer flexible circuit board 100 according to an embodiment will be described in detail.

Fig. 10a and 10b are plan views schematically showing a chip package including a multilayer flexible circuit board 100 on which a first chip and a second chip are mounted according to an embodiment.

Referring to fig. 10a and 10b, the multi-layer flexible printed circuit board 100 according to the embodiment may include arranging the first chip C1 and the second chip C2 on different surfaces of a plurality of substrates. In this case, the first chip C1 and the second chip C2 are shown to be disposed on the same layer in fig. 10a and 10b, since the first chip C1 is shown as the first chip C1 exposed to the outside through the opening of the second substrate 112 and the first opening region of the protective layer, as viewed from the top.

In the three-layer flexible circuit board 100 according to the embodiment, the length in the transverse direction (x-axis direction) may be greater than the length in the longitudinal direction (y-axis direction). In other words, the three-layer flexible circuit board 100 according to the embodiment may include two long sides in the transverse direction and two short sides in the longitudinal direction.

Each of the first chip C1 and the second chip C2 may have a length in the lateral direction (x-axis direction) that is greater than a length in the longitudinal direction (y-axis direction). In other words, the first chip C1 and the second chip C2 may include two long sides in the lateral direction and two short sides in the longitudinal direction.

The long side of the three-layered flexible printed circuit board 100 according to the embodiment may be parallel to each of the long side of the first chip C1 and the long side of the second chip C2, so that the chips may be efficiently disposed on one multi-layered flexible printed circuit board 100.

The lateral length (long side) of the first chip C1 may be greater than the lateral length (long side) of the second chip C2. The longitudinal length (short side) of the first chip C1 may be smaller than the longitudinal length (short side) of the second chip C2. Referring to fig. 10a, the second chip C2 may be disposed on an upper portion of the second substrate so as not to vertically overlap the first chip C1.

The first chip C1 may be a driving IC chip. The second chip C2 may include: a second chip C2a selected from one of a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor; and a second chip C2b selected from another one of the diode chip, the power IC chip, the touch sensor IC chip, the MLCC chip, the BGA chip, and the chip capacitor.

Referring to fig. 11a, 11b, 12a, 12b, 13a, 13b, and fig. 14, a manufacturing process of a chip package including a multilayer flexible circuit board according to an embodiment will be described.

Fig. 11a and 11b are plan views illustrating a multi-layer flexible circuit board 100 according to an embodiment.

Referring to fig. 11a and 11b, the protective layer 140 disposed on one surface of the multi-layer flexible printed circuit board 100 may include a plurality of holes. In other words, the protective layer 140 may include a plurality of open regions. In this case, it is shown in the following drawings that the second conductive pattern part CP2 and the third conductive pattern part CP3 are formed on different layers so as not to overlap with each other in the vertical direction. However, the drawings are provided only for convenience of explanation of each conductive pattern part, and thus the second and third conductive pattern parts CP2 and CP3 may be substantially disposed such that at least a portion of the second and third conductive pattern parts CP2 and CP3 overlap each other in a vertical direction. In addition, the second and third conductive pattern parts CP2 and CP3 may be electrically connected to each other through a metal material filled in the via hole. Hereinafter, for convenience of explanation, only a portion of the second and third conductive pattern parts CP2 and CP3 is shown in the drawings for explanation.

The first opening area OA1 of the protective layer may be an area exposed so as to be connected to the first connection portion 70. The third conductive pattern part CP3 disposed on the first substrate 111 exposed in the first opening area OA1 of the protective layer may include a pure plating layer on a surface thereof facing the first connection part. In other words, the tin content of the second plating layer included in the third conductive pattern part CP3 in the first opening area OA1 of the protective layer may be 50 atomic% or more.

The second opening region OA2 of the protective layer may be a region exposed so as to be connected to the second connection part 80. The second conductive pattern part CP2 exposed in the second opening region OA2 of the protective layer may include an alloy layer of copper and tin on its surface facing the second connection part. In other words, the tin content of the second plating layer included in the second conductive pattern part CP2 in the second opening region OA2 of the protective layer may be less than 50 atomic%.

The first opening area OA1 may be disposed on an area vertically overlapping the opening of the second substrate 112, and thus, the first opening area OA1 may be an area for connecting the first chip to the first substrate 111. The third conductive pattern part CP3 and the first sub-first inner lead pattern part I1a may have widths corresponding to each other or widths different from each other. For example, the width W1 of the third conductive pattern part CP3 may correspond to the width W2 of the first sub-first inner lead pattern part I1 a. For example, the width W1 of the third conductive pattern part CP3 may be greater than the width W2 of the first sub-first inner lead pattern part I1 a. In detail, a difference between the width W1 of the first extension pattern part of the third conductive pattern part CP3 and the width W2 of the first sub-first inner lead pattern part I1 may be within 20%. Accordingly, a plurality of third conductive pattern parts CP3 may be formed in the intermediate pattern layer.

The first sub-first inner lead pattern part I1a and the third sub-first inner lead pattern part I1c extending toward the inside of the first opening region OA1 may have widths corresponding to each other.

The widths of the first extension pattern parts of the third conductive pattern part CP3 extending from the first opening region OA1 toward the outside of the substrate may correspond to each other for each region. Therefore, the width of the first extension pattern portion is set such that a first chip having a fine line width and requiring a large number of first connection portions is formed in the middle pattern layer, and a second chip having a large line width and requiring a small number of second connection portions is formed in the upper pattern layer, so that both the first chip and the second chip can be mounted on one multilayer flexible printed circuit board 100. In this case, the fine line width may refer to the following case: the line width of one of the first sub-first and third sub-first inner lead patterns I1a and I1c is smaller than the line width of one of the second and third inner lead patterns I2 and I3. Meanwhile, a large line width may refer to the following case: the line width of one of the second and third inner lead pattern parts I2 and I3 is relatively greater than the line width of the first inner lead pattern part I1.

The multi-layered flexible printed circuit board 100 of the embodiment may include a plurality of second opening regions OA2a and OA2b for connecting different types of second chips C2a and C2b, respectively.

A second opening region OA2a may be a region for connecting a second chip C2 a. The width W3 of the second inner lead pattern portion I2 disposed in the second opening region OA2 may be greater than the width W4 of the second extension pattern portion (preferably, the extension pattern portion of the second conductive pattern portion) of the second conductive pattern portion CP 2. In detail, the width W3 of the second inner lead pattern portion I2 may be at least 1.5times the width W4 of the extension pattern portion of the second conductive pattern portion CP2 (the width W3 of the second inner lead pattern portion I2a y be at least 1.5time header and the width W4 of the extension pattern portion of the second conductive pattern portion CP 2). In other words, the second conductive pattern part CP2 may include the second inner lead pattern part I2, the third inner lead pattern part I3, and an extension pattern part.

In other words, since the third conductive pattern part having the plurality of leads connected to the first chip C1 is formed in the middle pattern layer, the second inner lead pattern part of the second chip C2 having a degree of freedom of design connected to the upper pattern layer may be large, so that the connection between the second chip C2 and the flexible circuit board may be facilitated. In addition, the width W3 of the second inner lead pattern I2 is greater than the width W4 of the extension pattern portion of the second conductive pattern portion CP2, so that the degree of freedom in design can be increased when forming the extension pattern portion having a length relatively greater than that of the second inner lead pattern portion in the upper pattern layer.

The other second opening region OA2b may be a region for connecting another second chip C2 b. The second conductive pattern part CP2 extending from the third inner lead pattern part I3 disposed in the second opening region OA2b toward the outside of the substrate may have different widths. For example, the width W5 of the third inner lead pattern part I3 may be greater than the width W6 of the third conductive pattern part CP 3. In detail, the width W5 of the third inner lead pattern part I3 may be at least 1.5times the width W6 of the third conductive pattern part CP 3.

At least one of the width W3 of the second inner lead pattern part I2 and the width W5 of the third inner lead pattern part I3 exposed through the second opening region may be greater than the width W2 of the first inner lead pattern part I1 exposed through the first opening region. Therefore, the lead pattern portion may be formed to correspond to various sizes/shapes of the first connection portion and the second connection portion, so that a degree of freedom of design may be improved. Further, the first inner lead pattern part set to the maximum number is formed in the intermediate pattern layer, so that the degree of freedom in design can be improved when the relatively small number of the second and third inner lead pattern parts and the extension pattern part of the second conductive pattern part are formed in the upper pattern layer. In other words, the embodiment may include inner lead pattern portions of various sizes and shapes suitable for different types of first and second chips, so that an optimal chip package may be realized.

The shape of the inner lead pattern part disposed under the first chip may be different from the shape of the inner lead pattern part disposed under the second chip. Accordingly, embodiments may include inner lead patterns having different shapes, each of which may have excellent adhesion characteristics with different types of first and second chips. Therefore, in the multilayer flexible printed circuit board according to the embodiment, the bonding characteristics of the first chip and the second chip may be excellent.

In other words, the inner lead pattern portions having different shapes may be an optimum pattern design in which different types of first and second chips are mounted on one substrate to ensure prescribed bonding performance.

The first inner lead pattern part I1 as viewed from the top may be formed in a stripe pattern having a rectangular shape. In detail, the first inner lead pattern part I1 when viewed from the top may be formed to have a stripe pattern having a rectangular shape including a uniform width and extending in one direction. For example, the widths of one end and the other end of the first inner lead pattern part I1 may be the same. Therefore, a large number of terminals of the first chip and the first inner lead can be bonded to each other.

For example, the second or third inner lead pattern part I2 or I3 may be formed as a protrusion pattern having various shapes such as a polygon, a circle, an ellipse, a hammer, a T, an arbitrary shape. In detail, the second or third inner lead pattern part I2 or I3 may be formed as a protrusion pattern having various shapes, for example, a polygon, a circle, an ellipse, a hammer, a T, and an arbitrary shape having a variable width and extending in a direction different from one direction. For example, one end and the other end of at least one of the second and third inner lead patterns I2 and I3 may have different widths. The widths of the other ends of the second and third inner lead patterns I2 and I3, which are distant from the protective layer, may be greater than the width of the end close to the protective layer. However, the embodiment is not limited thereto, and the other ends of the second and third inner lead patterns I2 and I3, which are distant from the protective layer, may have a width smaller than that of the end near the protective layer. Therefore, when a relatively smaller number of terminals than the first chip are bonded to the second inner leads, the terminals and the second inner leads can be bonded in a large space, so that the bonding efficiency can be improved.

For example, when the second chip is an MLCC chip, the inner lead pattern part may have a T shape, such as the second inner lead pattern part I2 of fig. 11 b.

For example, when the second chip is a BGA chip, the inner lead pattern part may have a circular shape, such as the third inner lead pattern part I3 of fig. 11 a. Alternatively, when the second chip is a BGA chip, the inner lead pattern part may have a semicircular shape or a rounded end shape, such as the third inner lead pattern part I3 of fig. 11 b.

In other words, a more efficient design can be ensured to connect the second chip (MLCC, BGA, etc.) having a wider terminal width and a smaller number of terminals than the first chip (drive IC).

The first inner lead pattern part and the first connection part may have the same shape. For example, the first inner lead pattern part and the first connection part may have a rectangular shape when viewed from the top. In this case, the first inner lead pattern part and the first connection part have the same shape means that the first inner lead pattern part and the first connection part have the same polygonal shape when viewed from the top, and may include different sizes.

The shapes of the second inner lead pattern part and the second connection part 80 may be the same as or different from each other. The shapes of the third inner lead pattern part and the third connection part 90 may be the same as or different from each other.

Referring to fig. 11a and 12a, the second inner lead pattern part I2 may have a polygonal shape when viewed from the top, and the second connection part may have a circular shape when viewed from the top. The third inner lead pattern part I3 may have a circular shape when viewed from the top, and the third connection part may have a circular shape.

Referring to fig. 11b and 12b, the second inner lead pattern part I2 may have a polygonal shape when viewed from the top, and the second connection part may have a rectangular shape or an elliptical shape with rounded corners when viewed from the top. The seventh inner lead pattern part I7 may have a long semicircular shape when viewed from the top, and the second connection part may have a circular shape.

The first connection portion 70 may have a shape in which a transverse length and a longitudinal length (aspect ratio) correspond to each other or are different from each other when viewed from the top. For example, the first connection portion 70 may have a square shape in which a lateral length and a longitudinal length (aspect ratio) correspond to each other, or a rectangular shape in which the lateral length and the longitudinal length (aspect ratio) are different from each other, when viewed from the top.

The second connection part 80 may have a shape in which a transverse length and a longitudinal length (aspect ratio) correspond to each other or are different from each other when viewed from the top. For example, the second connection part 80 may have a circular shape in which a lateral length and a longitudinal length (aspect ratio) correspond to each other, or an elliptical shape in which the lateral length and the longitudinal length (aspect ratio) are different from each other, when viewed from the top.

The first pitch P1, which is a spacing between the adjacent third conductive pattern parts CP3, may be smaller than the second pitch P2, which is a spacing between the adjacent second conductive pattern parts CP 2. In this case, the first pitch and the second pitch may refer to an average separation interval between two adjacent conductive pattern portions. Therefore, a portion including a large number of inner leads connected to a chip having a large number of terminals can be formed in the intermediate pattern layer, so that a plurality of chips can be formed on one printed circuit board.

The first pitch P1 may be less than 30 μm. For example, the first pitch may be 5 μm to 25 μm. For example, the first pitch may be 5 μm to 15 μm.

When the first pitch P1 is less than 5 μm, an electrical short may occur between the third conductive patterns connected to the driving IC. When the first pitch P1 is 30 μm or more, in order to form all the third conductive patterns for driving the ICs in the intermediate layer, the length L2 of the flexible circuit board may be increased, so that it may be difficult to secure a space for arranging additional components such as a battery in the electronic device.

The second pitch P2 may be 30 μm or greater. For example, the second pitch may be 30 μm to 500 μm. For example, the second pitch may be 100 μm to 300 μm.

When the second pitch P2 is less than 30 μm, an electrical short may occur between the second conductive patterns connected to the MLCC or the BGA chip. When the second pitch P2 is 300 μm or more, in order to form all the second conductive patterns for chips such as MLCCs or BGAs in an upper layer, the length L2 of the flexible circuit board may be increased, so that it may be difficult to secure a space for arranging additional components such as a battery in an electronic device.

Therefore, signals between the conductive pattern portions connected to each of the first chip and the second chip can be prevented from being interfered, and the accuracy of the signals can be improved.

The planar area of the first inner lead pattern part I1 in the first opening region OA1 may correspond to the first connection part 70 or may be different from the first connection part 70.

The width of the first inner lead pattern part I1 and the width of the first connection part 70 may be the same, or may have a difference within 20%. Therefore, the first inner lead pattern part I1 and the first connection part 70 can be stably mounted. In addition, the adhesion characteristics between the first inner lead pattern part I1 and the first connection part 70 may be improved.

The planar area of one of the inner lead pattern part I2 and the third inner lead pattern part I3 in the second opening region OA2 may correspond to the second connection part 80 or may be different from the second connection part 80.

For example, the width of the second connection portion 80 may be at least 1.5times the width of one of the inner lead pattern portion I2 and the third inner lead pattern portion I3. Therefore, the width of the second connection portion 80 may be set such that the adhesion property between the second connection portion 80 and one of the second and third inner lead patterns I2 and I3 may be improved.

With reference to fig. 12a and 12b, the arrangement of the first connection portion 70 and the second connection portion 80 on the flexible circuit board 100 of the embodiment will be described.

The first connection part 70 may be disposed on the first inner lead pattern part I1 exposed through the first opening region OA 1. For example, the first connection part 70 may cover all or a portion of the top surface of the first inner lead pattern part I1.

The total number of the plurality of first inner lead patterns I1 spaced apart from each other may correspond to the number of the first connections 70.

For example, referring to fig. 13a and 13b, when the number of the plurality of first sub-first inner lead patterns I1a spaced apart from each other is 9 and the number of the plurality of third sub-first inner lead patterns I1c spaced apart from each other is 9, the number of the first connections 70 may be 18, which is the sum of the number of the first sub-first inner lead patterns I1a (i.e., 9) and the number of the third sub-first inner lead patterns I1c spaced apart from each other (i.e., 9).

The second connection 80 may be disposed on each of the second and third inner lead patterns I3 and I3 exposed through the second opening region OA 2. For example, the second connection 80 may cover all or a portion of the top surfaces of the second and third inner lead patterns I2 and I3.

The number of the plurality of second inner lead pattern parts I2 spaced apart from each other may correspond to the number of the second connection parts 80 and the number of the third connection parts 90 provided on the third inner lead pattern part I3.

For example, referring to fig. 13a and 13b, the number of the second inner lead pattern parts I2 spaced apart from each other may be two, and the number of the second connection parts 80 provided on the second inner lead pattern part I2 may be two.

The number of the plurality of third inner lead patterns I3 spaced apart from each other may correspond to the number of the third connection portions 90 provided on the third inner lead pattern I3.

For example, referring to fig. 13a and 13b, the number of the third inner lead patterns I3 spaced apart from each other may be three, and the number of the third connections 90 provided on the third inner lead patterns I3 may be three.

Each of the second and

third connection parts

80 and 90 may be larger than the first connection part 70. Since the width of the second or third inner lead pattern part I2 or I3 exposed through the second opening region is greater than the width of the first inner lead pattern part I1 exposed through the first opening region, each of the second and

third connection parts

80 and 90 may be greater than the first connection part 70.

Referring to fig. 13a and 13b, the arrangement of the first chip C1 and the second chips C2a and C2b on the multilayer flexible printed circuit board 100 of the embodiment will be described.

The first chip C1 may be disposed on the first connection portion 70.

The second chip C2 may be disposed on the second connection portion 80.

In order to prevent problems such as signal interference, a failure such as disconnection, and a failure due to heat, for example, the first chip C1 and the second chip C2 may be spaced apart from each other by a prescribed distance in a vertical direction without overlapping in the vertical direction.

The multi-layer flexible printed circuit board 100 according to the embodiment may implement three layers of conductive pattern portions having a fine pitch, so that the multi-layer flexible printed circuit board 100 may be suitable for an electronic device having a high resolution display unit.

In addition, since the multi-layer flexible printed circuit board 100 according to the embodiment is flexible, small in size, and thin in thickness, the multi-layer flexible printed circuit board 100 may be used for various electronic devices.

For example, referring to fig. 14, the multi-layer flexible printed circuit board 100 according to the embodiment may be used for an edge display because a bezel may be reduced.

For example, referring to fig. 15, the multi-layer flexible printed circuit board 100 according to the embodiment may be included in a bent flexible electronic device. Accordingly, the touch device including the multi-layer flexible printed circuit board 100 may be a flexible touch device. Thus, the user can bend or bend the device by hand. Such a flexible touch window may be applied to a wearable touch screen or the like.

For example, referring to fig. 16, the multi-layer flexible printed circuit board 100 according to the embodiment may be applied to various electronic devices employing a foldable display device. Referring to fig. 16a to 16c, the foldable cover window may be folded in the foldable display device. The foldable display device may be included in various portable electronic products. In detail, the foldable display device may be included in a mobile terminal (mobile phone), a notebook computer (portable computer), or the like. Therefore, the display area of the portable electronic product can be increased, while the size of the device can be reduced during storage or transportation, so that portability can be improved. Therefore, the convenience of the user of the portable electronic product can be improved. However, the embodiment is not limited thereto, and the foldable display device may be used in other electronic products.

Referring to fig. 16a, the foldable display device may include one folding area in the screen area. For example, the foldable display device may have a C-shape when folded. In other words, one end of the foldable display device and the other end opposite to the one end may overlap each other. In this case, the one end and the other end may be close to each other. For example, the one end and the other end may face each other.

Referring to fig. 16b, the foldable display device may include two folding areas in a screen area. For example, the foldable display device may have a G-shape when folded. In other words, one end and the other end opposite to the one end of the foldable display device may overlap each other when the one end and the other end are folded in corresponding directions. In this case, the one end and the other end may be spaced apart from each other. For example, the one end and the other end may be parallel to each other.

Referring to fig. 16c, the foldable display device may include two folding areas in the screen area. For example, the foldable display device may have an S-shape when folded. In other words, one end of the foldable display device and the other end opposite to the one end may be folded in different directions. In this case, the one end and the other end may be spaced apart from each other. For example, the one end and the other end may be parallel to each other.

In addition, although not shown in the drawings, the flexible circuit board 100 according to the embodiment may be applied to a rollable display.

Referring to fig. 17, the multi-layer flexible printed circuit board 100 according to the embodiment may be included in various wearable touch devices including a bent display. Accordingly, an electronic device including the multi-layer flexible printed circuit board 100 according to the embodiment may have a slim, miniaturized, or lightweight structure.

Referring to fig. 18, the multi-layer flexible printed circuit board 100 according to the embodiment may be used for various electronic devices having a display portion, such as TVs, monitors, and notebook computers.

However, the embodiment is not limited thereto, and the flexible circuit board 100 according to the embodiment may be used for various electronic devices having a flat display portion or a bent display portion.

Although embodiments have been described with reference to a number of illustrative embodiments, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various changes and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

Claims

1. A flexible circuit board comprising:

a first substrate;

a second substrate disposed on the first substrate and including an opening;

a first conductive pattern part disposed on a bottom surface of the first substrate;

a second conductive pattern part disposed on a top surface of the second substrate;

a third conductive pattern part disposed between the first substrate and the second substrate; and

an upper protective layer partially disposed on the second conductive pattern part and including a first open region,

wherein the third conductive pattern part includes:

a first inner lead pattern part disposed in the opening of the second substrate; and

a first extension pattern part connected to the first inner lead pattern part, the second conductive pattern part including:

a second inner lead pattern part disposed in the first opening region of the upper protective layer; and

a second extended pattern part connected to the second inner lead pattern part, and

the number of the first inner lead pattern parts is greater than the number of the second inner lead pattern parts.

2. The flexible circuit board of claim 1, wherein the first inner lead pattern portion has a width smaller than a width of the second inner lead pattern portion.

3. The flexible circuit board of claim 1, wherein a width of the first extended pattern portion is smaller than a width of the second extended pattern portion.

4. The flexible circuit board according to claim 2, wherein a pitch between the first inner lead pattern portions is smaller than a pitch between the second inner lead pattern portions.

5. The flexible circuit board of claim 3, wherein a spacing between the first extended pattern portions is smaller than a spacing between the second extended pattern portions.

6. The flexible circuit board according to claim 1, wherein at least one of the first to third conductive pattern parts includes:

a conductive pattern layer; and

a plating layer disposed on the conductive pattern layer and including tin.

7. The flexible circuit board according to claim 6, wherein the conductive pattern layer of at least one of the first to third conductive pattern parts includes:

a first conductive pattern comprising nickel and chromium;

a second conductive pattern disposed on the first conductive pattern and including copper; and

a third conductive pattern disposed on the second conductive pattern and comprising copper.

8. The flexible circuit board of claim 1, further comprising:

at least one first via passing through the first substrate and connecting the first conductive pattern to the third conductive pattern; and

at least one second via passing through the second substrate and connecting the second conductive pattern and the third conductive pattern,

wherein each of the first and second vias comprises:

a first via layer that is provided on an inner wall of a through-hole formed through the first substrate or the second substrate and contains palladium; and

a second via layer disposed in the first via layer to fill the through-holes, and the second via layer includes copper.

9. The flexible circuit board of claim 1, wherein the first substrate has a thickness thicker than a thickness of the second substrate.

10. The flexible circuit board of claim 1, further comprising a lower protective layer disposed partially below the first conductive pattern portion and including a third open area,

wherein the first conductive pattern part includes a first outer lead pattern part and a second outer lead pattern part exposed through the third opening region.

11. The flexible circuit board according to claim 1, wherein the second conductive pattern part further includes a third inner lead pattern part exposed through the second open region of the upper protective layer, and

the total number of the second and third inner lead patterns is smaller than the number of the first inner lead patterns.

12. A chip package comprising a flexible circuit board, wherein the flexible circuit board comprises:

a first substrate;

a second substrate disposed on the first substrate and including an opening;

the third conductive pattern portion includes:

a first extension pattern part connected to the first inner lead pattern part,

the second conductive pattern portion includes:

at least one second inner lead pattern part disposed in the first opening region of the upper protective layer; and

a second extended pattern part connected to the second inner lead pattern part, a first connection part and a first chip being disposed on the first inner lead pattern part, a second connection part and a second chip being disposed on the second inner lead pattern part, and

the number of terminals included in the first chip is larger than the number of terminals included in the second chip.

13. The chip package of claim 12, wherein the first chip comprises a driver IC chip, and

the second chip includes at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor.

14. The chip package of claim 12, wherein the second conductive pattern portion further includes a third inner lead pattern portion exposed through the second open region of the upper protective layer,

a third connection portion and a third chip are disposed on the third inner lead pattern portion, and

the total number of terminals included in the second chip and the third chip is smaller than the number of terminals included in the first chip.

15. An electronic device, comprising:

a flexible circuit board, the flexible circuit board comprising:

a first substrate;

a second substrate disposed on the first substrate and including an opening;

a third conductive pattern part disposed between the first substrate and the second substrate;

an upper protective layer partially disposed on the second conductive pattern part and including a first open region and a second open region; and

a lower protective layer partially disposed under the first conductive pattern part and including a third opened region,

wherein the third conductive pattern part includes:

a first extension pattern part connected to the first inner lead pattern part,

the second conductive pattern portion includes:

a second inner lead pattern part disposed in the first opening region of the upper protective layer;

a third inner lead pattern part disposed on the second opening region of the upper protective layer; and

a second extended pattern part connected to at least one of the second and third inner lead pattern parts,

the first conductive pattern part includes a first outer lead pattern part and a second outer lead pattern part exposed through the third opening region, and

the number of the first inner lead pattern parts is greater than that of the second inner lead pattern parts;

the electronic device further includes:

a display panel connected to the first outer lead pattern part; and

a main board connected to the second outer lead pattern part.