CN110875575A - Method for manufacturing narrow ridge structure of semiconductor laser - Google Patents
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- CN110875575A CN110875575A CN201811008424.7A CN201811008424A CN110875575A CN 110875575 A CN110875575 A CN 110875575A CN 201811008424 A CN201811008424 A CN 201811008424A CN 110875575 A CN110875575 A CN 110875575A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/223—Buried stripe structure
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Abstract
A method for manufacturing a narrow ridge structure of a semiconductor laser comprises the step of preparing a vertical narrow ridge with the width smaller than 2 mu m by using a second photoresist layer and a hard mask layer as etching masks and utilizing an ICP dry etching technology. By using the mask structure with the hard mask layer on the upper part and the first photoresist layer on the lower part, the photoresist is protected from ion bombardment while the sufficient etching selection ratio is ensured, the strength of the photoresist is maintained, and the possibility is provided for manufacturing a current injection window. The plasmas generated by ICP are utilized to enable the two side walls of the peelable glue layer to react with the oxygen plasmas, the width of the peelable glue layer is narrowed, and the purpose of making a narrower current injection window on the narrow ridge stripe is achieved.
Description
Technical Field
The invention relates to the technical field of semiconductor laser manufacturing, in particular to a manufacturing method of a narrow ridge structure of a semiconductor laser.
Background
The semiconductor laser has the advantages of small volume, light weight, power saving and the like, and is widely applied to the fields of laser printing and printing, optical measurement, robot and automatic control, cosmetology, medical treatment, optical communication and the like.
To achieve stable output of a single transverse mode spot, ridge structures that are less than 4 μm or even narrower (less than 2 μm) and have vertical sidewalls are critical. The vertical narrow ridge structure cannot be realized due to the isotropic characteristic of wet etching, and the requirement of a laser for single-mode spot output cannot be met. ICP (inductively coupled plasma) etching has the characteristic of anisotropy, and ridge structures with vertical side walls can be manufactured. Meanwhile, in order to increase the current density injected into the light emitting region and prevent the current from expanding to the non-light emitting region, a current injection window is usually made on the surface of the ridge; the conventional method for manufacturing the current injection window is to grow a layer of SiO2, spin-coat a layer of photoresist, and remove SiO2 in the window by using an etching solution containing hydrofluoric acid after exposure and development. This approach is relatively easy to implement for wide ridge structures, but is substantially impossible to implement for narrow ridge structures (especially less than 2 μm) due to the limitations of the lithography machine precision. Therefore, it is important to select a suitable method to obtain a vertical narrow ridge structure and to stably and repeatedly prepare a current injection window on the narrow ridge.
Chinese patent CN106785911A teaches a method for manufacturing a narrow ridge semiconductor device, which comprises using SiO2 as a mask, throwing positive photoresist and photo-etching a ridge window once, ICP etching to obtain a 4 μm wide ridge structure, then throwing negative photoresist and photo-etching twice, forming a 2 μm wide window on the 4 μm ridge while protecting the side wall and the lower surface of the ridge, and finally removing the SiO2 mask in the window with corrosive liquid to obtain the narrow ridge structure. The patent mainly teaches that the ridge epitaxial layer is protected from being eroded by subsequent SiO2 corrosive liquid by using secondary negative glue, and does not mention a method for manufacturing a current injection window on a ridge; meanwhile, the width of the ridge made by the method is 4 μm, and for narrower ridges (such as 2 μm), the method is limited by the precision of a photoetching machine, and the purpose of making a current injection window on the narrow ridge is difficult to achieve by using the method.
Disclosure of Invention
In order to overcome the defects of the technology, the invention provides a method for manufacturing a narrow ridge structure of a semiconductor laser, which can manufacture a vertical narrow ridge with the width less than 2 mu m and realize a current injection window on the narrow ridge. The technical scheme adopted by the invention for overcoming the technical problems is as follows:
a method for manufacturing a narrow ridge structure of a semiconductor laser comprises the following steps:
a) carrying out epitaxial growth on a semiconductor epitaxial structure on a substrate to form a semiconductor laser epitaxial wafer;
b) spin-coating a first photoresist layer on the semiconductor epitaxial structure, photoetching the first photoresist layer to form a periodic first window, developing the first window, and then hardening and baking to form a strippable photoresist layer;
c) covering and growing a hard mask layer on the semiconductor epitaxial structure and the strippable glue layer;
d) spin-coating a second photoresist layer on the hard mask layer, photoetching the hard mask layer by using a photoetching plate to obtain a photoresist mask pattern which is adaptive to the size of a required ridge stripe, forming shoulder photoresist layers on two sides above the hard mask layer, forming a ridge photoresist layer in the middle part above the hard mask layer, forming an etching groove between the ridge photoresist layer and the shoulder photoresist layers on the two sides, and hardening and baking the shoulder photoresist layers and the ridge photoresist layers;
e) etching the hard mask layer downwards along the etching groove by using the on-shoulder photoresist layer and the on-ridge photoresist layer as masks through ICP dry etching until the etching depth reaches the upper surface of the semiconductor epitaxial structure, and etching the hard mask layer positioned at the lower end of the on-ridge photoresist layer to form a peelable protective layer;
f) removing the strippable glue layers on the two sides of the strippable glue protection layer in the etching groove by utilizing ICP dry etching, and removing the on-shoulder photoresist layer and the on-ridge photoresist layer by utilizing ICP etching;
g) etching the semiconductor epitaxial structure downwards along the etching groove by using an ICP (inductively coupled plasma) dry etching method by taking the peelable glue protection layer and the hard mask layers on the two sides of the peelable glue protection layer as masks until the etching depth reaches the upper surface of a P-waveguide layer in the semiconductor epitaxial structure, and etching the semiconductor epitaxial structure below the peelable glue layer to form a ridge;
h) the strippable glue protective layer and the hard mask layers on the two sides of the strippable glue protective layer are used for masking, and plasmas generated by ICP are used for enabling the two side walls of the strippable glue layer to react with the oxygen plasmas, so that the width of the strippable glue layer is narrowed;
i) removing the peelable glue protection layer and the hard mask layers on the two sides of the peelable glue protection layer by using corrosive liquid, and hardening and baking the exposed peelable glue layer;
j) growing a current barrier layer on the surfaces of the semiconductor epitaxial structure and the strippable glue layer;
k) and stripping the strippable glue layer on the ridge stripe to form a current injection window on the current barrier layer.
Preferably, the hard mask layer in step c) is made of SiO2Or SiNxThe material is made of 2000-4000 angstrom, preferably, the current barrier layer in the step j) is made of SiO2Or SiNxThe material is made of 800-2000 angstroms in thickness.
Preferably, the first photoresist layer in step b) is a negative photoresist with a thickness of 0.8-2 μm.
Preferably, the second photoresist layer in step d) is a positive photoresist with a thickness of 1.5-3 μm.
Preferably, the etching gas in the ICP etching in the step e) is CF4Or SF6。
Preferably, the etching gas in step f) and step h) is O2。
Preferably, the gas for ICP etching in step g) is Cl2、BCl3、CCl4、Ar、N2、H2One or more of (a).
Preferably, the etching solution in step i) is a solution containing HF acid.
Preferably, the hard mask layer in step c) and the current blocking layer in step j) are grown by using a PVD or PECVD apparatus at a growth temperature of 50-100 ℃.
Preferably, the width of the peelable glue layer is less than the sum of the widths of the peelable glue protective layer and the two etched grooves.
The invention has the beneficial effects that: and preparing the vertical narrow ridge stripe with the width less than 2 mu m by using the second photoresist layer and the hard mask layer as etching masks and utilizing an ICP dry etching technology. By using the mask structure with the hard mask layer on the upper part and the first photoresist layer on the lower part, the photoresist is protected from ion bombardment while the sufficient etching selection ratio is ensured, the strength of the photoresist is maintained, and the possibility is provided for manufacturing a current injection window. The plasmas generated by ICP are utilized to enable the two side walls of the peelable glue layer to react with the oxygen plasmas, the width of the peelable glue layer is narrowed, and the purpose of making a narrower current injection window on the narrow ridge stripe is achieved. Because the step e), the step f) and the step g) are all completed by adopting dry etching, the manufacturing process is carried out in the ICP etching cavity, only etching gas needs to be replaced, and other processing is not needed to be carried out by opening the cavity and taking the wafer, so that the continuity of the manufacturing process is ensured, the production efficiency is improved, and the cost is reduced.
Drawings
FIG. 1 is a schematic structural view of a spin-coated first photoresist layer according to the present invention;
FIG. 2 is a schematic structural diagram of the peelable glue layer of the present invention after being formed;
FIG. 3 is a schematic diagram of a structure after forming a hard mask layer according to the present invention;
FIG. 4 is a schematic structural view of the spin-coated second photoresist layer of the present invention;
FIG. 5 is a schematic diagram of the structure after forming the etched trench according to the present invention;
FIG. 6 is a schematic structural diagram of the peelable glue protective layer according to the present invention;
FIG. 7 is a schematic structural view of the present invention after removing the over-shoulder photoresist layer and the over-ridge photoresist layer;
FIG. 8 is a schematic diagram of the structure after etching to form ridge bars according to the present invention;
FIG. 9 is a schematic view of a structure of the present invention after the width of the peelable glue layer is narrowed;
FIG. 10 is a schematic view of the structure of the present invention after the current blocking layer is grown;
FIG. 11 is a schematic diagram of a structure after forming a current injection window according to the present invention;
in the figure, 1, a substrate 2, a semiconductor epitaxial structure 3, a first photoresist layer 301, a strippable glue layer 4, SiO2 Hard mask layer 401, strippable protective layer 5, second photoresist layer 501, shoulder photoresist layer 502, ridge photoresist layer 6, P-waveguide layer 7, ridge stripe 8, SiO2 Current blocking layer 9 current injection window.
Detailed Description
The present invention will be further described with reference to fig. 1 to 11.
A method for manufacturing a narrow ridge structure of a semiconductor laser comprises the following steps:
a) as shown in fig. 1, a semiconductor laser epitaxial wafer is formed by epitaxially growing a semiconductor epitaxial structure 2 on a substrate 1;
b) as shown in fig. 2, a first photoresist layer 3 is spin-coated on the semiconductor epitaxial structure 2, a periodic first window is formed on the first photoresist layer 3 by lithography, and the first window is developed and then is hardened and baked to form a peelable layer 301;
c) as shown in fig. 3, a hard mask layer 4 is blanket grown on the semiconductor epitaxial structure 2 and the peelable glue layer 301;
d) as shown in fig. 4 and 5, a second photoresist layer 5 is spin-coated on the hard mask layer 4, a photoresist mask pattern corresponding to the required ridge size is obtained by photoetching the hard mask layer 4 by using a photoetching plate, shoulder photoresist layers 501 are formed on two sides above the hard mask layer 4, a ridge photoresist layer 502 is formed in the middle part above the hard mask layer 4, an etching groove is formed between the ridge photoresist layer 502 and the shoulder photoresist layers 501 on two sides, and the shoulder photoresist layer 501 and the ridge photoresist layer 502 are hardened and baked;
e) as shown in fig. 6, the hard mask layer 4 is etched downwards along the etching groove by ICP dry etching with the on-shoulder photoresist layer 501 and the on-ridge photoresist layer 502 as masks, the etching depth is up to the upper surface of the semiconductor epitaxial structure 2, and the hard mask layer 4 at the lower end of the on-ridge photoresist layer 502 is etched to form a peelable photoresist protection layer 401;
f) as shown in fig. 7, the strippable glue layer 301 on the two sides of the strippable glue protection layer 401 in the etching groove is removed by ICP dry etching, and the on-shoulder photoresist layer 501 and the on-ridge photoresist layer 502 are removed by ICP etching;
g) as shown in fig. 8, the strippable glue protection layer 401 and the hard mask layers 4 on the two sides thereof are used as masks, the semiconductor epitaxial structure 2 is etched downwards along the etching groove by using ICP dry etching, the etching depth is up to the upper surface of the P-waveguide layer 6 in the semiconductor epitaxial structure 2, and the semiconductor epitaxial structure 2 below the strippable glue layer 301 is etched to form a ridge stripe 7;
h) as shown in fig. 9, by using the peelable glue protection layer 401 and the masking of the hard mask layers 4 on both sides thereof, the plasma generated by ICP is used to make both sidewalls of the peelable glue layer 301 react with the oxygen plasma, and the width of the peelable glue layer 301 is narrowed;
i) removing the peelable glue protection layer 401 and the hard mask layers 4 on the two sides of the peelable glue protection layer by using corrosive liquid, and hardening and baking the exposed peelable glue layer 301;
j) as shown in fig. 10, a current blocking layer 8 is grown on the surface of the semiconductor epitaxial structure 2 and the surface of the peelable glue layer 301;
k) as shown in fig. 11, the peelable glue layer 301 on the ridge stripe 7 is peeled off to form a current injection window 9 on the current blocking layer 8.
Vertical narrow ridge stripes having a width of less than 2 μm are prepared by an ICP dry etching technique using the second photoresist layer 5 and the hard mask layer 4 as etching masks. By using the mask structure with the hard mask layer 4 on the upper part and the first photoresist layer on the lower part, the photoresist is protected from ion bombardment while the sufficient etching selection ratio is ensured, the strength of the photoresist is maintained, and the possibility is provided for manufacturing a current injection window. Plasma generated by ICP is utilized to enable two side walls of the peelable glue layer 301 to react with oxygen plasma, the width of the peelable glue layer 301 is narrowed, and the purpose of making a narrower current injection window on the narrow ridge is achieved. Because the step e), the step f) and the step g) are all completed by adopting dry etching, the manufacturing process is carried out in the ICP etching cavity, only etching gas needs to be replaced, and other processing is not needed to be carried out by opening the cavity and taking the wafer, so that the continuity of the manufacturing process is ensured, the production efficiency is improved, and the cost is reduced.
Example 1:
the hard mask layer 4 in step c) is made of SiO2Or SiNxMade of a material with a thickness of 2000-4000 angstroms,
the current barrier layer 8 in step j) is made of SiO2Or SiNxThe material is made of 800-2000 angstroms in thickness.
Example 2:
in the step b), the first photoresist layer (3) is a negative photoresist with the thickness of 0.8-2 μm.
Example 3:
in the step d), the second photoresist layer (5) is selected from positive photoresist, and the thickness of the second photoresist layer is 1.5-3 mu m.
Example 4:
the etching gas in the step e) during ICP etching isCF4Or SF6。
Example 5:
the etching gas in the step f) and the step h) is O2。
Example 6:
the gas in the step g) during ICP etching is Cl2、BCl3、CCl4、Ar、N2、H2One or more of (a).
Example 7:
the corrosive liquid in the step i) is a solution containing HF acid.
The implementation is as follows:
the hard mask layer (4) in the step c) and the current barrier layer (8) in the step j) are grown by using PVD or PECVD equipment, and the growth temperature is 50-100 ℃.
Example 9:
the width of the strippable glue layer (301) is less than the sum of the widths of the strippable glue protective layer (401) and the two etching grooves.
Claims (10)
1. A method for manufacturing a narrow ridge structure of a semiconductor laser is characterized by comprising the following steps:
a) carrying out epitaxial growth on a semiconductor epitaxial structure (2) on a substrate (1) to form a semiconductor laser epitaxial wafer;
b) spin-coating a first photoresist layer (3) on the semiconductor epitaxial structure (2), photoetching the first photoresist layer (3) to form a periodic first window, developing the first window, and then hardening and baking to form a strippable glue layer (301);
c) covering and growing a hard mask layer (4) on the semiconductor epitaxial structure (2) and the strippable glue layer (301);
d) spin-coating a second photoresist layer (5) on the hard mask layer (4), photoetching the hard mask layer (4) by using a photoetching plate to obtain a photoresist mask pattern which is adaptive to the size of a required ridge strip, forming shoulder photoresist layers (501) on two sides above the hard mask layer (4), forming a ridge photoresist layer (502) in the middle part above the hard mask layer (4), forming an etching groove between the ridge photoresist layer (502) and the shoulder photoresist layers (501) on the two sides, and hardening and baking the shoulder photoresist layers (501) and the ridge photoresist layer (502);
e) etching the hard mask layer (4) downwards along the etching groove by using the on-shoulder photoresist layer (501) and the on-ridge photoresist layer (502) as masks through ICP dry etching until the etching depth reaches the upper surface of the semiconductor epitaxial structure (2), and etching the hard mask layer (4) positioned at the lower end of the on-ridge photoresist layer (502) to form a peelable photoresist protective layer (401);
f) removing the peelable glue layers (301) on two sides of the peelable glue protection layer (401) in the etching groove by utilizing ICP dry etching, and removing the on-shoulder photoresist layer (501) and the on-ridge photoresist layer (502) by utilizing ICP etching;
g) taking the peelable glue protection layer (401) and the hard mask layers (4) on the two sides of the peelable glue protection layer as masks, etching the semiconductor epitaxial structure (2) downwards along the etching groove by using ICP (inductively coupled plasma) dry etching, wherein the etching depth is up to the upper surface of a P-waveguide layer (6) in the semiconductor epitaxial structure (2), and etching the semiconductor epitaxial structure (2) below the peelable glue layer (301) to form a ridge stripe (7);
h) by using the peelable glue protective layer (401) and the masking of the hard mask layers (4) on the two sides of the peelable glue protective layer, the two side walls of the peelable glue layer (301) are reacted with oxygen plasma by using plasma generated by ICP, and the width of the peelable glue layer (301) is narrowed;
i) removing the peelable glue protection layer (401) and the hard mask layers (4) on the two sides of the peelable glue protection layer by using corrosive liquid, and hardening and baking the exposed peelable glue layer (301);
j) growing a current barrier layer (8) on the surfaces of the semiconductor epitaxial structure (2) and the strippable glue layer (301);
k) and stripping the strippable glue layer (301) on the ridge stripe (7) to form a current injection window (9) on the current barrier layer (8).
2. A method for fabricating a narrow ridge structure of a semiconductor laser as claimed in claim 1 wherein: the hard mask layer (4) in the step c) is made of SiO2Or SiNxMade of a material having a thickness of 2000-4000A, the current blocking layer (8) in step j) being made of SiO2Or SiNxThe material is made of 800-2000 angstroms in thickness.
3. A method for fabricating a narrow ridge structure of a semiconductor laser as claimed in claim 1 wherein: in the step b), the first photoresist layer (3) is a negative photoresist with the thickness of 0.8-2 μm.
4. A method for fabricating a narrow ridge structure of a semiconductor laser as claimed in claim 1 wherein: in the step d), the second photoresist layer (5) is selected from positive photoresist, and the thickness of the second photoresist layer is 1.5-3 mu m.
5. A method for fabricating a narrow ridge structure of a semiconductor laser as claimed in claim 1 wherein: the etching gas in the ICP etching in the step e) is CF4Or SF6。
6. A method for fabricating a narrow ridge structure of a semiconductor laser as claimed in claim 1 wherein: the etching gas in the step f) and the step h) is O2。
7. A method for fabricating a narrow ridge structure of a semiconductor laser as claimed in claim 1 wherein: the gas in the step g) during ICP etching is Cl2、BCl3、CCl4、Ar、N2、H2One or more of (a).
8. A method for fabricating a narrow ridge structure of a semiconductor laser as claimed in claim 1 wherein: the corrosive liquid in the step i) is a solution containing HF acid.
9. A method for fabricating a narrow ridge structure of a semiconductor laser as claimed in claim 1 wherein: the hard mask layer (4) in the step c) and the current barrier layer (8) in the step j) are grown by using PVD or PECVD equipment, and the growth temperature is 50-100 ℃.
10. A method for fabricating a narrow ridge structure of a semiconductor laser as claimed in claim 1 wherein: the width of the strippable glue layer (301) is less than the sum of the widths of the strippable glue protective layer (401) and the two etching grooves.
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| CN113571609A (en) * | 2021-07-21 | 2021-10-29 | 江西兆驰半导体有限公司 | Double ISO process for high-voltage LED chip |
| CN114400496A (en) * | 2021-12-22 | 2022-04-26 | 西安立芯光电科技有限公司 | Semiconductor laser array bar manufacturing method and semiconductor laser array bar |
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| CN113571609A (en) * | 2021-07-21 | 2021-10-29 | 江西兆驰半导体有限公司 | Double ISO process for high-voltage LED chip |
| CN114400496A (en) * | 2021-12-22 | 2022-04-26 | 西安立芯光电科技有限公司 | Semiconductor laser array bar manufacturing method and semiconductor laser array bar |
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