CN113571609A - Double ISO process for high-voltage LED chip - Google Patents
Double ISO process for high-voltage LED chip Download PDFInfo
- Publication number
- CN113571609A CN113571609A CN202110825690.4A CN202110825690A CN113571609A CN 113571609 A CN113571609 A CN 113571609A CN 202110825690 A CN202110825690 A CN 202110825690A CN 113571609 A CN113571609 A CN 113571609A
- Authority
- CN
- China
- Prior art keywords
- photoresist
- less
- equal
- substrate
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
Abstract
The invention provides a double ISO process for a high-voltage LED chip, which comprises the following steps: the method comprises the following steps: coating a first photoresist on a substrate with an epitaxial layer, exposing by using a first photomask, and then developing and hardening; step two: coating a second photoresist on the basis of the first step, exposing by using a second photomask, and then developing and baking; step three: performing ICP etching on the basis of the second step; step four: and removing the photoresist. Compared with the prior art, the high-voltage LED chip double ISO process provided by the invention has the advantages that two times of continuous photoetching and one-time ICP etching are adopted, one ICP etching procedure is reduced, the cost of the double ISO process is reduced, and the production efficiency is improved.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a double ISO process for a high-voltage LED chip.
Background
With the continuous development of semiconductor technology, the LED chip occupies the leading positions of two fields of illumination and display by the advantages of energy conservation, high brightness, high durability, long service life, lightness and the like, the High Voltage (HV) LED chip is particularly and greatly applied to the direction of a bulb lamp, each independent light-emitting unit is connected in series in the chip manufacturing stage, the wire bonding times in the packaging stage are reduced, the cost is saved, the production efficiency is greatly improved, and the driving cost of an application end is effectively reduced by the advantage of high voltage of the High Voltage (HV) LED chip;
with the gradual development of the technology, the current high-pressure product gradually pushes out a double-ISO process to improve the luminous efficiency, and the current mainstream double-ISO process adopts a process of firstly performing channel photoetching, performing dry etching on GaN at a channel, then performing photoetching at a metal bridging part, and performing dry etching on the GaN at the bridging part so as to achieve the effect of double angles of the channel and the bridging; however, the cost of the existing process needs to be further reduced, and the production efficiency needs to be improved. Based on the above description, the invention provides a manufacturing method of a high-voltage LED chip by using a dual ISO process.
Disclosure of Invention
The invention aims to provide a manufacturing method of a high-voltage LED chip double ISO process, which optimizes the existing double ISO process, reduces the cost of the double ISO process and improves the production efficiency.
The invention adopts the following technical scheme to solve the technical problems:
a high-voltage LED chip double ISO process comprises the following steps:
the method comprises the following steps: coating a first photoresist on a substrate with an epitaxial layer, exposing by using a first photomask, and then developing and hardening;
step two: coating a second photoresist on the basis of the first step, exposing by using a second photomask, and then developing and baking;
step three: performing ICP etching on the basis of the second step;
step four: and removing the photoresist.
Further, in the first reticle stage: c1 is more than or equal to 10um and less than or equal to d1 and less than or equal to 20um, a1 and less than or equal to 20um and less than or equal to 30um, b1 and less than or equal to 2um and less than or equal to 10 um; wherein a1 is the width of the isolation channel inside the chip, b1 is the width of the bridge, and c1 and d1 are the widths of the isolation channels at the periphery of the chip in different directions.
Further, in the second reticle stage: c2 is more than or equal to 5um and less than or equal to d2 and less than or equal to 15um, a2 is more than or equal to 5um and less than or equal to 15um, b2 is more than or equal to 50um and less than or equal to 70 um; wherein a2 is the width of the isolation channel inside the chip, b2 is the width of the bridge, and c2 and d2 are the widths of the isolation channels at the periphery of the chip in different directions.
Further, the first photoresist is a positive photoresist with the thickness of 6-12 um; the first photoresist hardening temperature is 100-160 ℃, and the hardening time is 30-60 min.
Further, the second photoresist is a positive photoresist with the thickness of 4-8 um; the baking temperature of the second photoresist is 80-110 ℃, and the baking time is 10-20 min.
And further, the second photoresist is a positive photoresist, and after the fourth step is finished, the included angle between the epitaxial layer and the substrate at the channel is more than or equal to 60 degrees and less than or equal to 80 degrees.
And further, the second photoresist is a positive photoresist, after the fourth step is finished, the included angle beta between the epitaxial layer at the bridging part and the substrate is more than or equal to 20 degrees and less than or equal to 50 degrees, and the included angle alpha between the epitaxial layer at the side wall and the substrate is more than or equal to 60 degrees and less than or equal to 80 degrees.
Further, the second photoresist is a negative photoresist with the thickness of 4-10 um; the baking temperature of the second photoresist is 50-80 ℃, and the baking time is 2-4 min.
And further, the second photoresist is a negative photoresist, and after the fourth step is finished, the included angle between the epitaxial layer and the substrate at the channel is more than or equal to 75 degrees and less than or equal to gamma 2 and less than 90 degrees.
Further, the second photoresist is a negative photoresist, after the fourth step is finished, the included angle between the epitaxial layer at the bridging part and the substrate is more than or equal to 20 degrees and less than or equal to beta 2 and less than or equal to 50 degrees, and the included angle between the epitaxial layer at the side wall and the substrate is more than or equal to 75 degrees and less than or equal to alpha 2 and less than 90 degrees
The invention has the advantages that:
1. the high-voltage LED chip double-ISO process provided by the invention comprises two continuous photoetching and one ICP etching, and the existing double-ISO photoetching and two ICP etching processes are optimized, so that compared with the existing process, one ICP etching procedure is reduced, the cost of the double-ISO process is reduced, and the production efficiency is improved;
2. the invention provides a process for freely selecting positive and negative glue properties by secondary photoetching, so that the etching angles of a channel and a side wall can be freely adjusted; due to the photosensitivity of the photoresist, the etching angles of the channel and the side wall can be freely adjusted within the range of 25-85 degrees by changing the photoetching energy.
3. In the first reticle stage of the present invention: c1 is more than or equal to 10um and less than or equal to d1 and less than or equal to 20um, a1 and less than or equal to 20um and less than or equal to 30um, b1 and less than or equal to 2um and less than or equal to 10 um; in the second reticle plate: c2 is more than or equal to 5um and less than or equal to d2 and less than or equal to 15um, a2 is more than or equal to 5um and less than or equal to 15um, b2 is more than or equal to 50um and less than or equal to 70 um; in the first photomask, a1 is the width of the isolation channel inside the chip, b1 is the width of the bridge, and c1 and d1 are the widths of the isolation channels on the periphery of the chip in different directions; in the second reticle, a2 is the width of the isolation channel inside the chip, b2 is the width of the bridge, and c2 and d2 are the widths of the isolation channels on the periphery of the chip in different directions; compared with the width of a cutting channel in the prior art, the numerical value of the cutting channel is greatly reduced, so that the light-emitting area is increased, and the light-emitting efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a first mask of the present invention;
FIG. 2 is a cross-sectional view taken along line A1 of FIG. 1 after a first photolithography step of the present invention has been performed;
FIG. 3 is a cross-sectional view taken along line B1 of FIG. 1 after a first photolithography step of the present invention has been performed;
FIG. 4 is a schematic diagram of a second mask in accordance with an embodiment of the present invention;
FIG. 5 is a cross-sectional view taken along line A2 of FIG. 4 after completion of a second photolithography in accordance with an embodiment of the present invention;
FIG. 6 is a cross-sectional view taken along line B2 of FIG. 4 after completion of a second photolithography in accordance with an embodiment of the present invention;
FIG. 7 is a cross-sectional view taken along line A2 of FIG. 4 after ICP etching to remove resist in accordance with an embodiment of the invention;
FIG. 8 is a cross-sectional view taken along line B2 of FIG. 4 after ICP etching to remove resist in an embodiment of the invention;
FIG. 9 is a schematic diagram of a second mask in accordance with an embodiment of the present invention;
FIG. 10 is a cross-sectional view taken along line A2 of FIG. 9 after completion of a second photolithography in accordance with an embodiment of the present invention;
FIG. 11 is a cross-sectional view taken along line B2 of FIG. 9 after completion of a second photolithography in accordance with an embodiment of the present invention;
FIG. 12 is a cross-sectional view taken along line A2 of FIG. 9 after ICP etching to remove photoresist in accordance with an embodiment of the invention;
FIG. 13 is a cross-sectional view taken along line B2 in FIG. 9 after ICP etching to remove resist in accordance with an embodiment of the invention;
wherein, 1, a substrate; 2. an epitaxial layer; 3. and (7) photoresist.
Detailed Description
The invention is further illustrated by the following examples, which are intended to illustrate, but not to limit the invention further. The technical means used in the following examples are conventional means well known to those skilled in the art, and all raw materials are general-purpose materials.
Example 1
As shown in FIGS. 1-8, FIG. 1 is a schematic view of a first mask of the present invention; FIG. 2 is a cross-sectional view taken along line A1 of FIG. 1 after a first photolithography step of the present invention has been performed; FIG. 3 is a cross-sectional view taken along line B1 of FIG. 1 after a first photolithography step of the present invention has been performed; FIG. 4 is a schematic diagram of a second mask in accordance with an embodiment of the present invention; FIG. 5 is a cross-sectional view taken along line A2 of FIG. 4 after completion of a second photolithography in accordance with an embodiment of the present invention; FIG. 6 is a cross-sectional view taken along line B2 of FIG. 4 after completion of a second photolithography in accordance with an embodiment of the present invention; FIG. 7 is a cross-sectional view taken along line A2 of FIG. 4 after ICP etching to remove resist in accordance with an embodiment of the invention; FIG. 8 is a cross-sectional view taken along line B2 of FIG. 4 after ICP etching to remove resist in an embodiment of the invention;
the double ISO process for the high-voltage LED chip provided in the embodiment 1 of the application comprises the following steps:
the method comprises the following steps: coating a first photoresist on a substrate with an epitaxial layer, exposing by using a first photomask, and then developing and hardening;
step two: coating a second photoresist on the basis of the first step, exposing by using a second photomask, and then developing and baking;
step three: performing ICP etching on the basis of the second step, etching through the epitaxial layer at the position without the photoresist protection, and etching to the substrate;
step four: and removing the surface photoresist after the etching is finished.
Wherein:
in the first reticle stage: c1 ═ d1 ═ 15um, a1 ═ 25um, b1 ═ 6 um; in the second mask plate: c2 ═ d2 ═ 10um, a2 ═ 10um, b2 ═ 60 um;
in the first photomask, a1 is the width of the isolation channel inside the chip, b1 is the width of the bridge, and c1 and d1 are the widths of the isolation channels on the periphery of the chip in different directions; in the second reticle, a2 is the width of the isolation channel inside the chip, b2 is the width of the bridge, and c2 and d2 are the widths of the isolation channels on the periphery of the chip in different directions;
the first photoresist is a positive photoresist with the thickness of 9 um; hardening the first photoresist at 130 ℃ for 45 min; the second photoresist is positive photoresist with the thickness of 6 um; the baking temperature of the second photoresist is 95 ℃, and the baking time is 15 min;
after the fourth step is finished, an included angle gamma between the epitaxial layer at the channel and the substrate is 70 degrees; the angle beta between the epitaxial layer at the bridge and the substrate is 35 degrees, and the angle alpha between the epitaxial layer at the side wall and the substrate is 70 degrees.
In the case of the example 2, the following examples are given,
on the basis of the process of the embodiment 1, parameters in each step are adjusted, wherein:
in the first reticle stage: c1 ═ d1 ═ 10um, a1 ═ 20um, b1 ═ 2 um; in the second mask plate: c2 ═ d2 ═ 5um, a2 ═ 5um, b2 ═ 50 um;
in the first photomask, a1 is the width of the isolation channel inside the chip, b1 is the width of the bridge, and c1 and d1 are the widths of the isolation channels on the periphery of the chip in different directions; in the second reticle, a2 is the width of the isolation channel inside the chip, b2 is the width of the bridge, and c2 and d2 are the widths of the isolation channels on the periphery of the chip in different directions;
the first photoresist is positive photoresist with the thickness of 6 um; hardening the first photoresist at 100 ℃ for 30 min; the second photoresist is a positive photoresist with the thickness of 4 um; the baking temperature of the second photoresist is 80 ℃, and the baking time is 10 min;
after the fourth step is finished, an included angle gamma between the epitaxial layer at the channel and the substrate is 60 degrees; the angle beta between the epitaxial layer at the bridge and the substrate is 20 degrees, and the angle alpha between the epitaxial layer at the side wall and the substrate is 60 degrees.
Example 3
On the basis of the process of the embodiment 1, parameters in each step are adjusted, wherein:
in the first reticle stage: c1 ═ d1 ═ 20um, a1 ═ 30um, b1 ═ 10 um; in the second mask plate: c2 ═ d2 ═ 15um, a2 ═ 15um, b2 ═ 70 um;
in the first photomask, a1 is the width of the isolation channel inside the chip, b1 is the width of the bridge, and c1 and d1 are the widths of the isolation channels on the periphery of the chip in different directions; in the second reticle, a2 is the width of the isolation channel inside the chip, b2 is the width of the bridge, and c2 and d2 are the widths of the isolation channels on the periphery of the chip in different directions;
the first photoresist is a positive photoresist with the thickness of 12 um; hardening the first photoresist at 160 ℃ for 60 min; the second photoresist is a positive photoresist with the thickness of 8 um; the baking temperature of the second photoresist is 110 ℃, and the baking time is 20 min;
after the fourth step is finished, an included angle gamma between the epitaxial layer at the channel and the substrate is 80 degrees; the angle beta between the epitaxial layer at the bridge and the substrate is 50 degrees, and the angle alpha between the epitaxial layer at the side wall and the substrate is 80 degrees.
Example 4:
as shown in FIGS. 9-13, FIG. 9 is a schematic diagram of a second mask in an embodiment of the present invention; FIG. 10 is a cross-sectional view taken along line A2 of FIG. 9 after completion of a second photolithography in accordance with an embodiment of the present invention; FIG. 11 is a cross-sectional view taken along line B2 of FIG. 9 after completion of a second photolithography in accordance with an embodiment of the present invention; FIG. 12 is a cross-sectional view taken along line A2 of FIG. 9 after ICP etching to remove photoresist in accordance with an embodiment of the invention; FIG. 13 is a cross-sectional view taken along line B2 in FIG. 9 after ICP etching to remove resist in accordance with an embodiment of the invention;
the high-voltage LED chip double ISO process provided in embodiment 2 of the application comprises the following steps:
the method comprises the following steps: coating a first photoresist on a substrate with an epitaxial layer, exposing by using a first photomask, and then developing and hardening;
step two: coating a second photoresist on the basis of the first step, exposing by using a second photomask, and then developing and baking;
step three: performing ICP etching on the basis of the second step, etching through the epitaxial layer at the position without the photoresist protection, and etching to the substrate;
step four: and removing the surface photoresist after the etching is finished.
Wherein:
in the first reticle stage: c1 ═ d1 ═ 15um, a1 ═ 25um, b1 ═ 6 um; in the second mask plate: c2 ═ d2 ═ 10um, a2 ═ 20um, b2 ═ 60 um;
in the first photomask, a1 is the width of the isolation channel inside the chip, b1 is the width of the bridge, and c1 and d1 are the widths of the isolation channels on the periphery of the chip in different directions; in the second reticle, a2 is the width of the isolation channel inside the chip, b2 is the width of the bridge, and c2 and d2 are the widths of the isolation channels on the periphery of the chip in different directions;
the first photoresist is a positive photoresist with the thickness of 9 um; hardening the first photoresist at 130 ℃ for 45 min; the second photoresist is a negative photoresist with the thickness of 6 um; the baking temperature of the second photoresist is 65 ℃, and the baking time is 3
min；
After the fourth step is finished, an included angle gamma 2 between the epitaxial layer at the channel and the substrate is 80 degrees; the included angle beta 2 between the epitaxial layer at the bridge joint and the substrate is 35 degrees, and the included angle alpha 2 between the epitaxial layer at the side wall and the substrate is more than or equal to 75 degrees and less than 90 degrees.
Example 5
On the basis of the process of the embodiment 4, parameters in each step are adjusted, wherein:
in the first reticle stage: c1 ═ d1 ═ 10um, a1 ═ 20um, b1 ═ 2 um; in the second mask plate: c2 ═ d2 ═ 5um, a2 ═ 5um, b2 ═ 50 um;
in the first photomask, a1 is the width of the isolation channel inside the chip, b1 is the width of the bridge, and c1 and d1 are the widths of the isolation channels on the periphery of the chip in different directions; in the second reticle, a2 is the width of the isolation channel inside the chip, b2 is the width of the bridge, and c2 and d2 are the widths of the isolation channels on the periphery of the chip in different directions;
the first photoresist is positive photoresist with the thickness of 6 um; hardening the first photoresist at 100 ℃ for 30 min; the second photoresist is a negative photoresist with the thickness of 4 um; the baking temperature of the second photoresist is 50 ℃, and the baking time is 2 min;
after the fourth step is finished, an included angle gamma 2 between the epitaxial layer at the channel and the substrate is 75 degrees; the angle beta 2 between the epitaxial layer and the substrate at the bridge is 20 degrees, and the angle alpha 2 between the epitaxial layer and the substrate at the side wall is 75 degrees.
Example 6
On the basis of the process of the embodiment 4, parameters in each step are adjusted, wherein:
in the first reticle stage: c1 ═ d1 ═ 20um, a1 ═ 30um, b1 ═ 10 um; in the second mask plate: c2 ═ d2 ═ 15um, a2 ═ 15um, b2 ═ 70 um;
in the first photomask, a1 is the width of the isolation channel inside the chip, b1 is the width of the bridge, and c1 and d1 are the widths of the isolation channels on the periphery of the chip in different directions; in the second reticle, a2 is the width of the isolation channel inside the chip, b2 is the width of the bridge, and c2 and d2 are the widths of the isolation channels on the periphery of the chip in different directions;
the first photoresist is a positive photoresist with the thickness of 12 um; hardening the first photoresist at 160 ℃ for 60 min; the second photoresist is a negative photoresist with the thickness of 10 um; the baking temperature of the second photoresist is 80 ℃, and the baking time is 4 min;
after the fourth step is finished, an included angle gamma 2 between the epitaxial layer at the channel and the substrate is 89 degrees; the angle beta 2 between the epitaxial layer at the bridge and the substrate is 50 degrees, and the angle alpha 2 between the epitaxial layer at the side wall and the substrate is 75 degrees.
Finally, it should be noted that: the above embodiments are only used to illustrate the present invention and do not limit the technical solutions described in the present invention; it will be understood by those skilled in the art that the present invention may be modified and equivalents may be substituted; all such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention and protected by the following claims.
Claims (10)
1. A high-voltage LED chip double ISO process is characterized by comprising the following steps:
the method comprises the following steps: coating a first photoresist on a substrate with an epitaxial layer, exposing by using a first photomask, and then developing and hardening;
step two: coating a second photoresist on the basis of the first step, exposing by using a second photomask, and then developing and baking;
step three: performing ICP etching on the basis of the second step;
step four: and removing the photoresist.
2. The high-voltage LED chip dual ISO process according to claim 1, wherein in the first reticle plate: d1 is not less than 10um and not more than 20um, a1 is not less than 20um and not more than 30um, b1 is not less than 2um and not more than 10um, wherein a1 is the width of the isolation channel inside the chip, b1 is the bridging width, and c1 and d1 are the widths of the isolation channels on the periphery of the chip in different directions.
3. The high-voltage LED chip dual ISO process according to claim 1, wherein in the second reticle stage: c2 is larger than or equal to 5um and smaller than or equal to 15um, a2 is larger than or equal to 5um and smaller than or equal to 15um, b2 is larger than or equal to 50um and smaller than or equal to 70um, wherein a2 is the width of the isolation channel inside the chip, b2 is the bridging width, and c2 and d2 are the widths of the isolation channels on the periphery of the chip in different directions.
4. The dual ISO process for the high voltage LED chip according to claim 1, wherein the first photoresist is a positive photoresist with a thickness of 6-12 um; the first photoresist hardening temperature is 100-160 ℃, and the hardening time is 30-60 min.
5. The dual ISO process for the high voltage LED chip according to claim 1, wherein the second photoresist is a positive photoresist with a thickness of 4-8 um; the baking temperature of the second photoresist is 80-110 ℃, and the baking time is 10-20 min.
6. The dual ISO process for the high voltage LED chip according to claim 1, wherein the second photoresist is a positive photoresist, and after the fourth step, an angle between the epitaxial layer and the substrate at the trench is 60 ° or more and γ or less and 80 ° or less.
7. The dual ISO process for the high voltage LED chip according to claim 1, wherein the second photoresist is a positive photoresist, and after the fourth step, the angle between the epitaxial layer at the bridge and the substrate is 20 ° or more and 50 ° or less, and the angle between the epitaxial layer at the sidewall and the substrate is 60 ° or more and α or less and 80 ° or less.
8. The dual ISO process for high voltage LED chips of claim 1, wherein the second photoresist is a negative photoresist with a thickness of 4-10 um; the baking temperature of the second photoresist is 50-80 ℃, and the baking time is 2-4 min.
9. The dual ISO process for the high voltage LED chip according to claim 1, wherein the second photoresist is a negative photoresist, and after the fourth step, an angle between the epitaxial layer and the substrate at the trench is 75 ° or more and γ 2 or less than 90 °.
10. The dual ISO process for the high voltage LED chip according to claim 1, wherein the second photoresist is a negative photoresist, and after the fourth step, the angle between the epitaxial layer at the bridge and the substrate is 20 ° or more and β 2 or less and 50 ° or less, and the angle between the epitaxial layer at the sidewall and the substrate is 75 ° or more and α 2 or less and 90 °.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110825690.4A CN113571609A (en) | 2021-07-21 | 2021-07-21 | Double ISO process for high-voltage LED chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110825690.4A CN113571609A (en) | 2021-07-21 | 2021-07-21 | Double ISO process for high-voltage LED chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113571609A true CN113571609A (en) | 2021-10-29 |
Family
ID=78165959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110825690.4A Pending CN113571609A (en) | 2021-07-21 | 2021-07-21 | Double ISO process for high-voltage LED chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113571609A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102556950A (en) * | 2012-02-07 | 2012-07-11 | 中国科学院光电技术研究所 | Tunable artificial electromagnetic material based on three-layer structure and preparation method thereof |
| CN103367558A (en) * | 2012-03-29 | 2013-10-23 | 山东浪潮华光光电子股份有限公司 | Spherical photoresist mask and preparation method thereof |
| CN103956418A (en) * | 2014-05-08 | 2014-07-30 | 项永昌 | Composite patterned substrate and preparation method thereof |
| CN104701434A (en) * | 2015-02-13 | 2015-06-10 | 西安神光皓瑞光电科技有限公司 | Flip LED chip preparation method |
| CN105226502A (en) * | 2014-06-30 | 2016-01-06 | 山东华光光电子有限公司 | A kind of preparation method of narrow vallum type GaAs base GaInP quantum well structure semiconductor laser |
| CN105719955A (en) * | 2016-02-16 | 2016-06-29 | 山东浪潮华光光电子股份有限公司 | Preparation method of GaN-based light-emitting diode chip |
| CN110875575A (en) * | 2018-08-31 | 2020-03-10 | 山东华光光电子股份有限公司 | Method for manufacturing narrow ridge structure of semiconductor laser |
| CN112147848A (en) * | 2019-06-26 | 2020-12-29 | 山东华光光电子股份有限公司 | Preparation method of small-size groove |
| CN112349818A (en) * | 2020-10-27 | 2021-02-09 | 江西乾照光电有限公司 | Deep etching method for high-voltage LED chip |
-
2021
- 2021-07-21 CN CN202110825690.4A patent/CN113571609A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102556950A (en) * | 2012-02-07 | 2012-07-11 | 中国科学院光电技术研究所 | Tunable artificial electromagnetic material based on three-layer structure and preparation method thereof |
| CN103367558A (en) * | 2012-03-29 | 2013-10-23 | 山东浪潮华光光电子股份有限公司 | Spherical photoresist mask and preparation method thereof |
| CN103956418A (en) * | 2014-05-08 | 2014-07-30 | 项永昌 | Composite patterned substrate and preparation method thereof |
| CN105226502A (en) * | 2014-06-30 | 2016-01-06 | 山东华光光电子有限公司 | A kind of preparation method of narrow vallum type GaAs base GaInP quantum well structure semiconductor laser |
| CN104701434A (en) * | 2015-02-13 | 2015-06-10 | 西安神光皓瑞光电科技有限公司 | Flip LED chip preparation method |
| CN105719955A (en) * | 2016-02-16 | 2016-06-29 | 山东浪潮华光光电子股份有限公司 | Preparation method of GaN-based light-emitting diode chip |
| CN110875575A (en) * | 2018-08-31 | 2020-03-10 | 山东华光光电子股份有限公司 | Method for manufacturing narrow ridge structure of semiconductor laser |
| CN112147848A (en) * | 2019-06-26 | 2020-12-29 | 山东华光光电子股份有限公司 | Preparation method of small-size groove |
| CN112349818A (en) * | 2020-10-27 | 2021-02-09 | 江西乾照光电有限公司 | Deep etching method for high-voltage LED chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8772138B2 (en) | High voltage light emitting diode chip and its manufacturing method | |
| CN101814564B (en) | Method for preparing epitaxial growing nano pattern substrate of nitride | |
| CN101515624B (en) | Method for manufacturing LED chips | |
| WO2007123289A1 (en) | High efficiency led with multi-layer reflector structure and method for fabricating the same | |
| CN113571609A (en) | Double ISO process for high-voltage LED chip | |
| CN109904285A (en) | A kind of light-emitting diode chip for backlight unit and its manufacturing method | |
| CN103413875B (en) | A kind of preparation method of PN step of PN step, LED chip and LED chip of LED chip | |
| TW201505206A (en) | Light emitting diode and method of producing the same | |
| US20130316476A1 (en) | Manufacturing method of a retaining wall of an LED | |
| CN105137725A (en) | Multi-exposure-based graph making method | |
| CN105607411B (en) | A kind of reticle and the method using reticle production light emitting diode | |
| CN112349818B (en) | Deep etching method for high-voltage LED chip | |
| US10649338B2 (en) | Stepped wafer and method for manufacturing stepped wafer | |
| CN103633198B (en) | LED chip manufacture method and LED chip | |
| CN101354528B (en) | Mask and related photo-etching method | |
| CN111697020A (en) | Preparation method of high-voltage LED chip | |
| TWI817630B (en) | Light-emitting device array substrate and method for fabricating the same | |
| KR20130118721A (en) | Led chip, led, and a method for manufacturing led chip | |
| CN103904175B (en) | There is the manufacture method of waveguiding structure photonic crystal light-emitting diode | |
| CN205406554U (en) | Figure sapphire substrate of luminous angle of adjustable LED | |
| CN104347772B (en) | The complete engraving method and LED chip preparation method of ITO | |
| CN115763351A (en) | Light emitting element array substrate and method for manufacturing same | |
| KR20180094751A (en) | Semiconductor device | |
| CN105552175B (en) | Without encapsulation LED flashing lights, its driving chip and preparation method | |
| CN114864774B (en) | Preparation method of patterned substrate and LED epitaxial structure with air gap |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |