CN112349818B - Deep etching method for high-voltage LED chip - Google Patents
Deep etching method for high-voltage LED chip Download PDFInfo
- Publication number
- CN112349818B CN112349818B CN202011163378.5A CN202011163378A CN112349818B CN 112349818 B CN112349818 B CN 112349818B CN 202011163378 A CN202011163378 A CN 202011163378A CN 112349818 B CN112349818 B CN 112349818B
- Authority
- CN
- China
- Prior art keywords
- deep etching
- led chip
- voltage led
- etching method
- positive photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/813—Bodies having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
- H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
Landscapes
- Led Devices (AREA)
Abstract
The invention provides a deep etching method of a high-voltage LED chip, which comprises the steps of carrying out deep etching treatment on a bridging part and a cutting channel of the high-voltage LED chip by taking a positive photoresist with a preset angle inclined plane as a mask after twice spin coating, twice exposure, twice development and the like, and simultaneously carrying out deep etching treatment on a non-bridging part of the high-voltage LED chip by taking a negative photoresist with a vertical plane as a mask. The method has the advantages that the isolation grooves with different angles and different line widths are etched in a deep mode at one time, full-etching processing is achieved under the condition that the width of a cutting channel is not changed, and a certain chamfer is formed, so that the ratio of the luminous area of a high-voltage LED chip is effectively increased, the light emitting efficiency of the chip is increased, and the COW is not required to be provided with a special test chip.
Description
Technical Field
The invention relates to the technical field of LEDs, in particular to a deep etching method of a high-voltage LED chip.
Background
A Light Emitting Diode (LED) is a semiconductor Light Emitting device, and can convert electrical energy into Light energy by using the P-N junction electroluminescence principle of a semiconductor, and has the advantages of small size, low power consumption, long service life, and the like, and is widely used in the fields of lighting of various scenes, backlight, car lights, and the like.
With the continuous development of the industry, a novel High Voltage (HV) LED chip is receiving attention, and compared with a common LED, an integrated High Voltage LED can reduce the packaging cost, reduce the number of elements and the number of solder joints, has higher reliability, and has small current, High Voltage, no need of large-amplitude Voltage conversion, small Voltage transformation loss, simple driving design, and low heat dissipation requirement.
However, the current high-voltage LED chip has a low light-emitting area ratio, which results in low light-emitting efficiency.
Disclosure of Invention
In view of the above, in order to solve the above problems, the present invention provides a deep etching method for a high voltage LED chip, which has the following technical scheme:
a deep etching method of a high-voltage LED chip comprises the following steps:
providing a substrate, wherein an epitaxial layer is arranged on the substrate, the epitaxial layer at least comprises an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer in a first direction, and the first direction is perpendicular to the substrate and is directed to the epitaxial layer from the substrate;
etching the epitaxial layer based on the serial stage requirement of the high-voltage LED chip, exposing the N-type semiconductor layer, and forming a cutting channel and an isolation groove;
spin-coating a positive photoresist on one side of the epitaxial layer, which is far away from the substrate, and performing at least exposure, development and hardening operation on the positive photoresist, so that the regions, located on the cutting streets and the isolation trenches, of the positive photoresist are inclined planes with preset angles, and part of the cutting streets and part of the isolation trenches are exposed;
spin-coating a negative photoresist on one side of the positive photoresist, which is far away from the substrate, and performing at least exposure, development and hardening operation on the negative photoresist, so that the region, which is located at the non-bridging position of the high-voltage LED chip, of the negative photoresist is a groove with a vertical surface, and the positive photoresist with the preset angle inclined plane is exposed at the bridging position of the high-voltage LED chip and the region of the cutting channel;
and taking the positive photoresist with the preset angle inclined plane as a mask, carrying out deep etching treatment on the bridging part of the high-voltage LED chip and the cutting channel, and taking the negative photoresist with a vertical surface as a mask, and simultaneously carrying out deep etching treatment on the non-bridging part of the high-voltage LED chip.
Optionally, in the deep etching method, the thickness of the positive photoresist is 10um to 18 um.
Optionally, in the deep etching method, the deep etching method further includes:
before the positive photoresist is exposed, soft baking is carried out on the positive photoresist;
wherein the soft baking temperature is 90-100 ℃, and the soft baking time is 100-300 s.
Optionally, in the deep etching method, the exposure amount to the positive photoresist is 270mj to 400 mj;
the developing time of the positive photoresist is 20s-160 s;
the film hardening temperature of the positive photoresist is 100-140 ℃, and the film hardening time is 15-40 min.
Optionally, in the deep etching method, the deep etching method further includes:
after the negative photoresist is exposed, baking the negative photoresist;
wherein the baking temperature is 90-100 ℃, and the baking time is 100-300 s.
Optionally, in the deep etching method, the exposure amount to the negative photoresist is 100mj to 200 mj;
the developing time for the negative photoresist is 60s-100 s.
Optionally, in the deep etching method, the preset angle is 40 ° to 60 °.
Optionally, in the deep etching method, after the deep etching process is completed, the width of the upper bottom of the bridge joint of the high-voltage LED chip is 15um to 25um, and the width of the lower bottom is 6um to 12 um.
Optionally, in the deep etching method, after the deep etching process is completed, the width of the upper bottom of the non-bridge part of the high-voltage LED chip is 4um to 6um, and the width of the lower bottom is 4um to 6 um.
Optionally, in the deep etching method, after the deep etching process is completed, the width of the upper bottom of the high-voltage LED chip cutting street is 10 μm to 16 μm, and the width of the lower bottom is 3 μm to 6 μm.
Compared with the prior art, the invention has the following beneficial effects:
the deep etching method for the high-voltage LED chip provided by the invention adopts operations of twice glue homogenizing, twice exposure, twice development and the like, then carries out deep etching treatment on the bridging position and the cutting street of the high-voltage LED chip by taking the positive photoresist with the preset angle inclined plane as a mask, and simultaneously carries out deep etching treatment on the non-bridging position of the high-voltage LED chip by taking the negative photoresist with the vertical plane as a mask. The method has the advantages that the isolation grooves with different angles and different line widths are etched in a deep mode at one time, full-etching processing is achieved under the condition that the width of a cutting channel is not changed, and a certain chamfer is formed, so that the ratio of the luminous area of a high-voltage LED chip is effectively increased, the light emitting efficiency of the chip is increased, and the COW is not required to be provided with a special test chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic flow chart of a deep etching method for a high-voltage LED chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a mesa lithographic pattern according to an embodiment of the present invention;
fig. 3 is a schematic diagram after an epitaxial layer mesa etching process according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an effect of a positive photoresist after the processing is completed according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an effect of a negative photoresist after processing is completed according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a high-voltage LED chip according to an embodiment of the present invention after deep etching;
fig. 7 is a schematic diagram of a high-voltage LED chip bridge after deep etching of an isolation trench provided in an embodiment of the present invention;
fig. 8 is a schematic diagram of a high-voltage LED chip after deep etching of an isolation trench at a non-bridge location according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a high-voltage LED chip after a scribe line is etched back according to an embodiment of the present invention;
fig. 10 is a schematic diagram of specific parameters after deep etching of an isolation trench at a bridge of a high-voltage LED chip according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of specific parameters of a high-voltage LED chip after deep etching of an isolation trench at a non-bridge junction according to an embodiment of the present invention;
fig. 12 is a schematic diagram of specific parameters of a high-voltage LED chip after deep etching of a scribe line provided in an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The high-voltage LED chip is formed by dividing a prepared epitaxial layer into a plurality of independent core particles which are connected in series through deep etching grooves, and can achieve higher power under the drive of small current.
High-voltage products with different driving voltages can be prepared according to the number of connected core particle units, for example, 2, 3 or 6 core particles are connected in series, and the voltage can reach about 6V/9V/18V respectively.
That is to say, in the manufacturing process of the high-voltage LED chip, the epitaxial GaN layer between the adjacent core particle units needs to be etched cleanly through a deep etching process until reaching the substrate, the etching depth of the epitaxial layer is generally 5um-7um, an insulating layer needs to be deposited above the groove, and metal electrodes are evaporated on the surface of the insulating layer to bridge and connect the adjacent core particle units in series.
In order to completely cover the electrodes at the groove bridging part, the bevel angle of the isolation groove needs to be reasonably set, and when the bevel angle of the isolation groove is too large, the electrode coverage is poor, cracks and even faults are easily generated, and therefore the high-voltage LED chip fails.
However, in order to ensure the reliability of the high-voltage LED chip, the bevel edge of the isolation trench needs to be large enough, and then the GaN area needs to be etched more, which results in a smaller light-emitting area of the high-voltage LED chip, and further reduces the light-emitting efficiency of the high-voltage LED chip.
In addition, at present, the scribe lines of the high-voltage LED chip are not etched deeply, so that a test core particle needs to be manufactured during the COW test, and the core particle needs to be etched away from other core particles and has a smaller size than other core particles, so that when a final product is formed after the test is finished, the test core particle cannot be taken off line as a product, but is discarded as a waste product, thereby losing the yield of the chip.
In the prior art, some technical means are deep etching by adopting a hard mask mode, although the light emitting area of the high-voltage LED chip can be effectively improved, the manufacturing process is complex, and the hard mask is deposited on the epitaxial layer for a long time, so that the damage of a P-type GaN layer can be aggravated, the reliability of the high-voltage LED chip is reduced, and the problem of voltage increase can be caused.
Based on the above, the embodiment of the invention provides a deep etching method for a high-voltage LED chip, which comprises the steps of performing operations such as twice photoresist evening, twice exposure, twice development and the like, namely, performing uniform positive photoresist-soft baking, exposure-development-hardening-uniform negative photoresist-exposure-postbaking, development-deep etching, performing deep etching treatment on a bridge joint and a cutting street of the high-voltage LED chip by using the positive photoresist with the preset angle inclined plane as a mask, and performing deep etching treatment on a non-bridge joint of the high-voltage LED chip by using the negative photoresist with a vertical plane as a mask. The method has the advantages that the isolation grooves with different angles and different line widths are etched in a deep mode at one time, full-etching processing is achieved under the condition that the width of a cutting channel is not changed, and a certain chamfer is formed, so that the ratio of the luminous area of a high-voltage LED chip is effectively increased, the light emitting efficiency of the chip is increased, and the COW is not required to be provided with a special test chip.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic flow chart of a deep etching method for a high-voltage LED chip according to an embodiment of the present invention.
The deep etching method comprises the following steps:
s101: providing a substrate, wherein an epitaxial layer is arranged on the substrate, the epitaxial layer at least comprises an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer in a first direction, and the first direction is perpendicular to the substrate and is directed to the epitaxial layer from the substrate.
In this step, the substrate includes, but is not limited to, a sapphire substrate, the N-type semiconductor layer is an N-type GaN layer, and the P-type semiconductor layer is a P-type GaN layer.
S102: and etching the epitaxial layer based on the serial stage requirement of the high-voltage LED chip, exposing the N-type semiconductor layer, and forming a cutting channel and an isolation groove.
In this step, referring to fig. 2, fig. 2 is a schematic diagram of a mesa lithographic pattern provided in an embodiment of the present invention, and the epitaxial layer is cleaned, and is subjected to spin coating, exposure and development to prepare the mesa lithographic pattern.
Referring to fig. 3, fig. 3 is a schematic diagram of an epitaxial layer mesa after being etched according to an embodiment of the present invention, which includes but is not limited to etching a mesa region by using an ICP (inductively Coupled Plasma) process, and removing a photoresist.
As shown in fig. 3, the present example is described by taking 3 core particles connected in series as an example.
S103: and spin-coating a positive photoresist on one side of the epitaxial layer, which is far away from the substrate, and performing at least exposure, development and hardening operation on the positive photoresist, so that the positive photoresist is positioned in the cutting channel and the isolation groove, and the area of the positive photoresist is an inclined plane with a preset angle, and part of the cutting channel and part of the isolation groove are exposed.
In this step, a positive photoresist is spin-coated on the epitaxial layer etched to form the mesa region, and after soft baking, exposing, developing and hardening, referring to fig. 4, fig. 4 is a diagram illustrating an effect after the positive photoresist is processed according to an embodiment of the present invention.
Based on the characteristics of the positive photoresist, the area of the positive photoresist, which is located in the scribe line and the isolation trench, is an inclined plane with a preset angle, and a part of the scribe line and a part of the isolation trench are exposed.
It should be noted that the size of the preset angle is mainly related to the parameters of the firm film.
S104: and spin-coating a negative photoresist on one side of the positive photoresist, which is deviated from the substrate, and at least performing exposure, development and film hardening operation on the negative photoresist so as to enable the region, which is positioned at the non-bridging part of the high-voltage LED chip, of the negative photoresist to be a groove with a vertical surface, and expose the positive photoresist with the preset angle inclined plane at the bridging part of the high-voltage LED chip and the region of the cutting channel.
In this step, after the positive photoresist is processed, a negative photoresist is spin-coated, and the negative photoresist at least covers the scribe line and the isolation trench, and after exposure-post-baking-development, referring to fig. 5, fig. 5 is a graph of an effect after the negative photoresist is processed according to an embodiment of the present invention.
The area of the negative photoresist at the non-bridging position of the high-voltage LED chip is a groove with a vertical surface, and the positive photoresist with the preset angle inclined plane is exposed at the bridging position of the high-voltage LED chip and the area of the cutting channel.
S105: and taking the positive photoresist with the preset angle inclined plane as a mask, carrying out deep etching treatment on the bridging part of the high-voltage LED chip and the cutting channel, and taking the negative photoresist with a vertical surface as a mask, and simultaneously carrying out deep etching treatment on the non-bridging part of the high-voltage LED chip.
Referring to fig. 6, fig. 6 is a schematic diagram of a high-voltage LED chip provided in an embodiment of the present invention after deep etching.
In this step, referring to fig. 7, fig. 7 is a schematic diagram after deep etching of an isolation trench at a bridge joint of a high-voltage LED chip according to an embodiment of the present invention, referring to fig. 8, fig. 8 is a schematic diagram after deep etching of an isolation trench at a non-bridge joint of a high-voltage LED chip according to an embodiment of the present invention, referring to fig. 9, and fig. 9 is a schematic diagram after deep etching of a scribe line of a high-voltage LED chip according to an embodiment of the present invention.
That is to say, according to the deep etching method for the high-voltage LED chip provided by the embodiment of the present invention, after operations such as twice spin coating, twice exposure, twice development, and the like are performed, that is, after a uniform positive photoresist, a soft baking operation, an exposure operation, a development operation, a hard film formation operation, a uniform negative photoresist, an exposure operation, a post baking operation, a development operation, and a deep etching operation are performed, the bridge connection position and the cutting street of the high-voltage LED chip are subjected to the deep etching operation with the positive photoresist having the preset angle inclined plane as a mask, and the non-bridge connection position of the high-voltage LED chip is subjected to the deep etching operation with the negative photoresist having the vertical plane as a mask. The method has the advantages that the isolation grooves with different angles and different line widths are etched in a deep mode at one time, full-etching processing is achieved under the condition that the width of a cutting channel is not changed, and a certain chamfer is formed, so that the ratio of the luminous area of a high-voltage LED chip is effectively increased, the light emitting efficiency of the chip is increased, and the COW is not required to be provided with a special test chip.
Further, according to the above embodiment of the present invention, the thickness of the positive photoresist is 10um to 18 um.
In this embodiment, the thickness of the positive photoresist is 12um or 15um or 17um, etc.
Further, based on the above embodiment of the present invention, the deep etching method further includes:
and before the positive photoresist is exposed, carrying out soft baking treatment on the positive photoresist.
Wherein the soft baking temperature is 90-100 ℃, and the soft baking time is 100-300 s.
In this embodiment, the soft baking temperature is 92 ℃ or 96 ℃ or 99 ℃ or the like, and the soft baking time is 132s or 147s or 278s or the like.
Further, according to the above embodiment of the present invention, the exposure amount for the positive photoresist is 270mj to 400 mj.
The developing time for the positive photoresist is 20s-160 s.
The film hardening temperature of the positive photoresist is 100-140 ℃, and the film hardening time is 15-40 min.
In this embodiment, the exposure amount is 281mj or 312mj or 380mj, or the like.
The development time is 24s or 89s or 154s, etc.
The film hardening temperature is 112 ℃, 129 ℃, 132 ℃ or the like, and the film hardening time is 17min, 23min, 36min or the like.
Further, based on the above embodiment of the present invention, the deep etching method further includes:
and after the negative photoresist is exposed, baking the negative photoresist.
Wherein the baking temperature is 90-100 ℃, and the baking time is 100-300 s.
In this embodiment, the baking temperature is 92 ℃ or 94 ℃ or 97 ℃ or the like, and the baking time is 120s or 231s or 279s or the like.
Further, according to the above embodiment of the present invention, the exposure amount for the negative photoresist is 100mj to 200 mj.
The developing time for the negative photoresist is 60s-100 s.
In this embodiment, the exposure amount of the negative photoresist is 116mj or 156mj or 179mj, etc.
The developing time of the negative photoresist is 66s or 81s or 93s and the like.
Further, according to the above embodiment of the present invention, the preset angle is 40 ° to 60 °.
In the embodiment, the specific preset angle is set based on different epitaxial layer thicknesses so as to improve the reliability of electrode coverage, avoid cracks and even faults, and improve the reliability of the high-voltage LED chip.
Further, based on the above embodiments of the present invention, referring to fig. 10, fig. 10 is a schematic diagram of specific parameters after deep etching of the isolation trench at the bridge of the high-voltage LED chip according to the embodiments of the present invention.
After the deep etching treatment is finished, the width of the upper bottom of the bridge joint of the high-voltage LED chip is 15um-25um, and the width of the lower bottom is 6um-12 um.
In this embodiment, the width of the upper bottom at the bridge of the high-voltage LED chip is 17um or 21um, etc., and the width of the lower bottom is 8um or 11um, etc.
Further, based on the above embodiments of the present invention, referring to fig. 11, fig. 11 is a schematic diagram of specific parameters after deep etching of the isolation trench at the non-bridge position of the high-voltage LED chip according to the embodiments of the present invention.
After the deep etching treatment is finished, the width of the upper bottom of the non-bridging part of the high-voltage LED chip is 4um-6um, and the width of the lower bottom is 4um-6 um.
In this embodiment, the width of the upper bottom at the non-bridge position of the high-voltage LED chip is 4.3um or 5um, etc., and the width of the lower bottom is 4.3um or 5um, etc.
Further, based on the above embodiment of the present invention, referring to fig. 12, fig. 12 is a schematic diagram of specific parameters of the high-voltage LED chip after the scribe line is etched back according to the embodiment of the present invention.
After the deep etching treatment is finished, the upper bottom width of the high-voltage LED chip cutting channel is 10-16 μm, and the lower bottom width is 3-6 μm.
In this embodiment, the width of the upper bottom of the high-voltage LED chip dicing street is 11 μm, 14 μm, 15 μm or the like, and the width of the lower bottom is 3.5 μm, 4.3 μm, 5 μm or the like.
Further, based on the above embodiment of the present invention, after the deep etching is completed, the process for preparing the high voltage LED chip at least further includes:
after deep etching, removing the positive photoresist and the negative photoresist;
thereafter, the region of the isolation trench exposed by the substrate includes, but is not limited to, a PECVD deposited insulating layer, which includes, but is not limited to, SiO2An insulating layer.
And etching the insulating layer by a wet method by using the positive photoresist as a mask to form a preset insulating pattern, and removing the positive photoresist after etching.
And depositing a transparent conductive thin film layer on the corresponding film layer on one side of the substrate by a sputtering process.
And annealing the transparent conductive film layer through a rapid annealing furnace.
And etching the transparent conductive film layer by using a positive photoresist as a mask through a wet method to form a preset transparent conductive film layer pattern, and removing the positive photoresist after etching.
And (3) adopting negative photoresist as a mask, carrying out metal evaporation through electron beam evaporation, and stripping and removing the negative photoresist after the metal evaporation.
It should be noted that the present invention is only a simple introduction of the subsequent process of the high voltage LED chip, and the core of the present invention is still the deep etching process in the high voltage LED chip manufacturing process.
As can be seen from the above description, the deep etching method for the high voltage LED chip provided by the present invention is a photolithography mask preparation process for isolation trench etching, which comprises two steps of photoresist spreading and two steps of exposure and development: the method comprises the steps of uniform positive photoresist → soft baking → first exposure → first development → hard film → second uniform negative photoresist → second exposure → baking after baking tray exposure → second development → deep etching.
Compared with the hard mask process: the method can achieve the same effect as a hard mask process under the condition of hardly increasing the cost, namely, the oblique angle of the groove at the bridging position is wide enough to ensure that the electrode is completely covered, but the groove at the non-bridging position can be etched to form a right angle, so that the top width of the groove is greatly reduced under the condition of ensuring that the bottom width is the same, and the ratio of the light-emitting area is effectively improved. In addition, the cutting channels are deeply etched under the condition that the width size is not changed, all chips are isolated, special test core particles do not need to be manufactured on the COW, and the yield of the chips is improved. And the N-GaN section of the cutting channel is provided with a fixed chamfer angle, so that the light emitting efficiency of the chip is improved, and the light efficiency is improved.
The method for deep etching of the high-voltage LED chip provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained herein by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011163378.5A CN112349818B (en) | 2020-10-27 | 2020-10-27 | Deep etching method for high-voltage LED chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011163378.5A CN112349818B (en) | 2020-10-27 | 2020-10-27 | Deep etching method for high-voltage LED chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112349818A CN112349818A (en) | 2021-02-09 |
| CN112349818B true CN112349818B (en) | 2022-02-22 |
Family
ID=74360226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011163378.5A Active CN112349818B (en) | 2020-10-27 | 2020-10-27 | Deep etching method for high-voltage LED chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112349818B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571609A (en) * | 2021-07-21 | 2021-10-29 | 江西兆驰半导体有限公司 | A high-voltage LED chip double ISO process |
| CN115064616B (en) * | 2022-06-02 | 2025-03-25 | 福建兆元光电有限公司 | A method for increasing the etching angle of LED chips |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733573B (en) * | 2015-03-31 | 2017-12-08 | 湘能华磊光电股份有限公司 | High-voltage LED and preparation method thereof |
| CN107658372A (en) * | 2017-09-21 | 2018-02-02 | 山西飞虹微纳米光电科技有限公司 | Deep etching Cutting Road flip LED chips and preparation method, LED display |
| CN111293200A (en) * | 2018-12-07 | 2020-06-16 | 大连德豪光电科技有限公司 | LED high-voltage chip, preparation method thereof and manufacturing method of isolation groove |
| CN109817779B (en) * | 2019-02-02 | 2020-08-14 | 厦门乾照光电股份有限公司 | Manufacturing method of high-voltage LED chip structure |
| CN110808318B (en) * | 2019-11-11 | 2021-04-27 | 厦门乾照光电股份有限公司 | A flip-chip high-voltage light-emitting diode and its manufacturing method |
-
2020
- 2020-10-27 CN CN202011163378.5A patent/CN112349818B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112349818A (en) | 2021-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI610459B (en) | Miniature light emitting diode device and manufacturing method thereof | |
| CN112349818B (en) | Deep etching method for high-voltage LED chip | |
| CN103219352B (en) | LED combination chip of array architecture and preparation method thereof | |
| CN102867837A (en) | Manufacture method of array type high-voltage LED device | |
| CN110459657B (en) | A micro-sized LED device with an annular Y-shaped electrode and a preparation method thereof | |
| TW201411875A (en) | Method for growing III-V compound layer on substrate and semiconductor device and illumination device having the same III-V compound layer | |
| CN113363360B (en) | LED chip with vertical structure and manufacturing method thereof | |
| CN114551680A (en) | Flip light-emitting diode chip and preparation method thereof | |
| CN113314650B (en) | Light emitting diode chip capable of improving lateral light-emitting intensity and manufacturing method thereof | |
| CN105514230B (en) | GaN base LED vertical chip structure and preparation method thereof | |
| TW202046523A (en) | Flip chip led and manufacturing method thereof | |
| CN113299803A (en) | Preparation method of Micro LED chip single device, display module and display device | |
| CN116759513A (en) | A mirror-covered structure reverse polarity red LED chip and its production method | |
| CN112968083B (en) | Method for manufacturing light emitting device | |
| CN103647010B (en) | A kind of preparation method of high-power LED chip | |
| CN214898480U (en) | Micro LED chip monomer device, display module and display device | |
| CN105206573B (en) | A kind of light-emitting diodes tube preparation method | |
| CN111697020A (en) | Preparation method of high-voltage LED chip | |
| CN106848027B (en) | The preparation method of the vertical flip LED chips of high reliability | |
| CN210607303U (en) | A micro-sized LED device with annular Y-like electrode | |
| CN102651438A (en) | Substrate, preparation method thereof and chip with substrate | |
| CN116387413A (en) | Preparation method of LED chip and LED chip | |
| CN101438422A (en) | Laser-lifted light-emitting diodes with improved light extraction | |
| CN105607411B (en) | A kind of reticle and the method using reticle production light emitting diode | |
| CN105244420A (en) | Manufacturing method of GaN-based light emitting diode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A Deep Etching Method for High Voltage LED Chips Granted publication date: 20220222 Pledgee: Jiujiang Bank Co.,Ltd. Nanchang Branch Pledgor: JIANGXI QIANZHAO PHOTOELECTRIC CO.,LTD. Registration number: Y2024980001944 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20220222 Pledgee: Jiujiang Bank Co.,Ltd. Nanchang Branch Pledgor: JIANGXI QIANZHAO PHOTOELECTRIC CO.,LTD. Registration number: Y2024980001944 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right |