CN111293200A - LED high-voltage chip, preparation method thereof and manufacturing method of isolation groove - Google Patents
LED high-voltage chip, preparation method thereof and manufacturing method of isolation groove Download PDFInfo
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Abstract
The invention relates to an LED high-voltage chip, a preparation method thereof and a manufacturing method of an isolation groove. The manufacturing method of the isolation groove comprises the following steps: providing an LED chip main body comprising a substrate and a light emitting semiconductor layer arranged on the substrate; forming a first barrier layer provided with a first penetrating opening and a second barrier layer provided with a second penetrating opening on the light-emitting semiconductor layer, wherein the inclination angle between the side edge of the first opening and the substrate is smaller than the inclination angle between the side edge of the second opening and the substrate, and the first opening and the second opening are arranged in parallel; and etching the light-emitting semiconductor layer to form an isolation groove, wherein the isolation groove comprises a first groove body and a second groove body, and the inclination angle between the side wall of the first groove body and the substrate is smaller than the inclination angle between the side wall of the second groove body and the substrate. The invention can realize different angle requirements at different positions of the isolation groove by one-time etching process, and can save about 30% of cost. Meanwhile, the light emitting area of the LED high-voltage chip can be increased by 10-30%, and the brightness can be improved by about 5%.
Description
Technical Field
The invention relates to the technical field of LED chips, in particular to an LED high-voltage chip and a preparation method thereof, and a manufacturing method of an isolation groove.
Background
The working voltage of the conventional LED chip is about 3V, and in order to access a national power grid with 220V voltage, a voltage reduction device needs to be added, but the power consumption is about 10% and the cost is increased. In order to directly access 220V voltage, the conventional method is to connect dozens of LED conventional chips in series, but the cost is increased. Therefore, the design of the LED high-voltage chip can greatly reduce the cost.
In the preparation of LED high voltage chips, the most important step is the method of dividing the light emitting semiconductor layer of the chip into individual light emitting semiconductor units. In the conventional method, the GaN layer of the light emitting semiconductor layer is etched to form independent light emitting semiconductor units which are isolated from each other and share the substrate, and then a conductive connection layer is prepared between the independent light emitting semiconductor units by an evaporation/sputtering method, so that the independent light emitting semiconductor units are connected in series. At present, in order to ensure that the conductive connection layer is not broken when the high-voltage chip is connected in series, the etching angle of the traditional high-voltage chip is controlled below 50 degrees, but the smaller the etching angle is, the more the light-emitting area is occupied, so that the light-emitting area is lost by about 20% on average in the manufacturing process. To reduce the loss, it is reported that two etching angles are formed by performing two etching processes, but the cost of the etching process is high, and the cost is increased again.
Disclosure of Invention
Therefore, it is necessary to provide an LED high-voltage chip, a method for manufacturing the LED high-voltage chip, and a method for manufacturing an isolation trench, in order to solve the problems of light-emitting area and cost of the high-voltage chip.
A manufacturing method of an LED high-voltage chip isolation groove comprises the following steps:
providing an LED chip main body, wherein the LED chip main body comprises a substrate and a light-emitting semiconductor layer arranged on the substrate;
forming a first barrier layer and a second barrier layer on the light-emitting semiconductor layer, wherein the first barrier layer is provided with a first penetrating opening, the second barrier layer is provided with a second penetrating opening, an inclination angle between the side edge of the first opening and the substrate is smaller than an inclination angle between the side edge of the second opening and the substrate, and the first opening and the second opening are arranged in parallel;
and etching the light-emitting semiconductor layer to form an isolation groove, wherein the isolation groove comprises a first groove body and a second groove body, and the inclination angle between the side wall of the first groove body and the substrate is smaller than the inclination angle between the side wall of the second groove body and the substrate.
In one embodiment, the side of the first opening includes a first side a and a second side b oppositely disposed, and the inclination angle between the first side a and the substrate is set to α1' the inclination angle between the second side edge b and the substrate is set to α2′，α1' and α2' are all 20 to 50 degrees; and/or
The side of the second opening comprises a second side a and a second side b which are oppositely arranged, and the inclination angle between the second side a and the substrate is set to β1' the inclination angle between the second side edge b and the substrate is set to β2′，β1' and β2' are all 60-90 degrees.
In one embodiment, the first barrier layer is formed by exposing, developing and baking a first photoresist.
In one embodiment, the material of the second barrier layer includes at least one of a metal, a metal oxide, a silicon compound, and a second photoresist.
In one embodiment, when the material of the second barrier layer includes at least one of a metal, a metal oxide, and a silicon compound, the second barrier layer is first formed on the light-emitting semiconductor layer, and then the first barrier layer is formed;
when the material of the second barrier layer is the second photoresist, the first barrier layer is firstly manufactured and formed on the light-emitting semiconductor layer, and then the second barrier layer is manufactured and formed.
In one embodiment, when the material of the second barrier layer is a second photoresist, the baking temperature for forming the second barrier layer is less than or equal to the baking temperature for forming the first barrier layer.
In one embodiment, the first barrier layer and the second barrier layer each have a thickness of 1 μm to 12 μm.
In one embodiment, the light emitting semiconductor layer includes an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer sequentially disposed on the substrate, and the light emitting semiconductor layer is etched to expose a portion of the N-type semiconductor layer before the first barrier layer and the second barrier layer are formed on the light emitting semiconductor layer.
A preparation method of an LED high-voltage chip comprises the following steps:
etching an isolation groove on an LED chip main body by adopting any one of the manufacturing methods of the LED high-voltage chip isolation groove, wherein the isolation groove isolates a light-emitting semiconductor layer into a plurality of light-emitting semiconductor units;
etching any side wall of the first groove body to form a notch extending from the P-type semiconductor layer to the N-type semiconductor layer;
forming an insulating layer on the first groove body, and exposing a gap part extending from the P-type semiconductor layer to the N-type semiconductor layer;
forming a transparent electrode on the surface of the P-type semiconductor layer of the light-emitting semiconductor unit;
and forming a conductive connecting layer on the insulating layer so that the transparent electrode is connected with the N-type semiconductor layer exposed at the gap of the adjacent light-emitting semiconductor unit to connect the adjacent light-emitting semiconductor units in series.
An LED high-voltage chip comprises a substrate, a plurality of luminous semiconductor units arranged on the substrate, and a conductive connecting layer, wherein the luminous semiconductor units are isolated by an isolation groove, the isolation groove comprises a first groove body and a second groove body, wherein,
the first groove body comprises a first side wall a and a first side wall b which are oppositely arranged, and the inclination angle between the first side wall a and the substrate is set to α1The inclination angle between the first sidewall b and the substrate is set to α2，α1And α2The angle of inclination between the second side wall a and the substrate is β1The inclination angle between the second sidewall b and the substrate is set to β2，β1And β2The conductive connecting layer extends along the side wall of the first groove body and is connected with the adjacent light-emitting semiconductor units in series.
According to the invention, the first barrier layer and the second barrier layer are simultaneously formed on the light-emitting semiconductor layer, so that the isolation groove can be manufactured by one-time etching process, and about 30% of cost can be saved. Meanwhile, the side walls of the first groove body and the second groove body of the manufactured isolation groove are inclined at different angles with the substrate, the conductive connecting layer is deposited on the first groove body with the smaller inclination angle to realize series connection of the luminous semiconductor units, the luminous area of the LED high-voltage chip can be increased by 10% -30%, the brightness is improved by about 5%, the covering performance of the conductive connecting layer is guaranteed, and the reliability is improved.
Drawings
FIG. 1 is a schematic structural diagram of an LED chip body;
FIG. 2 is a schematic structural diagram of a first barrier layer and a second barrier layer formed on the LED chip body of FIG. 1;
FIG. 3 is a schematic structural diagram of an isolation trench etched in an LED chip body;
FIG. 4 is a top view of FIG. 3;
FIG. 5 is a schematic structural diagram of etching the LED chip body to expose part of the N-type semiconductor layer;
FIG. 6 is a schematic diagram of a structure of forming a first barrier layer and a second barrier layer on the LED chip body of FIG. 5;
FIG. 7 is a schematic structural diagram of a side wall of a first groove body of an LED high-voltage chip after a notch is formed by etching;
fig. 8 is a cross-sectional view of the LED high-voltage chip along the first groove.
In the figure: 10. a substrate; 20. a light-emitting semiconductor layer; 30. a first barrier layer; 40. a second barrier layer; 50. a light emitting semiconductor unit; 60. a first tank body; 70. a second tank body; 100. an insulating layer; 101. a conductive connection layer; 102. a transparent electrode; 103. an insulating protective layer; 201. an N-type semiconductor layer; 202. a light emitting layer; 203. a P-type semiconductor layer; 204. a notch; 300. a first opening; 301. a first side edge a; 302. a first side edge b; 400. a second opening; 401. a second side a; 402. a second side edge b; 601. a first side wall a; 602. a first side wall b; 701. a second side wall a; 702. a second side wall b.
Detailed Description
The LED high-voltage chip and the manufacturing method thereof, and the manufacturing method of the isolation trench provided by the present invention will be further described below.
Referring to fig. 1 to 4, the method for manufacturing the LED high voltage chip provided by the present invention includes the following steps:
s1, providing an LED chip body including a substrate 10 and a light emitting semiconductor layer 20 disposed on the substrate;
s2, forming a first barrier layer 30 and a second barrier layer 40 on the light emitting semiconductor layer 20, wherein the first barrier layer 30 is provided with a first through opening 300, the second barrier layer 40 is provided with a second through opening 400, an inclination angle between a side edge of the first opening 300 and the substrate 10 is smaller than an inclination angle between a side edge of the second opening 400 and the substrate 10, and the first opening 300 and the second opening 400 are arranged in parallel;
and S3, etching the light-emitting semiconductor layer 20 to form an isolation groove, wherein the isolation groove comprises a first groove body 60 and a second groove body 70, and the inclination angle between the side wall of the first groove body 60 and the substrate 10 is smaller than the inclination angle between the side wall of the second groove body 70 and the substrate 10.
Referring to fig. 1 in particular, the light emitting semiconductor layer 20 in step S1 includes an N-type semiconductor layer 201, a light emitting layer 202, and a P-type semiconductor layer 203 sequentially disposed on the substrate 10.
Referring to fig. 2 and 3 in particular, the side of the first opening 300 in step S2 includes a first side a301 and a first side b 302 oppositely disposed, and the inclination angle between the first side a301 and the substrate 10 is set to α1' the inclination angle between the first side b 302 and the substrate 10 is set to α2′，α1' and α2' are all 20-50 degrees.
In the etching process, the first barrier layer 30 is used to protect the light emitting semiconductor layer 20, so that the first groove 60 is etched, in consideration of uniformity and stability of the etching process, after etching, an inclination angle between the side wall of the first groove 60 and the substrate 10 is substantially equal to an inclination angle between the side edge of the first barrier layer 30 and the substrate 10, and the first groove 60 is mainly used to deposit a conductive connection layer, so that, in order to ensure the coating effect and reliability of the conductive connection layer, it is preferable that α is used to ensure the coating effect and reliability of the conductive connection layer1' and α2' are all 30-40 degrees.
Further, α1′＝α2', the first side edge a301 and the first side edge b 302 are axially symmetric along the central axis of the first opening 300.
In addition, the shortest distance between the first side a301 and the first side b 302 is d1′，d1′＞0。
The side of the second opening 400 includes a second side a401 and a second side b 402 which are oppositely disposed, and the inclination angle between the second side a401 and the substrate 10 is set to β1', the second side edge b 402 and the linerThe inclination angle between the bases 10 is set to β2′，β1' and β2' are all 60-90 degrees.
The second barrier layer 40 serves to protect the light emitting semiconductor layer 20 during the etching process, so that the second groove 70 is etched, and after the etching process, the inclination angle between the sidewall of the second groove 70 and the substrate 10 is substantially equal to the inclination angle between the side of the second barrier layer 40 and the substrate 10, and the second groove 70 serves to isolate the light emitting semiconductor unit 50, and thus, it is preferable that β is formed in consideration of the light emitting area, because the etching process is uniform and stable1' and β2' are all 70-80 degrees.
Further, β1′＝β2', the second side a401 and the second side b 402 are axially symmetric along the central axis of the second opening 400.
Preferably, the central axis of the first opening 300 is collinear with the central axis of the second opening 400.
In addition, the shortest distance between the second side a401 and the second side b 402 is d2′，d2′＞0。
In the etching process, the light emitting semiconductor layer 20 is gradually etched in a direction perpendicular to the substrate 10, and etching is started toward both sides in a horizontal direction parallel to the substrate 10 to etch the first and second trenches 60 and 70. As the etching progresses, the first barrier layer 30 and the second barrier layer 40 gradually become a suspended state. In order to ensure that the first barrier layer 30 and the second barrier layer 40 do not collapse during the etching process, preferably, the thicknesses of the first barrier layer 30 and the second barrier layer 40 are both 1 μm to 12 μm.
Specifically, the first barrier layer 30 is formed by exposing, developing and baking a first photoresist. The first photoresist is required to be capable of forming a glue layer with the thickness and adjustable in angle at different temperatures. Including PR1-4000A from Futurrex (USA), ma-P1200 from Micro Resist (Germany), SPR220 from Suzhou research Micro-nano technology, etc.
The material of the second barrier layer 40 includes at least one of a metal, a metal oxide, a silicon compound, and a second photoresist.
Wherein the metal comprises Cr, Au, Ti, Pt, etc., and the metal oxide comprises Al2O3、TiO2、Ti3O5Etc., the silicon compound comprises SiO2SiN, etc., the second photoresist comprises PR1-4000A, ma-P1200, SPR220, etc.
When the material of the second barrier layer 40 is a second photoresist, it is preferable that the second photoresist is a different kind of photoresist from the first photoresist. So that the second barrier layer 40 and the first barrier layer 30 are not affected by each other when they are prepared.
Specifically, the higher the baking temperature of the first photoresist and the second photoresist is, the smaller the angle formed is. Therefore, when the material of the second barrier layer 40 is the second photoresist, the first barrier layer 30 is first fabricated and formed on the light emitting semiconductor layer 20, and then the second barrier layer 40 is fabricated and formed. At this time, the baking temperature for forming the second barrier layer 40 is less than or equal to the baking temperature for forming the first barrier layer 30, so that the first barrier layer 30 is not damaged when the second barrier layer 40 is formed, the angle of the first barrier layer 30 is not reduced, and the angle of the second barrier layer 40 can be ensured.
Preferably, the baking temperature for forming the first barrier layer 30 is 80-150 ℃ and the baking time is not less than 120 s. The baking temperature for forming the second barrier layer 40 is 0 to 150 ℃, and is less than the baking temperature for forming the first barrier layer 30.
In consideration of the long manufacturing process time (generally >1 hour) and the high temperature (generally >200 ℃) of the metal layer, the metal oxide layer and the silicon compound layer, when the material of the second barrier layer 40 is metal, metal oxide or silicon compound, in order to avoid deterioration failure of the first barrier layer 30 due to a high temperature environment for a long time, the second barrier layer 40 is first formed on the light emitting semiconductor layer 20, and then the first barrier layer 30 is formed.
Further, the thickness of the first barrier layer 30 is 4 μm to 12 μm. When the material of the second barrier layer 40 is the second photoresist, the thickness of the second barrier layer 40 is 4 μm to 12 μm, and when the material of the second barrier layer 40 is the metal or the oxide, the thickness of the second barrier layer 40 is 1 μm to 10 μm.
In step S3, the light emitting semiconductor layer 20 is etched by using a conventional etching method such as dry etching, and after the etching is completed, the first barrier layer 30 and the second barrier layer 40 are removed to form an isolation trench.
Referring to fig. 3 and 4, the isolation grooves isolate the light emitting semiconductor layer 20 into a plurality of light emitting semiconductor units 50 spaced apart from each other.
Specifically, the isolation groove includes a first groove 60 and a second groove 70, and an inclination angle between the sidewall of the first groove 60 and the substrate 10 is smaller than an inclination angle between the sidewall of the second groove 70 and the substrate 10.
Wherein the first tank 60 comprises a first side wall a 601 and a first side wall b 602 which are oppositely arranged, and the inclination angle between the first side wall a 601 and the substrate 10 is set to α1The inclination angle between the first sidewall b 602 and the substrate 10 is set to α2，α1And α2All are 20-50 degrees.
Further, the first side wall a 601 of the first tank 60 has substantially the same structure as the first side a301 of the first barrier layer 30, and the first side wall b 602 has substantially the same structure as the first side b 302, α1And α2And preferably from 30 to 40.
Further, α1＝α2The first side wall a 601 and the first side wall b 602 are made to be axisymmetrical along the central axis of the first groove body 60 along the extending direction of the isolation groove.
In addition, the shortest distance between the first side wall a 601 and the first side wall b 602 is d1，d1> 0 and d1≥d1′。
The second tank 70 includes a second sidewall a 701 and a second sidewall b 702 disposed opposite to each other, and an inclination angle between the second sidewall a 701 and the substrate 10 is set to β1The inclination angle between the second sidewall b 702 and the substrate 10 is set to β2，β1And β2All are 60 degrees to 90 degrees.
The second side a 701 of the second channel 70 has substantially the same structure as the second side a401 of the second barrier layer 40, and the second side b 702 has substantially the same structure as the second side b 402, β1And β2And are each preferably from 70 to 80.
Further, β1＝β2The second side wall a 701 and the second side wall b 702 are axially symmetric along the central axis of the second groove body 70 along the extending direction of the isolation groove.
Preferably, the central axis of the first groove body 60 along the extending direction of the isolation groove and the central axis of the second groove body 70 along the extending direction of the isolation groove are collinear, so that the occupied area of the isolation groove is smaller.
The shortest distance between the second side wall a 701 and the second side wall b 702 is d2，d2> 0, and d2≥d2′。
Referring to fig. 5, before forming the first barrier layer 30 and the second barrier layer 40 on the light emitting semiconductor layer 20, the light emitting semiconductor layer 20 may be etched to expose a portion of the N-type semiconductor layer 201, and then the first barrier layer 30 and the second barrier layer 40 may be formed on the light emitting semiconductor layer 20.
Referring to fig. 6, the first side a301 and the first side b 302 of the first barrier layer 30, which are oppositely disposed, both extend to expose a portion of the N-type semiconductor layer 201, and the second side a401 and the second side b 402 of the second barrier layer 40, which are oppositely disposed, both extend to expose a portion of the N-type semiconductor layer 201. However, the distance d between the first side edge a301 and the first side edge b 3021' still greater than 0, the distance d between said second side a401 and said second side b 4022' is also still greater than 0, and thus, a portion of the N-type semiconductor layer 201 can still be exposed. Further, the etching speed in step S3 can be increased.
Referring to fig. 7 and 8, the present invention further provides a method for manufacturing an LED high voltage chip, including the following steps:
(1) etching an isolation groove on the LED chip main body by adopting the manufacturing method of the LED high-voltage chip isolation groove, wherein the isolation groove isolates the light-emitting semiconductor layer into a plurality of light-emitting semiconductor units 50;
(2) etching any side wall of the first groove body 60 to form a notch 204 extending from the P-type semiconductor layer 203 to the N-type semiconductor layer 201;
(3) forming an insulating layer 100 on the first groove body 60, and exposing a gap 204 part extending from the P-type semiconductor layer 203 to the N-type semiconductor layer 201;
(4) forming a transparent electrode 102 on the surface of the P-type semiconductor layer 203 of the light-emitting semiconductor unit 50;
(5) a conductive connection layer 101 is formed on the insulating layer 100 so that the transparent electrode 102 is connected to the N-type semiconductor layer 201 exposed at the notch 204 of the adjacent light emitting semiconductor unit 50 to connect the adjacent light emitting semiconductor units 50 in series.
After the step (5), forming an insulating protection layer 103 to obtain an LED high-voltage chip; the insulating protection layer 103 covers the light-emitting semiconductor unit 50 and the surface of the isolation trench, and covers the light-emitting semiconductor unit 50, the insulating layer 100, the conductive connection layer 101 and the transparent electrode 102.
Specifically, the material of the insulating layer comprises SiO2、Si3N4、TiO2、Ti3O5And the like.
The material of the transparent electrode 102 includes indium tin oxide and the like.
The material of the insulating protective layer comprises Al2O3、SiO2And the like.
Referring to fig. 7 and 8, in order to provide an LED high-voltage chip provided by the present invention, the LED high-voltage chip includes a substrate 10, a plurality of light-emitting semiconductor units 50 disposed on the substrate 10, and a conductive connection layer 101, wherein the plurality of light-emitting semiconductor units 50 are isolated by an isolation trench, and the isolation trench includes a first trench body 60 and a second trench body 70.
Wherein the first groove body 60 comprises a first side wall a 601 and a first side wall b 602 which are oppositely arranged, and the first side wall a601 to the substrate 10 is set to α1The inclination angle between the first sidewall b 602 and the substrate 10 is set to α2，α1And α2The angle of each of the second grooves 70 is 20 to 50 degrees, the second grooves 70 include a second side wall a 701 and a second side wall b 702 which are oppositely arranged, and the inclination angle between the second side wall a 701 and the substrate 10 is set to β1The inclination angle between the second sidewall b 702 and the substrate 10 is set to β2，β1And β2Are all 60 degrees to 90 degrees, and the conductive connecting layer 101 extends along the side wall of the first groove body 60 and is connected with the adjacent light-emitting semiconductor units 50 in series.
Specifically, the light emitting semiconductor unit 50 includes an N-type semiconductor layer 201, a light emitting layer 202, and a P-type semiconductor layer 203 sequentially stacked on the substrate 10, a notch 204 extending from the P-type semiconductor layer 203 to the N-type semiconductor layer 201 is disposed on any sidewall of the first tank 60 to expose a portion of the N-type semiconductor layer 201, a transparent electrode 102 is disposed on the surface of the P-type semiconductor layer 203, and the exposed portion of the N-type semiconductor layer 201 at the notch 204 is connected to the adjacent transparent electrode 102 on the light emitting semiconductor unit 50 through the conductive connection layer 101, so that a current flows to the N-type semiconductor layer 201 of the adjacent light emitting semiconductor unit 50 through the transparent electrode 102. Thus, the plurality of semiconductor units 50 are connected in series to form the LED high voltage chip.
Specifically, an insulating layer 100 is arranged between the conductive connecting layer 101 and the first tank 60, and is used for isolating the conductive connecting layer 101 from contacting with the first tank 60. Thus, the conductive connection layer 101 prevents the N-type semiconductor layer and the P-type semiconductor layer of the same light emitting semiconductor unit 50 from being electrically connected to each other and leakage current from occurring.
Specifically, the LED high-voltage chip further includes an insulating protection layer 103, and the insulating protection layer 103 covers the light-emitting semiconductor unit 50 and the surface of the isolation groove, and is used for isolating the LED high-voltage chip from contacting with air.
It can be understood that the insulating protection layer 103 covers the insulating layer 100, the conductive connection layer 101 and the transparent electrode 102 when covering the light emitting semiconductor unit 50 and the surface of the isolation trench.
Therefore, the first barrier layer and the second barrier layer are simultaneously formed on the light-emitting semiconductor layer, so that the isolation groove can be manufactured by one-time etching process, and the cost can be saved by about 30%.
Meanwhile, the side wall of the first groove body and the side wall of the second groove body of the manufactured isolation groove are inclined at different angles with the substrate, and the conductive connecting layer is deposited on the first groove body with a smaller inclination angle to realize series connection of the luminous semiconductor units, so that the luminous area of the LED high-voltage chip is increased by 10% -30%, the brightness is improved by about 5%, the covering performance of the conductive connecting layer is ensured, and the reliability is improved.
Hereinafter, the LED high voltage chip, the method for manufacturing the LED high voltage chip, and the method for manufacturing the isolation trench will be further described with reference to the following embodiments.
Example 1:
the LED chip main body comprises a substrate and a light emitting semiconductor layer consisting of an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer which are sequentially arranged on the substrate.
And coating glue in an area where the first groove body needs to be etched by using ma-P1200 as a first photoresist, wherein the glue thickness is 12 mu m, carrying out plate alignment, exposure and development, then baking the first photoresist at the temperature of 140 ℃ for 10 minutes, and curing to obtain a first barrier layer. The first barrier layer is provided with a first opening which penetrates through the first barrier layer, the first opening comprises a first side edge a and a first side edge b which are symmetrical along the central axis of the first opening, and the distance d between the first side edge a and the first side edge b1' 3 μm, first side a and the angle of inclination between first side b and the substrate α1' and α2' are all 20 deg..
And in the remaining area needing to be etched with the second groove body, coating photoresist with PR1-4000 and the thickness of 10 mu m by using second photoresist, carrying out plate alignment, exposure and development, baking the second photoresist at the temperature of 110 ℃ for 10 minutes, and curing to obtain a second barrier layer. The second barrier layer is provided with a second opening which penetrates through the second barrier layer, the second opening comprises a second side edge a and a second side edge b which are symmetrical along the central axis of the second opening, and the second side edge a and the second side edge bDistance d of side b2' 3 μm, second side a and second side b inclined at β to the substrate1' and β2' are all 60 deg.. Wherein the central axis of the first opening and the central axis of the second opening are collinear.
And etching the light-emitting semiconductor layer by adopting a dry etching method to form an isolation groove comprising a first groove body and a second groove body, and removing the first barrier layer and the second barrier layer after etching.
Then etching the first side wall a of the first groove body to form a gap extending from the P-type semiconductor layer to the N-type semiconductor layer, and then sequentially depositing SiO2An insulating layer, an indium tin oxide transparent electrode, a conductive connection layer for the series connection of light-emitting semiconductor units deposited on the insulating layer, and Al deposited2O3And insulating the protective layer to obtain the LED high-voltage chip.
The LED high-voltage chip comprises a substrate, a plurality of luminous semiconductor units and a conductive connecting layer, wherein the luminous semiconductor units are arranged on the substrate, the luminous semiconductor units are isolated through isolation grooves, and the isolation grooves comprise first groove bodies and second groove bodies. Wherein the first groove body comprises a first side wall a and a first side wall b which are axisymmetric along the central axis thereof, and the shortest distance d between the first side wall a and the first side wall b13 μm, the first side wall a and the first side wall b and the substrate are inclined at an angle α1And α2Are all 20 degrees.
The second trough body comprises a second side wall a and a second side wall b which are symmetrical along the central axis of the second trough body, and the shortest distance d between the second side wall a and the second side wall b23 μm, second side wall a and second side wall b and the substrate at an inclination angle β1And β2Are all 60 degrees. Wherein, the axis of the first cell body is collinear with the axis of the second cell body.
Example 2:
the LED chip main body comprises a substrate and a light emitting semiconductor layer consisting of an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer which are sequentially arranged on the substrate.
The light emitting semiconductor layer is etched using a conventional MESA to expose a portion of the N-type semiconductor layer.
In the area where the first groove body needs to be etchedAnd coating glue by taking the ma-P1200 as a first photoresist, wherein the glue thickness is 10 mu m, carrying out plate alignment, exposure and development, then baking the first photoresist for 10 minutes at the temperature of 130 ℃, and curing to obtain a first barrier layer. The first barrier layer is provided with a first opening which penetrates through the first barrier layer, the first opening comprises a first side edge a and a first side edge b which are symmetrical along the central axis of the first opening, and the distance d between the first side edge a and the first side edge b1' 3 μm, first side a and the angle of inclination between first side b and the substrate α1' and α2' are all 30 deg..
And in the remaining area where the second groove body needs to be etched, coating photoresist with PR1-4000A as a second photoresist, wherein the thickness of the photoresist is 8 mu m, performing plate alignment, exposure and development, baking the second photoresist at the temperature of 80 ℃ for minutes, and curing to obtain a second barrier layer. The second barrier layer is provided with a second opening which penetrates through the second barrier layer, the second opening comprises a second side edge a and a second side edge b which are symmetrical along the central axis of the second opening, and the distance d between the second side edge a and the second side edge b2' 3 μm, second side a and second side b inclined at β to the substrate1' and β2' are all 70 deg.. Wherein the central axis of the first opening and the central axis of the second opening are collinear.
And etching the light-emitting semiconductor layer by adopting a dry etching method to form an isolation groove comprising a first groove body and a second groove body, and removing the first barrier layer and the second barrier layer after etching.
Then etching the first side wall a of the first groove body to form a notch extending from the P-type semiconductor layer to the N-type semiconductor layer, and then sequentially depositing Si3N4An insulating layer, an indium tin oxide transparent electrode, a conductive connection layer for the deposition of series-connected light-emitting semiconductor units on the insulating layer, and deposition of SiO2And insulating the protective layer to obtain the LED high-voltage chip.
The LED high-voltage chip comprises a substrate, a plurality of luminous semiconductor units and a conductive connecting layer, wherein the luminous semiconductor units are arranged on the substrate, the luminous semiconductor units are isolated through isolation grooves, and the isolation grooves comprise first groove bodies and second groove bodies. Wherein the first groove body comprises a first side wall a and a first side wall b which are axisymmetric along the central axis thereof, and the most extreme of the first side wall a and the first side wall bShort distance d13 μm, the first side wall a and the first side wall b and the substrate are inclined at an angle α1And α2Are all 30 degrees.
The second trough body comprises a second side wall a and a second side wall b which are symmetrical along the central axis of the second trough body, and the shortest distance d between the second side wall a and the second side wall b23 μm, second side wall a and second side wall b and the substrate at an inclination angle β1And β2Are all 70 degrees. Wherein, the axis of the first cell body is collinear with the axis of the second cell body.
Example 3:
the LED chip main body comprises a substrate and a light emitting semiconductor layer consisting of an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer which are sequentially arranged on the substrate.
The light emitting semiconductor layer is etched using a conventional MESA to expose a portion of the N-type semiconductor layer.
And depositing metal Ti as a second barrier layer in the area where the second groove body needs to be etched, wherein the thickness of the second barrier layer is 4 mu m. The second barrier layer is provided with a penetrating second opening, the second opening comprises a second side edge a and a second side edge b which are oppositely arranged, and the distance d between the second side edge a and the second side edge b2' 3 μm, the angle of inclination between the second side a and the substrate β1' 90 deg., the angle of inclination between the second side edge b and the substrate β2' is 90 deg..
And coating glue in an area where the first groove body needs to be etched by using ma-P1200 as a first photoresist, wherein the glue thickness is 8 mu m, carrying out plate alignment, exposure and development, then baking the first photoresist for 20 minutes at the temperature of 110 ℃, and curing to obtain a first barrier layer. The first barrier layer is provided with a first opening which penetrates through the first barrier layer, the first opening comprises a first side edge a and a first side edge b which are oppositely arranged, and the distance d between the first side edge a and the first side edge b1' 4 μm, the angle of inclination between the first side a and the substrate α1' 40 deg., the angle of inclination between the first side b and the substrate α2' is 40 deg..
And etching the light-emitting semiconductor layer by adopting a dry etching method to form an isolation groove comprising a first groove body and a second groove body, and removing the first barrier layer and the second barrier layer after etching.
Then etching the first side wall a of the first groove body to form a gap extending from the P-type semiconductor layer to the N-type semiconductor layer, and then sequentially depositing SiO2An insulating layer, an indium tin oxide transparent electrode, a conductive connection layer for the deposition of series-connected light-emitting semiconductor units on the insulating layer, and deposition of SiO2And insulating the protective layer to obtain the LED high-voltage chip.
The LED high-voltage chip comprises a substrate, a plurality of luminous semiconductor units and a conductive connecting layer, wherein the luminous semiconductor units are arranged on the substrate, the luminous semiconductor units are isolated through isolation grooves, and the isolation grooves comprise first groove bodies and second groove bodies. Wherein, the first trough body comprises a first side wall a and a first side wall b which are oppositely arranged, and the shortest distance d between the first side wall a and the first side wall b1At 3 μm, the first sidewall a has an inclination angle α with respect to the substrate1Is 40 deg., and the angle of inclination α between the first side wall b and the substrate2Is 40 deg..
The second groove body comprises a second side wall a and a second side wall b which are oppositely arranged, and the shortest distance d between the second side wall a and the second side wall b23 μm, the angle of inclination between the second side wall a and the substrate β1Is 90 deg., and the angle of inclination β between the second side wall b and the substrate2Is 90 deg..
Example 4:
the LED chip main body comprises a substrate and a light emitting semiconductor layer consisting of an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer which are sequentially arranged on the substrate.
The light emitting semiconductor layer is etched using a conventional MESA to expose a portion of the N-type semiconductor layer.
Depositing SiO in the area where the second groove body needs to be etched2As a second barrier layer, the thickness was 4 μm. The second barrier layer is provided with a penetrating second opening, the second opening comprises a second side edge a and a second side edge b which are oppositely arranged, and the distance d between the second side edge a and the second side edge b2' 3 μm, the angle of inclination between the second side a and the substrate β1' is 80 deg., and the second side edge b is inclined at an angle β to the substrate2' is 80 deg..
In the area where the first groove body needs to be etched, so as toAnd (3) coating glue on the ma-P1200 photoresist with the glue thickness of 6 mu m, performing plate alignment, exposure and development, baking the first photoresist at the temperature of 80 ℃ for 10 minutes, and curing to obtain a first barrier layer. The first barrier layer is provided with a first opening which penetrates through the first barrier layer, the first opening comprises a first side edge a and a first side edge b which are oppositely arranged, and the distance d between the first side edge a and the first side edge b1' 3 μm, the angle of inclination between the first side a and the substrate α1' 50 deg., the angle of inclination between the first side b and the substrate α2' is 50 deg..
And etching the light-emitting semiconductor layer by adopting a dry etching method to form an isolation groove comprising a first groove body and a second groove body, and removing the first barrier layer and the second barrier layer after etching.
Then etching the first side wall a of the first groove body to form a notch extending from the P-type semiconductor layer to the N-type semiconductor layer, and then sequentially depositing Si3N4An insulating layer, an indium tin oxide transparent electrode, a conductive connection layer for the deposition of series-connected light-emitting semiconductor units on the insulating layer, and deposition of SiO2And insulating the protective layer to obtain the LED high-voltage chip.
The LED high-voltage chip comprises a substrate, a plurality of luminous semiconductor units and a conductive connecting layer, wherein the luminous semiconductor units are arranged on the substrate, the luminous semiconductor units are isolated through isolation grooves, and the isolation grooves comprise first groove bodies and second groove bodies. Wherein, the first trough body comprises a first side wall a and a first side wall b which are oppositely arranged, and the shortest distance d between the first side wall a and the first side wall b1At 3 μm, the first sidewall a has an inclination angle α with respect to the substrate1Is 50 deg., the angle of inclination α between the first sidewall b and the substrate2Is 50 deg..
The second groove body comprises a second side wall a and a second side wall b which are oppositely arranged, and the shortest distance d between the second side wall a and the second side wall b23 μm, the angle of inclination between the second side wall a and the substrate β1Is 80 deg., and the angle of inclination β between the second side wall b and the substrate2Is 80 degrees.
Example 5:
the LED chip main body comprises a substrate and a light emitting semiconductor layer consisting of an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer which are sequentially arranged on the substrate.
The light emitting semiconductor layer is etched using a conventional MESA to expose a portion of the N-type semiconductor layer.
Depositing Al in the area where the second groove body needs to be etched2O3As a second barrier layer, the thickness was 1 μm. The second barrier layer is provided with a penetrating second opening, the second opening comprises a second side edge a and a second side edge b which are oppositely arranged, and the distance d between the second side edge a and the second side edge b2' 3 μm, the angle of inclination between the second side a and the substrate β1' 90 deg., the angle of inclination between the second side edge b and the substrate β2' is 90 deg..
And coating glue in an area where the first groove body needs to be etched by using ma-P1200 as a first photoresist, wherein the glue thickness is 8 mu m, carrying out plate alignment, exposure and development, then baking the first photoresist for 20 minutes at the temperature of 110 ℃, and curing to obtain a first barrier layer. The first barrier layer is provided with a first opening which penetrates through the first barrier layer, the first opening comprises a first side edge a and a first side edge b which are oppositely arranged, and the distance d between the first side edge a and the first side edge b1' 4 μm, the angle of inclination between the first side a and the substrate α1' 40 deg., the angle of inclination between the first side b and the substrate α2' is 38 deg..
And etching the light-emitting semiconductor layer by adopting a dry etching method to form an isolation groove comprising a first groove body and a second groove body, and removing the first barrier layer and the second barrier layer after etching.
Then etching the first side wall a of the first groove body to form a gap extending from the P-type semiconductor layer to the N-type semiconductor layer, and then sequentially depositing SiO2An insulating layer, an indium tin oxide transparent electrode, a conductive connection layer for the deposition of series-connected light-emitting semiconductor units on the insulating layer, and deposition of SiO2And insulating the protective layer to obtain the LED high-voltage chip.
The LED high-voltage chip comprises a substrate, a plurality of luminous semiconductor units and a conductive connecting layer, wherein the luminous semiconductor units are arranged on the substrate, the luminous semiconductor units are isolated through isolation grooves, and the isolation grooves comprise first groove bodies and second groove bodies. Wherein, the first groove body comprises a first side which is arranged oppositelyWall a and first side wall b, the shortest distance d of first side wall a and first side wall b1At 3 μm, the first sidewall a has an inclination angle α with respect to the substrate1Is 40 deg., and the angle of inclination α between the first side wall b and the substrate2Is 38 deg..
The second groove body comprises a second side wall a and a second side wall b which are oppositely arranged, and the shortest distance d between the second side wall a and the second side wall b23 μm, the angle of inclination between the second side wall a and the substrate β1Is 90 deg., and the angle of inclination β between the second side wall b and the substrate2Is 90 deg..
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A manufacturing method of an LED high-voltage chip isolation groove is characterized by comprising the following steps:
providing an LED chip main body, wherein the LED chip main body comprises a substrate and a light-emitting semiconductor layer arranged on the substrate;
forming a first barrier layer and a second barrier layer on the light-emitting semiconductor layer, wherein the first barrier layer is provided with a first penetrating opening, the second barrier layer is provided with a second penetrating opening, an inclination angle between the side edge of the first opening and the substrate is smaller than an inclination angle between the side edge of the second opening and the substrate, and the first opening and the second opening are arranged in parallel;
and etching the light-emitting semiconductor layer to form an isolation groove, wherein the isolation groove comprises a first groove body and a second groove body, and the inclination angle between the side wall of the first groove body and the substrate is smaller than the inclination angle between the side wall of the second groove body and the substrate.
2. The method for manufacturing the LED high-voltage chip isolation groove according to claim 1, wherein the side of the first opening comprises a first side a and a second side b which are oppositely arranged, and the inclination angle between the first side a and the substrate is set to α1' the inclination angle between the second side edge b and the substrate is set to α2′，α1' and α2' are all 20 to 50 degrees; and/or
The side of the second opening comprises a second side a and a second side b which are oppositely arranged, and the inclination angle between the second side a and the substrate is set to β1' the inclination angle between the second side edge b and the substrate is set to β2′，β1' and β2' are all 60-90 degrees.
3. The method for manufacturing the LED high-voltage chip isolation groove according to claim 2, wherein the first blocking layer is formed by exposing, developing and baking a first photoresist.
4. The method of claim 3, wherein the material of the second barrier layer comprises at least one of a metal, a metal oxide, a silicon compound, and a second photoresist.
5. The method for manufacturing the LED high-voltage chip isolation groove according to claim 4, wherein when the material of the second barrier layer comprises at least one of metal, metal oxide and silicon compound, the second barrier layer is firstly manufactured and formed on the light-emitting semiconductor layer, and then the first barrier layer is manufactured and formed;
when the material of the second barrier layer is the second photoresist, the first barrier layer is firstly manufactured and formed on the light-emitting semiconductor layer, and then the second barrier layer is manufactured and formed.
6. The method of claim 5, wherein when the second barrier layer is made of a second photoresist, the baking temperature for forming the second barrier layer is less than or equal to the baking temperature for forming the first barrier layer.
7. The method for manufacturing the LED high-voltage chip isolation groove according to claim 1, wherein the thickness of the first barrier layer and the thickness of the second barrier layer are both 1-12 μm.
8. The manufacturing method of the LED high-voltage chip isolation groove as claimed in claims 1 to 7, wherein the light emitting semiconductor layer comprises an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer which are sequentially arranged on the substrate, and the light emitting semiconductor layer is etched to expose a part of the N-type semiconductor layer before the first barrier layer and the second barrier layer are formed on the light emitting semiconductor layer.
9. The preparation method of the LED high-voltage chip is characterized by comprising the following steps:
etching an isolation groove on an LED chip main body by adopting the manufacturing method of the LED high-voltage chip isolation groove of any one of claims 1 to 9, wherein the isolation groove isolates a light-emitting semiconductor layer into a plurality of light-emitting semiconductor units;
etching any side wall of the first groove body to form a notch extending from the P-type semiconductor layer to the N-type semiconductor layer;
forming an insulating layer on the first groove body, and exposing a gap part extending from the P-type semiconductor layer to the N-type semiconductor layer;
forming a transparent electrode on the surface of the P-type semiconductor layer of the light-emitting semiconductor unit;
and forming a conductive connecting layer on the insulating layer so that the transparent electrode is connected with the N-type semiconductor layer exposed at the gap of the adjacent light-emitting semiconductor unit to connect the adjacent light-emitting semiconductor units in series.
10. An LED high-voltage chip is characterized by comprising a substrate, a plurality of luminous semiconductor units arranged on the substrate and a conductive connecting layer, wherein the luminous semiconductor units are isolated by an isolation groove, the isolation groove comprises a first groove body and a second groove body, wherein,
the first groove body comprises a first side wall a and a first side wall b which are oppositely arranged, and the inclination angle between the first side wall a and the substrate is set to α1The inclination angle between the first sidewall b and the substrate is set to α2，α1And α2The angle of inclination between the second side wall a and the substrate is β1The inclination angle between the second sidewall b and the substrate is set to β2，β1And β2The conductive connecting layer extends along the side wall of the first groove body and is connected with the adjacent light-emitting semiconductor units in series.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111697020A (en) * | 2020-06-23 | 2020-09-22 | 江西乾照光电有限公司 | Preparation method of high-voltage LED chip |
| CN112349818A (en) * | 2020-10-27 | 2021-02-09 | 江西乾照光电有限公司 | Deep etching method for high-voltage LED chip |
| US20210391501A1 (en) * | 2020-06-15 | 2021-12-16 | Korea University Research And Business Foundation | Micro light-emitting diode including optimized passivation layer and method of fabricating the same |
| WO2023279259A1 (en) * | 2021-07-06 | 2023-01-12 | 泉州三安半导体科技有限公司 | High-voltage light-emitting diode |
| WO2023184313A1 (en) * | 2022-03-31 | 2023-10-05 | 京东方科技集团股份有限公司 | Light-emitting diode chip, display substrate and display apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20210391501A1 (en) * | 2020-06-15 | 2021-12-16 | Korea University Research And Business Foundation | Micro light-emitting diode including optimized passivation layer and method of fabricating the same |
| CN111697020A (en) * | 2020-06-23 | 2020-09-22 | 江西乾照光电有限公司 | Preparation method of high-voltage LED chip |
| CN112349818A (en) * | 2020-10-27 | 2021-02-09 | 江西乾照光电有限公司 | Deep etching method for high-voltage LED chip |
| WO2023279259A1 (en) * | 2021-07-06 | 2023-01-12 | 泉州三安半导体科技有限公司 | High-voltage light-emitting diode |
| WO2023184313A1 (en) * | 2022-03-31 | 2023-10-05 | 京东方科技集团股份有限公司 | Light-emitting diode chip, display substrate and display apparatus |
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