CN104576867A - Method for manufacturing group III semiconductor luminescent device - Google Patents

Method for manufacturing group III semiconductor luminescent device Download PDF

Info

Publication number
CN104576867A
CN104576867A CN201510027675.XA CN201510027675A CN104576867A CN 104576867 A CN104576867 A CN 104576867A CN 201510027675 A CN201510027675 A CN 201510027675A CN 104576867 A CN104576867 A CN 104576867A
Authority
CN
China
Prior art keywords
type
layer
electrode
gold
insulating barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510027675.XA
Other languages
Chinese (zh)
Other versions
CN104576867B (en
Inventor
许顺成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xiangneng Hualei Optoelectrical Co Ltd
Original Assignee
Xiangneng Hualei Optoelectrical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xiangneng Hualei Optoelectrical Co Ltd filed Critical Xiangneng Hualei Optoelectrical Co Ltd
Priority to CN201510027675.XA priority Critical patent/CN104576867B/en
Publication of CN104576867A publication Critical patent/CN104576867A/en
Application granted granted Critical
Publication of CN104576867B publication Critical patent/CN104576867B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Abstract

The invention discloses a method for manufacturing a group III semiconductor luminescent device. The method comprises the steps that a substrate, a buffer layer, an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer grow in sequence from bottom to top to form an epitaxy structure; yellow light etching processing is utilized to define patterns of a boss, the p-type nitride semiconductor layer and the active layer are etched, the n-type nitride semiconductor layer is exposed, and the boss is obtained; a transparent conducting layer is deposited, the yellow light etching processing is utilized to define patterns of the transparent conducting layer, and the transparent conducting layer is etched; an insulating layer is deposited; yellow light etching processing is used for defining patterns to be involved into current distribution, and the insulating layer and/or the transparent conducting layer are/is etched; patterns of a P-type electrode and an N-type electrode are defined by yellow light stripping processing, the P-type electrode and the N-type electrode are deposited, the stripping processing is utilized to remove light resistance, and a wafer is produced out; finally the wafer is thinned, scribed, splintered, tested and sorted. By means of the method for manufacturing the group III semiconductor luminescent device, production cost is reduced, the active layer below an N-type bonding pad is restored, and the light-emitting area is enlarged.

Description

A kind of manufacture method of III light emitting semiconductor device
Technical field
The application relates to technical field of semiconductor illumination, specifically, relates to a kind of manufacture method of III light emitting semiconductor device.
Background technology
The luminous efficiency of gallium nitride based light emitting diode obtained raising to a great extent in recent years, but external quantum efficiency, current distribution uniformity have become the major technology bottleneck that restriction light-emitting diode performance improves further.In prior art, in Sapphire Substrate, gallium nitride based light emitting diode can all be positioned at substrate together first because of its P/N type electrode, its P-type electrode, N-type electrode generally comprise line bond pad and line electrode, line bond pad due to N-type electrode will be used for welding gold ball (gold goal diameter is generally 75um), therefore the design of N-type electrode line dimensions of bond pads is comparatively large, so just causes active layer to etch area excessive.
Have active layer etching area problems of too to solve gallium nitride based light emitting diode in Sapphire Substrate, current solution is as follows:
1, by laser lift-off technique, substrate and nitride semiconductor layer peeled off mutually and manufacture vertical light-emitting device, although light emitting diode with vertical structure technology solves gallium nitride based light emitting diode Problems existing in traditional Sapphire Substrate, as heat radiation, active layer etch the problems such as area is excessive, current distribution uniformity, but substrate desquamation complex process, with high costs and yield is too low.
2, by forming multiple sapphire hole in Sapphire Substrate, Sapphire Substrate hole wall and a kind of N type semiconductor metal of bottom deposit, and each hole is filled another kind of metal to form a N-type electrode contact and then to form light emitting diode with vertical structure.But this scheme exists sapphire bores multiple holes complex process, the problems such as with high costs and reliability of technology is lower.
Summary of the invention
In order to solve produced problem in the above prior art, the object of this invention is to provide a kind of manufacture method of III light emitting semiconductor device, to solve the etched many problems of active layer, increase active layer thus improve photoelectric characteristic, and by the new construction that provides by CURRENT DISTRIBUTION evenly and increase anlistatig ability.
The invention provides a kind of manufacture method of III light emitting semiconductor device, comprise the following steps:
Substrate, resilient coating, n-type nitride semiconductor layer, active layer and p-type nitride semiconductor layer grow successively from bottom to top and form epitaxial structure, and the upper surface of described epitaxial structure is the upper surface of described p-type nitride semiconductor layer;
Utilize gold-tinted etch process to define cam pattern, then etch described p-type nitride semiconductor layer and active layer, and expose described n-type nitride semiconductor layer, finally remove photoresistance, obtain boss;
Deposit transparent conductive layer on described p-type nitride-based semiconductor or deposit transparent conductive layer on described p-type nitride-based semiconductor and between n-type nitride semiconductor layer, gold-tinted etch process is utilized to define described pattern for transparent conductive layer, etch described transparency conducting layer again, finally remove photoresistance, obtain the boss that upper surface has transparency conducting layer;
Depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier;
Gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss,
Finally described disk is carried out thinning, scribing, sliver, test, sorting.
Compared with prior art, the manufacture method of the III light emitting semiconductor device described in the application, has the following advantages:
(1) manufacture method provided by the invention, production cycle is shortened, greatly reduce production cost, and the active layer reduced below N-type pad, to solve the etched many problems of active layer, add active layer thus improve photoelectric characteristic, reducing the active layer below N-type pad, the active layer that can also reduce below part N-type line electrode, which increases light-emitting area.Because light-emitting area becomes large, so operating voltage declines, brightness is risen.
(2) the present invention also provides the structure of P type pad or N-type pad can be positioned at any position above insulating barrier, so do not participate in CURRENT DISTRIBUTION completely, a wired electrodes participates in CURRENT DISTRIBUTION, therefore more easily designs mask pattern.The present invention reduces the active layer below N-type pad, and because light-emitting area becomes large, the contact resistance of transparency conducting layer and p-type nitride semiconductor layer declines, so operating voltage declines;
(3) in method of the present invention, transparency conducting layer is made together with mesa pattern, not only simplify one processing procedure, also solve the problem that transparency conducting layer is aimed at mesa pattern.In addition P type pad, P molded line electrode and N-type line electrode 14 pattern that will participate in CURRENT DISTRIBUTION can be defined in the present invention, so can lean on the region of etching isolation layer to define the pattern that will participate in CURRENT DISTRIBUTION, so mask set is easier.
(4) the present invention also provides a kind of new construction to be line bond pad (metal)/insulating barrier/transparency conducting layer, and this structure is capacitance structure, can increase the yield of antistatic effect;
(5) difference in height between P type pad of the prior art or N-type pad reaches 1100-1600nm, and the difference in height in the present invention between P type pad and N-type pad is less than or equal to 300nm, is of the present inventionly compared to existing technology more conducive to routing than tradition.
(6) the present invention reduces the active layer below N-type pad, and the percentage that the active layer below chip size less reduction N-type pad accounts for light-emitting area is more, so more small size operating voltage declines more, brightness is risen more.
(7) in prior art, P-type electrode or N-type electrode (comprising P type pad, N-type pad, P molded line electrode and N-type line electrode) are disposable platings, but the P type pad in the present invention, N-type pad and P molded line electrode, N-type line electrode can also can plate respectively in disposable plating, reach better ohmic contact.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide further understanding of the present application, and form a application's part, the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 is the vertical view of III light emitting semiconductor device in prior art;
Fig. 2 is the profile of Fig. 1 along A-B direction;
Fig. 3 is the vertical view of III light emitting semiconductor device provided by the invention;
Fig. 4 a-Fig. 4 c is the profile of the N-type pad in Fig. 3 along I-J direction;
Fig. 5 a-Fig. 5 d is the profile of the P type pad in Fig. 3 along M-N direction;
Fig. 6 a and Fig. 6 b is the profile of the N-type pad in Fig. 3 along C-D direction;
Fig. 7 a-Fig. 7 d is the profile of the P molded line electrode in Fig. 3 along E-F direction;
Fig. 8 a-Fig. 8 d is the profile of the N-type line electrode in Fig. 3 along G-H direction;
Fig. 9 is the vertical view of the active layer of N-type line electrode and below thereof;
Figure 10 is the profile of the N-type line electrode in Fig. 9 along K-L direction;
Figure 11 a and Figure 11 b is line bond pad-insulation layer-transparent conducting layer in the present invention and equivalent electric circuit thereof;
Figure 12 a-Figure 12 c is the product profile of each step in embodiment 3;
Figure 13 is III light emitting semiconductor device Making programme figure provided by the invention;
Figure 14 a-Figure 14 c is the product profile of each step in embodiment 4.
Embodiment
As employed some vocabulary to censure specific components in the middle of specification and claim.Those skilled in the art should understand, and hardware manufacturer may call same assembly with different noun.This specification and claims are not used as with the difference of title the mode distinguishing assembly, but are used as the criterion of differentiation with assembly difference functionally." comprising " as mentioned in the middle of specification and claim is in the whole text an open language, therefore should be construed to " comprise but be not limited to "." roughly " refer to that in receivable error range, those skilled in the art can solve the technical problem within the scope of certain error, reach described technique effect substantially.In addition, " couple " word and comprise directly any and indirectly electric property coupling means at this.Therefore, if describe a first device in literary composition to be coupled to one second device, then represent described first device and directly can be electrically coupled to described second device, or be indirectly electrically coupled to described second device by other devices or the means that couple.Specification subsequent descriptions is implement the better embodiment of the application, and right described description is for the purpose of the rule that the application is described, and is not used to the scope limiting the application.The protection range of the application is when being as the criterion depending on the claims person of defining.
Below in conjunction with accompanying drawing, the application is described in further detail, but not as the restriction to the application.
Embodiment 1:
III light emitting semiconductor device manufacture method of the present invention comprises the following steps:
S1301: substrate, resilient coating, n-type nitride semiconductor layer, active layer and p-type nitride semiconductor layer grow successively from bottom to top and form epitaxial structure, and the upper surface of described epitaxial structure is the upper surface of described p-type nitride semiconductor layer;
S1302: utilize gold-tinted etch process to define cam pattern, then etch described p-type nitride semiconductor layer and active layer, and expose described n-type nitride semiconductor layer, finally remove photoresistance, obtain boss;
S1303: deposit transparent conductive layer on described p-type nitride-based semiconductor or deposit transparent conductive layer on described p-type nitride-based semiconductor and between n-type nitride semiconductor layer, gold-tinted etch process is utilized to define described pattern for transparent conductive layer, etch described transparency conducting layer again, finally remove photoresistance, obtain the boss that upper surface has transparency conducting layer;
S1304: depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier;
S1305: gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss,
S1306: finally described disk is carried out thinning, scribing, sliver, test, sorting.
Wherein step S1304 comprises following five kinds of concrete production programs:
1) depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, utilizes gold-tinted etch process to define the pattern that will participate in CURRENT DISTRIBUTION, then etches described insulating barrier, finally remove photoresistance, obtain the boss with insulating barrier.
2) depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described insulating barrier and transparency conducting layer continuously again, finally remove photoresistance, obtain the boss with insulating barrier.
3) depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier again, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier.
4) depositing insulating layer is on the upper surface of transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define pattern, the again etching isolation layer that will participate in CURRENT DISTRIBUTION, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described insulating barrier and transparency conducting layer continuously again, finally remove photoresistance, obtain the boss with insulating barrier.
5) depositing insulating layer is on the upper surface of transparency conducting layer and the surface of described boss, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described insulating barrier and transparency conducting layer continuously again, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier again, finally remove photoresistance, obtain the boss with insulating barrier.
Wherein step S1305 comprises following four kinds of concrete production programs:
A) described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposits described P-type electrode and N-type electrode simultaneously, and processing procedure is peeled off in rear utilization, then removes photoresistance, makes disk.
B) gold-tinted peels off program defining P molded line electrode and N-type line electrode pattern, deposit described P molded line electrode and N-type line electrode simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining P type pad and N-type welding disk pattern, deposits described P type pad and N-type pad simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
C) gold-tinted peels off program defining P type pad and N-type welding disk pattern, deposit described P type pad and N-type pad simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining P molded line electrode and N-type line electrode pattern, deposits described P molded line electrode and N-type line electrode simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
D) gold-tinted peels off program defining P type pad and P molded line electrode pattern, deposit described P type pad and P molded line electrode simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining N-type pad and N-type line electrode pattern, deposits described N-type pad and N-type line electrode simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
E) gold-tinted peels off program defining N-type pad and N-type line electrode pattern, deposit described N-type pad and N-type line electrode simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining P type pad and P molded line electrode pattern, deposits described P type pad and P molded line electrode simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
III group nitride compound semiconductor light emitting element has been made according to said method in the present embodiment, as shown in Figure 3, for the vertical view of the III light emitting semiconductor device that the present embodiment provides, Fig. 4 a-Fig. 4 c is the profile of N-type pad along I-J direction toward N-type line electrode in Fig. 3; Fig. 5 a to Fig. 5 d is the profile of the P type pad in Fig. 3 along M-N direction; Fig. 6 a and Fig. 6 b is the profile of the N-type pad in Fig. 3 along C-D direction; Fig. 7 a-Fig. 7 d is the profile of the P molded line electrode in Fig. 3 along E-F direction; Fig. 8 a-8d is the profile of the N-type line electrode in Fig. 3 along G-H direction; Fig. 9 is the vertical view of the active layer of N-type line electrode and below thereof; Figure 10 is the profile that in Fig. 9, below N-type line electrode, active layer is reduced; Figure 11 a and Figure 11 b is line bond pad-insulation layer-transparent conducting layer in the present invention and equivalent circuit diagram thereof.
Active layer below described N-type line electrode 14 is etched, can also be partially etched by the active layer below described N-type line electrode 13.
In step S1305, can there be multiple setting the position of P type pad 11, and Fig. 5 a-Fig. 5 d is the special case during these are arranged.In Fig. 5 a, P type pad 11 is positioned at insulating barrier 15 on the surface, so P type pad 11 does not participate in CURRENT DISTRIBUTION, certain P type pad 11 can be positioned on the surface of insulating barrier 15, also can be embedded in insulating barrier 15, be not specifically limited here; In another one embodiment provided by the invention, as shown in Figure 5 c, P type pad 11 is positioned on transparency conducting layer 7 surface, and certain P type pad 11 can also be embedded in transparency conducting layer 7; In another embodiment provided by the invention, as fig 5d, P type pad 11 is positioned on p-type nitride semiconductor layer 5, and certain P type pad 11 can also be embedded in p-type nitride semiconductor layer 5; Certainly this P type pad 11 (can also contact with p-type nitride semiconductor layer 5 and transparency conducting layer 7) between described p-type nitride semiconductor layer 5 and transparency conducting layer 7 simultaneously, that is a part for P type pad 11 contacts with p-type nitride semiconductor layer 5, and a part contacts with transparency conducting layer 7; P type pad 11 (contacts with insulating barrier 15 and transparency conducting layer 7) between described insulating barrier 15 and transparency conducting layer 7 simultaneously, and that is a part for P type pad 11 contacts with insulating barrier 15, and a part contacts with transparency conducting layer 7; P type pad 11 also (can contact with p-type nitride semiconductor layer 5 and insulating barrier 15) between p-type nitride semiconductor layer 5 and insulating barrier 15 simultaneously; P type pad 11 can also at insulating barrier 15, between transparency conducting layer 7 and p-type nitride semiconductor layer 5 (namely be positioned at insulating barrier 15, transparency conducting layer 7 and p-type nitride semiconductor layer 5 contact) simultaneously, that is P type pad 11 some be positioned at that insulating barrier 15 contacts, a part is positioned at that transparency conducting layer 7 contacts, some is positioned at p-type nitride semiconductor layer 5 and contacts, P type pad 11 in the present embodiment is positioned on insulating barrier 15, is not specifically limited here to the particular location of P type pad 11.Be not specifically limited the shape of P type pad 11 in the present invention, P type pad 11 can be circle, two pentadecagons, square or oval, and in the present embodiment, P type pad is circular.
For the position of P molded line electrode 13 in step S1305, have multiple setting, Fig. 7 a-Fig. 7 d is the facilities of P molded line electrode 13.P molded line electrode 13 can be positioned at transparency conducting layer 7 on the surface, can also be embedded in transparency conducting layer 7; P molded line electrode 13 (can also contact with transparency conducting layer 7 and insulating barrier 15) between transparency conducting layer 7 and insulating barrier 15 simultaneously, and that is a part for P molded line electrode 13 contacts with transparency conducting layer 7, and a part contacts with insulating barrier 15; P molded line electrode 13 also its part can be positioned at described insulating barrier 15 on the surface, because P molded line electrode 13 can not be positioned at separately insulating barrier 15 on the surface, so be that a part is positioned at insulating barrier 15 on the surface; P molded line electrode 13 also can be positioned at described p-type nitride semiconductor layer 5 on the surface, and certain P molded line electrode can also be embedded in described p-type nitride semiconductor layer 5; P molded line electrode 13 also (can contact with described p-type nitride semiconductor layer 5 and transparency conducting layer 7) between described p-type nitride semiconductor layer 5 and transparency conducting layer 7 simultaneously, namely a part contacts with p-type nitride semiconductor layer 5, and a part contacts with transparency conducting layer 7); P molded line electrode 13 also (can contact with described p-type nitride semiconductor layer 5 and insulating barrier 15) between described p-type nitride semiconductor layer 5 and insulating barrier 15 simultaneously, namely a part contacts with described p-type nitride semiconductor layer 5, and a part contacts with insulating barrier 15); P molded line electrode 13 can also between described p-type nitride semiconductor layer 5, insulating barrier 15 and transparency conducting layer 7 (and between described p-type nitride semiconductor layer 5, insulating barrier 15 and transparency conducting layer 7) simultaneously, namely a part contacts with described p-type nitride semiconductor layer 5, a part contacts with insulating barrier 15, some contacts with transparency conducting layer 7, is not specifically limited here to the position of P molded line electrode 13.
Described P type pad 11 is the Ni layer be arranged in order from inside to outside, Al layer, middle Cr layer, 2nd Ni layer and Au layer composition, or the Ni layer be arranged in order from inside to outside, Al layer, middle Cr layer, Pt layer, Au layer forms, or the Ni layer be arranged in order from inside to outside, Al layer, 2nd Ni layer, Pt layer, Au layer forms, or the Ni layer be arranged in order from inside to outside, Al layer, Ti layer, Pt layer and Au layer composition, or the Ni layer be arranged in order from inside to outside, Al layer, Ti layer, Pt layer, Ti layer, Pt layer, Ti layer, Pt layer and Au layer composition, or the Cr layer be arranged in order from inside to outside, Al layer, middle Cr layer, Pt layer, Au layer forms, or the Cr layer be arranged in order from inside to outside, Al layer, 2nd Ni layer, Pt layer, Au layer forms.In above-mentioned several structure, Laminate construction thickness in often kind of structure is: the thickness of a Ni layer is 0.4-3nm, the thickness of Al layer is 50-300nm, the thickness of middle Cr layer is 10-300nm, the thickness of the thickness of the 2nd Ni layer to be the thickness of 10-300nm, Au layer be 200-3000nm, Pt layer is 10-300nm, the thickness of Ti layer is 10-300nm, and the thickness of a Cr layer is 0.4-5nm.
It should be noted that, the structure of the P type pad 11 in the present embodiment is a Ni layer, Al layer, the 2nd Ni layer, Pt layer and the Au layer composition be arranged in order from inside to outside, wherein, the thickness of the one Ni layer is 0.4-3nm, the thickness of Al layer is 50-300nm, the thickness of the thickness of the 2nd Ni layer to be the thickness of 10-300nm, Pt layer be 10-300nm, Au layer is 200-3000nm.And the structure of P molded line electrode can be identical with P type pad 11, also can not be identical, be not specifically limited here.N-type pad 12 is positioned on insulating barrier 15 surface, and such N-type pad 100% does not participate in CURRENT DISTRIBUTION, and such structure reaches the object more easily designing mask pattern.Be not specifically limited the shape of N-type pad 12 in the present invention, N-type pad 12 can be circle, two pentadecagons, square or oval, and the N-type pad 12 in the present embodiment is square.
In step S1305, there is multiple setting the position of N-type line electrode 14, composition graphs 8a-8d and Figure 10, and N-type line electrode 14 can be positioned on n-type nitride semiconductor layer 3 surface, also can be embedded in n-type nitride semiconductor layer 3; N-type line electrode 14 also can be positioned on transparency conducting layer 7, and wherein N-type line electrode 14 can be positioned on transparency conducting layer 7 surface, also can be embedded in transparency conducting layer 7; N-type line electrode 14 (can also contact with n-type nitride semiconductor layer 3 and insulating barrier 15) between n-type nitride semiconductor layer 3 and insulating barrier 15 simultaneously, namely a part contacts with described n-type nitride semiconductor layer 3, and a part contacts with insulating barrier 15; N-type line electrode 14 (can also contact with transparency conducting layer 7 and insulating barrier 15) between transparency conducting layer 7 and insulating barrier 15 simultaneously, and namely a part contacts with described transparency conducting layer 7, and a part contacts with insulating barrier 15; N-type line electrode 14 (can also contact with described n-type nitride semiconductor layer 3, transparency conducting layer 7 and insulating barrier 15) between n-type nitride semiconductor layer 3, transparency conducting layer 7 and insulating barrier 15 simultaneously, namely a part contacts with described n-type nitride semiconductor layer 3, a part contacts with transparency conducting layer 7, and some contacts with insulating barrier).The profile of Figure 10 is the profile of the N-type line electrode in Fig. 9 along K-L direction, and N-type line electrode 14 is now positioned on insulating barrier 15, can be positioned on insulating barrier 15 surface, also can be embedded in insulating barrier 15.
In the present invention, N-type pad 12 is the Ni layer be arranged in order from inside to outside, Al layer, middle Cr layer, 2nd Ni layer and Au layer composition, or the Ni layer be arranged in order from inside to outside, Al layer, middle Cr layer, Pt layer, Au layer forms, or the Ni layer be arranged in order from inside to outside, Al layer, 2nd Ni layer, Pt layer, Au layer forms, or the Ni layer be arranged in order from inside to outside, Al layer, Ti layer, Pt layer and Au layer composition, or the Ni layer be arranged in order from inside to outside, Al layer, Ti layer, Pt layer, Ti layer, Pt layer, Ti layer, Pt layer and Au layer composition, or the Cr layer be arranged in order from inside to outside, Al layer, middle Cr layer, Pt layer, Au layer forms, or the Cr layer be arranged in order from inside to outside, Al layer, 2nd Ni layer, Pt layer, Au layer forms.In above-mentioned several structure, wherein the thickness of a Ni layer is 0.4-3nm, the thickness of Al layer is 50-300nm, the thickness of middle Cr layer is 10-300nm, the thickness of the thickness of the 2nd Ni layer to be the thickness of 10-300nm, Au layer be 200-3000nm, Pt layer is 10-300nm, the thickness of Ti layer is 10-300nm, and the thickness of a Cr layer is 0.4-5nm.
In the present embodiment, the structure of N-type pad 12 is identical with the structure of P type pad 11, for a Ni layer, Al layer, the 2nd Ni layer, Pt layer and the Au layer composition be arranged in order from inside to outside, wherein, the thickness of a described Ni layer is 0.4-3nm, the thickness of described Al layer is 50-300nm, the thickness of described 2nd Ni layer is 10-300nm, and the thickness of described Pt layer is 10-300nm, and the thickness of described Au layer is 200-3000nm.Here the structure of N-type line electrode 14 and the structure of N-type pad 12 can be identical, also can not be identical, are not specifically limited here.
As can be seen here, in the present invention, the material of N-type pad 12 and P pad 11 or structure are identical, can not certainly be identical, are not specifically limited here.
As can be seen from the contrast of Fig. 3 and Fig. 1, the N-type pad 12 in the present invention is positioned at the same side, in same rectilinear direction with P type pad 11.And in prior art (as shown in Figure 1), N-type pad 12 and P type pad 11 are the positions at diagonal angle.N-type pad 12 of the present invention also can be positioned at diagonal position with the position of P type pad 11, and just preferably situation is positioned at the same side, is not specifically limited here for the particular location of N-type pad 12 with P type pad 11.Difference in height in this structure of the present invention between N-type pad 12 and P type pad 11, less than or equal to 300nm, is so more conducive to routing.Height in this structure of the present invention between N-type pad 12 with P type pad 11 also can be equal, is not specifically limited here.
As shown in Figure 11 a and Figure 11 b, owing to also having the structure of line bond pad (metal)-insulation layer-transparent conducting layer in structure in the present embodiment, here line bond pad refers to N-type pad 12 or P type pad 11, this structure is namely followed successively by P type pad 11 (or N-type pad 12), insulating barrier 15 and transparency conducting layer 7 from top to bottom, it is in fact a capacitance structure, so effectively can increase antistatic effect.
Also step is comprised: deposition current barrier layer is on p-type nitride semiconductor layer in another embodiment of the present invention, it is inner that this current barrier layer is positioned at described transparency conducting layer, and utilize gold-tinted etch process to define described current blocking layer pattern, etch current barrier layer again, finally remove photoresistance, obtain the epitaxial structure with current barrier layer.This step is between S1302 and S1303.As shown in Figure 7b, in an III light emitting semiconductor device, boss 16 upper surface is also provided with current barrier layer 6, can not certainly arrange this current barrier layer 6, is not specifically limited here to whether arranging current barrier layer 6 at boss 16 upper surface.If have current barrier layer 6 and transparency conducting layer 7 in embodiment simultaneously, then current barrier layer 6 is positioned at the inside of transparency conducting layer 7.
The specification of III group nitride compound semiconductor light emitting element is 1125um × 1125um.Shown in composition graphs 12a-Figure 12 c and Figure 13, this III nitride semiconductor devices comprises substrate 1, at described substrate 1 Epitaxial growth resilient coating 2, in described resilient coating 2 Epitaxial growth n-type nitride semiconductor layer 3, at the active layer 4 of described n-type nitride semiconductor layer 3 Epitaxial growth, at described active layer 4 Epitaxial growth p-type nitride semiconductor layer 5, manufacture method is:
S1301: grow successively from bottom to top at substrate 1, resilient coating 2, n-type nitride semiconductor layer 3, active layer 4 and described p-type nitride semiconductor layer 5 and form epitaxial structure, the upper surface of described epitaxial structure is the upper surface of p-type nitride semiconductor layer 5, this structure is epitaxial structure, it is for what obtain by manufacture craft of the prior art, and the method that described epitaxial structure makes chip comprises the following steps:
S1302: utilize gold-tinted etch process to define cam pattern, then etch described p-type nitride semiconductor layer and active layer, and expose described n-type nitride semiconductor layer, finally remove photoresistance, obtain boss;
S1303: structure chart as figure 12 a shows, deposit transparent conductive layer 7 on described p-type nitride-based semiconductor 5 or deposit transparent conductive layer on described p-type nitride-based semiconductor 5 and between n-type nitride semiconductor layer 3, gold-tinted etch process is utilized to define described pattern for transparent conductive layer, etch described transparency conducting layer again, finally remove photoresistance, obtain the boss that upper surface has transparency conducting layer 7;
Be that deposit transparent conductive layer 7 is on p-type nitride semiconductor layer 5, and use e-beam evaporation deposition ITO (tin indium oxide) when transparency conducting layer 7, be deposited on p-type nitride semiconductor layer 5, the thickness of transparency conducting layer 7 is 10-300nm further; And utilize gold-tinted etch process to define boss 16 pattern, again with etching solution etching transparency conducting layer 7, recycling ICP etching p-type nitride semiconductor layer 5 and active layer 4, and exposing n-type nitride semiconductor layer 3, with etching solution, transparency conducting layer 7 is inside contracted again, finally remove photoresistance, form the boss with transparency conducting layer 7, wherein ICP etching gas is BCl 3/ Cl 2/ Ar; Again Wafer is carried out high annealing, make to form good ohmic contact and penetrance between transparency conducting layer 7 and p-type nitride semiconductor layer 5.Annealing way quick anneal oven (RTA) short annealing, temperature is 560 DEG C, and the time is 3 minutes;
S1303: depositing insulating layer 15 is on the upper surface of described transparency conducting layer 7 and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier 15 and/or transparency conducting layer 7 again, finally remove photoresistance, obtain the boss with insulating barrier;
Further, structure chart as shown in Figure 12b, uses PECVD (plasma enhanced chemical vapor deposition method deposition) SiO 2when insulating barrier 15, SiO 2thickness is 50-300nm, and wherein power is 50W, and pressure is 850mTorr, and temperature is 200-400 DEG C, N 2o is 1000sccm, N2 is 400sccm, 5%SiH 4/ N2 is 400sccm;
S1304: gold-tinted peels off program defining P molded line electrode and N-type line electrode pattern, deposit described P molded line electrode and N-type line electrode simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining P type pad and N-type welding disk pattern, deposit described P type pad and N-type pad simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss.
In the present embodiment, as shown in Figure 12b, P molded line electrode 13 is deposited on described transparency conducting layer 7 structure chart, and N-type line electrode 14 is deposited in described n-type nitride semiconductor layer.P molded line electrode 13 is identical with N-type line electrode 14 structure, is Ti layer, Al layer, Ni layer and the Au layer composition be arranged in order from inside to outside, wherein, the thickness of described Ti layer is 0.4-5nm, the thickness of described Al layer is 150nm, and the thickness of described Ni layer is 50nm, and the thickness of described Au layer is 100nm.
Structure refers to Figure 12 c, gold-tinted peels off program defining P type pad 11 and N-type pad 12 pattern, utilizes and peels off processing procedure, remove photoresistance after using e-beam evaporation deposition P type pad 11 and N-type pad 12, wherein, P type pad 11 and N-type pad 12 are all deposited on insulating barrier 15.
S1305: finally described disk is carried out thinning, scribing, sliver, test, sorting.
Embodiment 2:
On the basis of embodiment 1, Fig. 3 is the vertical view of the III light emitting semiconductor device that the present embodiment provides, and Fig. 4 a to-Fig. 8 d is the sectional view of Fig. 3 respectively.
Fig. 5 a-Fig. 5 d, Fig. 6 a, Fig. 6 b are the P type pad 11 of Fig. 3 and N-type pad 12 sectional view along M-N and C-D hatching respectively, can find out that P type pad 11 and N-type pad 12 are all positioned at the top of active layer 4, wherein the structure of Fig. 5 a, Fig. 5 b, Fig. 6 a, Fig. 6 b can be positioned at any position above insulating barrier, because do not affect CURRENT DISTRIBUTION, therefore more easily design mask pattern.
Be insulating barrier below P type pad 11 in Fig. 5 a, Fig. 5 b, Fig. 6 a and Fig. 6 b and N-type pad 12, so do not participate in CURRENT DISTRIBUTION, therefore this structure only has P molded line electrode 13, N-type line electrode 14 participates in CURRENT DISTRIBUTION.The P type pad 11 of Fig. 5 c all participates in CURRENT DISTRIBUTION.And Fig. 5 d participates in the situation of CURRENT DISTRIBUTION, depending on the ohmic contact situation of P type pad 11 with p-type nitride semiconductor layer 5.P type pad 11 can be there is in Fig. 5 a-Fig. 5 d structure simultaneously, or appoint the two or appoint three or be present in P type pad 11 simultaneously, be insulating barrier below the N-type pad 12 of Fig. 6 a and Fig. 6 b, so neither participate in CURRENT DISTRIBUTION, these two kinds of structures of Fig. 6 a and Fig. 6 b can exist with luminescent device simultaneously.
Insulating barrier below the P type pad 11 of Fig. 5 a, 6a and N-type pad 12, so do not participate in CURRENT DISTRIBUTION, but the yield of antistatic effect can be increased, because structure is line bond pad (metal)/insulating barrier/transparency conducting layer, this structure is capacitance structure, so be used on light emitting semiconductor device by this structure, equivalent electric circuit is as Figure 11 b, suppose that the radius of circular pad is 50 μm, circular pad area S is 7.85 × 10 -9m 2, SiO in the present embodiment 2for insulating barrier, SiO 2thickness d is 200nm, relative dielectric constant ε rbe 4, permittivity of vacuum ε 0be 8.85 × 10 -12f/m, substitutes into capacitance equation C=ε 0ε rs/d, as shown in fig. lla, obtains a circular pad and produces electric capacity 1.39pF, can increase anlistatig ability.
Fig. 7 a-Fig. 8 d is the P molded line electrode 13 of Fig. 3 respectively, the sectional view of N-type line electrode 14, Figure 10 is the sectional view of the N-type line electrode 14 of Fig. 9, the P electrode of conventional process, N electrode (comprises P/N type pad 11, 12, and P/N molded line electrode 13, 14) be disposable plating, but P-type electrode 8 and N-type electrode 9 can once have been plated in the present invention, also can by P type pad 11, N-type pad 12 and P molded line electrode 13, N-type line electrode 14 plates respectively, at this P type pad 11, N-type pad 12 and P molded line electrode 13, N-type line electrode 14 structure component can be the same or different, Fig. 7 a-Fig. 7 d structure can exist simultaneously or appoint the two or appoint three to exist or individualism simultaneously, but the usual not individualism of the structure of Fig. 7 d, because do not participate in CURRENT DISTRIBUTION, so meeting and Fig. 7 a, Fig. 7 b uses together with the structure of Fig. 7 c, Fig. 8 c in addition, the usual not individualism of structure of Fig. 8 d and Figure 10, because do not participate in CURRENT DISTRIBUTION, so can use together with the structure in Fig. 8 a or Fig. 8 b.
Embodiment 3:
The present embodiment provides a kind of and has the manufacture method that new construction applies to III group nitride compound semiconductor light emitting element, and the specification of luminescent device is 1125um × 1125um, S1201:
This III nitride semiconductor devices comprises substrate 1, at described substrate 1 Epitaxial growth resilient coating 2, in described resilient coating 2 Epitaxial growth n-type nitride semiconductor layer 3, at the active layer 4 of described n-type nitride semiconductor layer 3 Epitaxial growth, at described active layer 4 Epitaxial growth p-type nitride semiconductor layer 5, as shown in fig. 4 a, the substrate 1 set gradually from bottom to top, resilient coating 2, n-type nitride semiconductor layer 3, active layer 4 and p-type nitride semiconductor layer 5, these five layers form epitaxial structure, the upper surface of epitaxial structure is the upper surface of p-type nitride semiconductor layer, its chip manufacture method comprises the following steps:
The first step: structure chart as figure 12 a shows, deposit transparent conductive layer 7 is on p-type nitride semiconductor layer 5, etch transparency conducting layer 7 again, p-type nitride semiconductor layer 5 and active layer 4, and exposing n-type nitride semiconductor layer 3, with etching solution, transparency conducting layer 7 is inside contracted again, finally remove photoresistance, obtain the boss that upper surface has transparency conducting layer, particularly, deposit transparent conductive layer 7 is on p-type nitride semiconductor layer 5, use e-beam evaporation deposition ITO (tin indium oxide) when transparency conducting layer 7, be deposited on p-type nitride semiconductor layer 5, the thickness of transparency conducting layer 7 is 200nm, and utilize gold-tinted etch process to define boss 16 pattern, again with etching solution etching transparency conducting layer 7, recycling ICP etching p-type nitride semiconductor layer 5 and active layer 4, and exposing n-type nitride semiconductor layer 3, with etching solution, transparency conducting layer 7 is inside contracted again, finally remove photoresistance, form the nitride semiconductor structure with boss, wherein ICP etching gas is BCl 3/ Cl 2/ Ar, again Wafer is carried out high annealing, make to form good ohmic contact and penetrance between transparency conducting layer 7 and p-type nitride semiconductor layer 5.Annealing way quick anneal oven (RTA) short annealing, temperature is 560 DEG C, and the time is 3 minutes;
Second step: structure chart as shown in Figure 12b, depositing insulating layer 15 is on the upper surface of transparency conducting layer 7 and the surface of described boss 16, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier 15 and/or transparency conducting layer 7 again, finally remove photoresistance, obtain the boss with insulating barrier; Use PECVD (plasma enhanced chemical vapor deposition method deposition) SiO 2when insulating barrier 15, SiO 2thickness is 100nm, and wherein power is 50W, and pressure is 850mTorr, and temperature is 300 DEG C, N 2o is 1000sccm, N2 is 400sccm, 5%SiH 4/ N2 is 400sccm;
3rd step: utilize gold-tinted to peel off the pattern of program defining P molded line electrode and N-type line electrode, utilizes stripping processing procedure after deposition P molded line electrode and N-type line electrode, finally removes photoresistance.Particularly, structure chart as shown in figure lib, utilize gold-tinted stripping program defining will participate in the pattern of CURRENT DISTRIBUTION, after using electron beam evaporation plating deposition P molded line electrode 13 and N-type line electrode 14, recycling is peeled off and is supported, and removes photoresistance, wherein, P molded line electrode 13 is deposited on described transparency conducting layer, and N-type line electrode 14 is deposited in described n-type nitride semiconductor layer.P molded line electrode 13 is identical with N-type line electrode 14 structure, is Ti layer, Al layer, Ni layer and the Au layer composition be arranged in order from inside to outside, wherein, the thickness of described Ti layer is 2nm, the thickness of described Al layer is 150nm, and the thickness of described Ni layer is 50nm, and the thickness of described Au layer is 100nm.
4th step: gold-tinted peels off the pattern of program defining P type pad 11 and N-type pad 12, utilize after depositing P type pad 11 and N-type pad 12 simultaneously and peel off processing procedure, remove photoresistance again, make disk, particularly, gold-tinted peels off program defining P type pad 11 and N-type pad 12 pattern, utilize after using e-beam evaporation deposition P type pad 11 and N-type pad 12 and peel off processing procedure, remove photoresistance, wherein, P type pad 11 and N-type pad 12 are all deposited on insulating barrier 15.Its structure refers to Figure 12 c; P type pad 11 is identical with N-type pad 12 structure, a Ni layer, Al layer, the 2nd Ni layer, Pt layer and Au layer all for being arranged in order by the top layer outside (namely from inside to outside) of nitride semiconductor layer form, wherein, the thickness of a described Ni layer is 1nm, the thickness of described Al layer is 150nm, the thickness of described 2nd Ni layer is 50nm, and the thickness of described Pt layer is 60nm, and the thickness of described Au layer is 1500nm.
5th step: finally described disk is carried out thinning, scribing, sliver, test, sorting.
Embodiment 4:
Make III group nitride compound semiconductor light emitting element, specification is 300um × 700um.Shown in composition graphs 14a-Figure 14 c and Figure 13,
S1301: grow successively from bottom to top at substrate 1, resilient coating 2, n-type nitride semiconductor layer 3, active layer 4 and described p-type nitride semiconductor layer 5 and form epitaxial structure, the upper surface of described epitaxial structure is the upper surface of p-type nitride semiconductor layer 5, this structure is epitaxial structure, it is what obtained by manufacture craft of the prior art
The method that described epitaxial structure makes chip comprises the following steps:
S1302: structure chart as shown in figures 14a, method is deposit transparent conductive layer 7, use e-beam evaporation or sputtering method deposition ITO (tin indium oxide) when transparency conducting layer 7, be deposited on p-type nitride semiconductor layer 5, the thickness of transparency conducting layer 7 is 10-300nm; And utilize gold-tinted etch process to define boss 16 pattern, recycling ICP etches transparency conducting layer 7, p-type nitride semiconductor layer 5 and active layer 4, and exposing n-type nitride semiconductor layer 3, with etching solution, transparency conducting layer 7 is inside contracted again, finally remove photoresistance, form the nitride semiconductor structure with boss, wherein ICP etching gas is BCl 3/ Cl 2/ Ar; Again Wafer is carried out high annealing, make to form good ohmic contact and penetrance between transparency conducting layer 7 and p-type nitride semiconductor layer 5.Annealing way quick anneal oven (RTA) short annealing, temperature is 560 DEG C, and the time is 3 minutes.
S1303: structure chart as shown in fig. 14b, uses PECVD (plasma enhanced chemical vapor deposition method deposition) SiO 2when insulating barrier 15, SiO 2thickness is 50-300nm, and wherein power is 50W, and pressure is 850mTorr, and temperature is 200-400 DEG C, N 2o is 1000sccm, N2 is 400sccm, 5%SiH 4/ N 2for 400sccm; Utilize gold-tinted etch process to define the pattern that will participate in CURRENT DISTRIBUTION, recycling dry method or wet etching insulating barrier 15, finally remove photoresistance, obtain the boss with insulating barrier;
Insulating barrier in the present embodiment is silicon dioxide, certainly, can also deposit one or both in alundum (Al2O3), titanium dioxide, tantalum pentoxide, niobium pentaoxide, silicon oxynitride or silicon nitride as insulating barrier, be not specifically limited here.
S1304: gold-tinted peels off program defining P-type electrode 8 and N-type electrode 9 (comprises P type pad 11, N-type pad 12 and P molded line electrode 13, N-type line electrode 14) pattern, use e-beam evaporation to deposit P-type electrode 8 and N-type electrode 9 simultaneously, remove photoresistance again, make disk, wherein, described N-type electrode 9 comprises: N-type line electrode 14 and N-type pad 12, described N-type line electrode 14 is connected with described N-type pad 12, described N-type line electrode 14 is deposited on described boss, active layer below described N-type line electrode 14 is etched, can also be partially etched by the active layer below described N-type line electrode 13, described N-type pad 12 is deposited on the top of described active layer 4, described P-type electrode comprises: P type pad 11 and P molded line electrode 13, described P-type electrode 8 is deposited on described boss.Its structure refers to Figure 14 c; In the present embodiment, P-type electrode 8 is identical with N-type electrode 9 structure, and a Ni layer, Al layer, the 2nd Ni layer, Pt layer and the Au layer all for being outwards arranged in order by the top layer of nitride semiconductor layer, the thickness of the one Ni layer is 0.4-3nm, the thickness of Al layer is 50-300nm, the thickness of the 2nd Ni layer is 10-300nm, the thickness of Pt layer is the thickness of 10-300nm, Au layer is 50-3000nm.Difference in height after deposition between N-type pad and described P type pad is less than or equal to 300nm.
Be that N-type pad 12 is deposited on described insulating barrier 15 on the surface in this step, can also be embedded in insulating barrier 15.And the deposition position of N-type line electrode 14 has multiple possibility, can be deposited on (or being embedded in n-type nitride semiconductor layer 3) on the surface of described n-type nitride semiconductor layer 3, also can be deposited between described n-type nitride semiconductor layer 3 and insulating barrier 15 and (namely contact with n-type nitride semiconductor layer 3 and insulating barrier 15 simultaneously, a part contacts with n-type nitride semiconductor layer 3, a part contacts with insulating barrier 15), on the basis of first two deposition conditions N-type line electrode 14 can also be deposited on insulating barrier 15 on the surface (but this situation can not occur separately, can only match with first two deposition conditions, namely part is deposited on insulating barrier 15 on the surface).
For the deposition position of P type pad 11 and P molded line electrode 13, also multiple possibility is had: P type pad 11 can be deposited on described insulating barrier 15 (can be deposited on insulating barrier 15 on the surface, also can be embedded in insulating barrier 15), can also deposit and (transparency conducting layer 7 can be deposited on the surface over transparent conductive layer, also can be embedded in transparency conducting layer 7), can also be deposited between insulating barrier 15 and transparency conducting layer 7 and (namely contact with insulating barrier 15 and transparency conducting layer 7 simultaneously, a part contacts with insulating barrier 15, a part contacts with transparency conducting layer 7, lower same).Deposition position for P molded line electrode 13 has following several possibility: P molded line electrode 13 can be deposited on described transparency conducting layer 7 on the surface, can also be deposited between described transparency conducting layer 7 and insulating barrier 15 and (namely contact with insulating barrier 15 and transparency conducting layer 7 simultaneously, a part contacts with insulating barrier 15, a part contacts with transparency conducting layer 7, lower same), the basis of first two deposition position can also be deposited on described insulating barrier 15 on the surface, but P molded line electrode 13 can only be part to be deposited on insulating barrier 15.
Certainly, P type pad 11 here, N-type pad 12, P molded line electrode 13, N-type line electrode 14 can be that structure is identical, is the Ni layer be arranged in order from inside to outside, Al layer, middle Cr layer, 2nd Ni layer and Au layer composition still can be the Ni layers be arranged in order from inside to outside, Al layer, middle Cr layer, Pt layer, Au layer forms, and also can be the Ni layer be arranged in order from inside to outside, Al layer, 2nd Ni layer, Pt layer, Au layer forms, and also can be the Ni layer be arranged in order from inside to outside, Al layer, Ti layer, Pt layer and Au layer composition also can be the Ni layers be arranged in order from inside to outside, Al layer, Ti layer, Pt layer, Ti layer, Pt layer, Ti layer, Pt layer and Au layer composition also can be the Cr layers be arranged in order from inside to outside, Al layer, middle Cr layer, Pt layer, Au layer forms, a Cr layer that can also be arranged in order from inside to outside, Al layer, 2nd Ni layer, Pt layer, Au layer forms, the thickness of a wherein said Ni layer is 0.4-3nm, the thickness of Al layer is 50-300nm, the thickness of middle Cr layer is 10-300nm, and the thickness of the 2nd Ni layer is the thickness of 10-300nm, Au layer is 200-3000nm, the thickness of Pt layer is 10-300nm, the thickness of Ti layer is 10-300nm, and the thickness of a Cr layer is 0.4-5nm, here to P type pad 11, N-type pad 12, the structure of P molded line electrode 13 and N-type line electrode 14 is not specifically limited.
S1305: finally described disk is carried out thinning, scribing, back of the body plating, sliver, test, sorting.
Contrast test:
Contrast test: be III group nitride compound semiconductor light emitting element of prior art, as depicted in figs. 1 and 2: comprise substrate 1, at described substrate 1 Epitaxial growth resilient coating 2, in the n-type nitride semiconductor layer 3 of described resilient coating 2 Epitaxial growth, at the active layer 4 of described n-type nitride semiconductor layer 3 Epitaxial growth, at the p-type nitride semiconductor layer 5 of described active layer 4 Epitaxial growth, difference deposition current barrier layer 6 on described p-type nitride-based semiconductor 5, transparency conducting layer 7 and P-type electrode 8 (comprise P type pad 11, P molded line electrode 13), passing through etching p-type nitride semiconductor layer 5 and active layer 4, and exposing n-type nitride semiconductor layer 3 is formed N-type electrode 9 and (comprise N-type pad 12, N-type line electrode 14), last deposit passivation layer 10.Its Making programme is as follows:
Existing III group nitride compound semiconductor light emitting element is obtained by five steps, and Details as Follows:
(1) boss is made: the exposing n-type nitride semiconductor layer by etching p-type nitride semiconductor layer and active layer;
(2) current barrier layer is made: deposition current barrier layer is on p-type nitride semiconductor layer;
(3) transparency conducting layer is made: be deposited on p-type nitride semiconductor layer and current barrier layer;
(4) make P-type electrode and N-type electrode: together with deposition P-type electrode and N-type electrode, P-type electrode comprises P type pad and P molded line electrode, described P molded line electrode deposition over transparent conductive layer, described P type pad is deposited on described p-type nitride semiconductor layer, and described N-type electrode is deposited in n-type nitride semiconductor layer;
(5) make passivation layer: last deposit passivation layer, and perforate allows the N-type pad in P type pad and N-type electrode expose.
Experimental condition is identical with embodiment 4, is XY2 by prior art products label, the method provided according to embodiment 3 make product code numbering S2, detect under identical conditions, test result as shown in Table 1 and Table 2:
The antistatic effect comparing data table of both table 1 S2, XY2
Table 1 is the data of both S2, XY2 antistatic effect, respectively at the yield of Human Body Model 2000 and 4000 volts, as can be known from Table 1, the yield of S2 antistatic effect is much better than XY2, and 2000 volts time, the yield of S2 is between 90-100%, and the yield of XY2 is between 75-85%, 4000 volts time, the yield of S2 is still between 90-100%, and the yield of XY2 is lower between 65-80% at 4000 volts.
The comparing data table of both table 2 S2, XY2
As can be known from Table 2, S2 revers voltage (input current is-10uA) and electric leakage (input voltage is-5V) characteristic similar; In operating voltage (input current is 350mA), S2 and XY2 compares, voltage drop 0.07V; In brightness, the mean flow rate of S2 is the mean flow rate of 125.1lm (379.58mW), XY2 is 120.3lm (364.21mW), and luminosity improves 4%; Comprehensive yield >85%, good stability.
Compared with prior art, the manufacture method of the III light emitting semiconductor device described in the application, has the following advantages:
(1) manufacture method provided by the invention, production cycle is shortened, greatly reduce production cost, and the active layer reduced below N-type pad, to solve the etched many problems of active layer, add active layer thus improve photoelectric characteristic, reducing the active layer below N-type pad, the active layer that can also reduce below part N-type line electrode, which increases light-emitting area.Because light-emitting area becomes large, so operating voltage declines, brightness is risen.
(2) the present invention also provides the structure of P type pad or N-type pad can be positioned at any position above insulating barrier, so do not participate in CURRENT DISTRIBUTION completely, a wired electrodes participates in CURRENT DISTRIBUTION, therefore more easily designs mask pattern.The present invention reduces the active layer below N-type pad, and because light-emitting area becomes large, the contact resistance of transparency conducting layer and p-type nitride semiconductor layer declines, so operating voltage declines;
(3) in method of the present invention, transparency conducting layer is made together with mesa pattern, not only simplify one processing procedure, also solve the problem that transparency conducting layer is aimed at mesa pattern.In addition P type pad, P molded line electrode and N-type line electrode 14 pattern that will participate in CURRENT DISTRIBUTION can be defined in the present invention, so can lean on the region of etching isolation layer to define the pattern that will participate in CURRENT DISTRIBUTION, so mask set is easier.
(4) the present invention also provides a kind of new construction to be line bond pad (metal)/insulating barrier/transparency conducting layer, and this structure is capacitance structure, can increase the yield of antistatic effect;
(5) difference in height between P type pad of the prior art or N-type pad reaches 1100-1600nm, and the difference in height in the present invention between P type pad and N-type pad is less than or equal to 300nm, is of the present inventionly compared to existing technology more conducive to routing than tradition.
(6) the present invention reduces the active layer below N-type pad, and the percentage that the active layer below chip size less reduction N-type pad accounts for light-emitting area is more, so more small size operating voltage declines more, brightness is risen more.
(7) in prior art, P-type electrode or N-type electrode (comprising P type pad, N-type pad, P molded line electrode and N-type line electrode) are disposable platings, but the P type pad in the present invention, N-type pad and P molded line electrode, N-type line electrode can also can plate respectively in disposable plating, reach better ohmic contact.
Above-mentioned explanation illustrate and describes some preferred embodiments of the application, but as previously mentioned, be to be understood that the application is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in application contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from the spirit and scope of the application, then all should in the protection range of the application's claims.
The invention discloses the manufacture method of an A1 III light emitting semiconductor device, it is characterized in that, comprise the following steps:
Substrate, resilient coating, n-type nitride semiconductor layer, active layer and p-type nitride semiconductor layer grow successively from bottom to top and form epitaxial structure, and the upper surface of described epitaxial structure is the upper surface of described p-type nitride semiconductor layer;
Utilize gold-tinted etch process to define cam pattern, then etch described p-type nitride semiconductor layer and active layer, and expose described n-type nitride semiconductor layer, finally remove photoresistance, obtain boss;
Deposit transparent conductive layer on described p-type nitride-based semiconductor or deposit transparent conductive layer on described p-type nitride-based semiconductor and between n-type nitride semiconductor layer, gold-tinted etch process is utilized to define described pattern for transparent conductive layer, etch described transparency conducting layer again, finally remove photoresistance, obtain the boss that upper surface has transparency conducting layer;
Depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier;
Gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss,
Finally described disk is carried out thinning, scribing, sliver, test, sorting.
The manufacture method of A2, III light emitting semiconductor device according to claim A1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer, on the upper surface of described transparency conducting layer and the surface of described boss, utilizes gold-tinted etch process to define the pattern that will participate in CURRENT DISTRIBUTION, then etches described insulating barrier, finally remove photoresistance, obtain the boss with insulating barrier.
The manufacture method of A3, III light emitting semiconductor device according to claim A1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described insulating barrier and transparency conducting layer continuously again, finally remove photoresistance, obtain the boss with insulating barrier.
The manufacture method of A4, III light emitting semiconductor device according to claim A1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier again, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier.
The manufacture method of A5, III light emitting semiconductor device according to claim A1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer is on the upper surface of transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define pattern, the again etching isolation layer that will participate in CURRENT DISTRIBUTION, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described insulating barrier and transparency conducting layer continuously again, finally remove photoresistance, obtain the boss with insulating barrier.
The manufacture method of A6, III light emitting semiconductor device according to claim A1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer is on the upper surface of transparency conducting layer and the surface of described boss, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described insulating barrier and transparency conducting layer continuously again, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier again, finally remove photoresistance, obtain the boss with insulating barrier.
The manufacture method of A7, III light emitting semiconductor device according to claim A1, is characterized in that, described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, then removes photoresistance, make disk, be further
Described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposits described P-type electrode and N-type electrode simultaneously, and processing procedure is peeled off in rear utilization, then removes photoresistance, makes disk.
The manufacture method of A8, III light emitting semiconductor device according to claim A1, is characterized in that, described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, then removes photoresistance, make disk, be further
Gold-tinted peels off program defining P molded line electrode and N-type line electrode pattern, deposit described P molded line electrode and N-type line electrode simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining P type pad and N-type welding disk pattern, deposits described P type pad and N-type pad simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
The manufacture method of A9, III light emitting semiconductor device according to claim A1, is characterized in that, described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, then removes photoresistance, make disk, be further
Gold-tinted peels off program defining P type pad and N-type welding disk pattern, deposit described P type pad and N-type pad simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining P molded line electrode and N-type line electrode pattern, deposits described P molded line electrode and N-type line electrode simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
The manufacture method of A10, III light emitting semiconductor device according to claim A1, is characterized in that, described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, then removes photoresistance, make disk, be further
Gold-tinted peels off program defining P type pad and P molded line electrode pattern, deposit described P type pad and P molded line electrode simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining N-type pad and N-type line electrode pattern, deposits described N-type pad and N-type line electrode simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
The manufacture method of A11, III light emitting semiconductor device according to claim A1, is characterized in that, described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, then removes photoresistance, make disk, be further
Gold-tinted peels off program defining N-type pad and N-type line electrode pattern, deposit described N-type pad and N-type line electrode simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining P type pad and P molded line electrode pattern, deposits described P type pad and P molded line electrode simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
The manufacture method of A12, III light emitting semiconductor device according to claim A1, it is characterized in that, described method also comprises step: deposition current barrier layer is on p-type nitride semiconductor layer, it is inner that this current barrier layer is positioned at described transparency conducting layer, and utilize gold-tinted etch process to define described current blocking layer pattern, etch current barrier layer again, finally remove photoresistance, obtain the epitaxial structure with current barrier layer.
A13, the manufacture method of III light emitting semiconductor device according to claim A1, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described N-type pad is positioned on described insulating barrier;
Described N-type line electrode is positioned in described n-type nitride semiconductor layer.
A14, the manufacture method of III light emitting semiconductor device according to claim A1, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described N-type pad is positioned on described insulating barrier;
Described N-type line electrode is positioned on described transparency conducting layer.
A15, the manufacture method of III light emitting semiconductor device according to claim A1, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described N-type pad is positioned on described insulating barrier;
Described N-type line electrode is positioned on described n-type nitride semiconductor layer and insulating barrier.
A16, the manufacture method of III light emitting semiconductor device according to claim A1, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described N-type pad is positioned on described insulating barrier;
Described N-type line electrode is positioned on described transparency conducting layer and insulating barrier.
A17, the manufacture method of III light emitting semiconductor device according to claim A1, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described N-type pad is positioned on described insulating barrier;
Described N-type line electrode is positioned on described n-type nitride semiconductor layer and transparency conducting layer.
A18, the manufacture method of III light emitting semiconductor device according to claim A1, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described N-type pad is positioned on described insulating barrier;
Described N-type line electrode is positioned on n-type nitride semiconductor layer and transparency conducting layer and insulating barrier.
A19, the manufacture method of III light emitting semiconductor device according to claim A1, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described N-type pad is positioned on described insulating barrier;
Described N-type line electrode is positioned on described insulating barrier.
A20, the manufacture method of III light emitting semiconductor device according to any one of claim A1 to A19, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described P type pad is positioned on described insulating barrier;
Described P molded line electrode is on described transparency conducting layer or between described transparency conducting layer and insulating barrier or partly on described insulating barrier or on described p-type nitride semiconductor layer or between described p-type nitride semiconductor layer and transparency conducting layer or between described p-type nitride semiconductor layer and insulating barrier or between described p-type nitride semiconductor layer, insulating barrier and transparency conducting layer.
A21, the manufacture method of the III light emitting semiconductor device according to claim A19, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described P type pad is positioned on described transparency conducting layer;
Described P molded line electrode is on described transparency conducting layer or between described transparency conducting layer and insulating barrier or partly on described insulating barrier or on described p-type nitride semiconductor layer or between described p-type nitride semiconductor layer and transparency conducting layer or between described p-type nitride semiconductor layer and insulating barrier or between described p-type nitride semiconductor layer, insulating barrier and transparency conducting layer.
A22, the manufacture method of the III light emitting semiconductor device according to claim A19, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described P type pad is positioned on described p-type nitride semiconductor layer;
Described P molded line electrode is on described transparency conducting layer or between described transparency conducting layer and insulating barrier or partly on described insulating barrier or on described p-type nitride semiconductor layer or between described p-type nitride semiconductor layer and transparency conducting layer or between described p-type nitride semiconductor layer and insulating barrier or between described p-type nitride semiconductor layer, insulating barrier and transparency conducting layer.
A23, the manufacture method of the III light emitting semiconductor device according to claim A19, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described P type pad is between described insulating barrier and transparency conducting layer;
Described P molded line electrode is on described transparency conducting layer or between described transparency conducting layer and insulating barrier or partly on described insulating barrier or on described p-type nitride semiconductor layer or between described p-type nitride semiconductor layer and transparency conducting layer or between described p-type nitride semiconductor layer and insulating barrier or between described p-type nitride semiconductor layer, insulating barrier and transparency conducting layer.
A24, the manufacture method of the III light emitting semiconductor device according to claim A19, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described P type pad is between described p-type nitride semiconductor layer and transparency conducting layer;
Described P molded line electrode is on described transparency conducting layer or between described transparency conducting layer and insulating barrier or partly on described insulating barrier or on described p-type nitride semiconductor layer or between described p-type nitride semiconductor layer and transparency conducting layer or between described p-type nitride semiconductor layer and insulating barrier or between described p-type nitride semiconductor layer, insulating barrier and transparency conducting layer.
A25, the manufacture method of the III light emitting semiconductor device according to claim A19, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described P type pad is between described insulating barrier and p-type nitride semiconductor layer;
Described P molded line electrode is on described transparency conducting layer or between described transparency conducting layer and insulating barrier or partly on described insulating barrier or on described p-type nitride semiconductor layer or between described p-type nitride semiconductor layer and transparency conducting layer or between described p-type nitride semiconductor layer and insulating barrier or between described p-type nitride semiconductor layer, insulating barrier and transparency conducting layer.
A26, the manufacture method of the III light emitting semiconductor device according to claim A19, it is characterized in that, gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss, be further,
Described P type pad is between described insulating barrier, transparency conducting layer and p-type nitride semiconductor layer;
Described P molded line electrode is on described transparency conducting layer or between described transparency conducting layer and insulating barrier or partly on described insulating barrier or on described p-type nitride semiconductor layer or between described p-type nitride semiconductor layer and transparency conducting layer or between described p-type nitride semiconductor layer and insulating barrier or between described p-type nitride semiconductor layer, insulating barrier and transparency conducting layer.
The manufacture method of A27, III light emitting semiconductor device according to claim A19, it is characterized in that, described P type pad is identical with N-type pad structure, further,
Described P type pad and N-type pad are the Ni layer be arranged in order from inside to outside, Al layer, middle Cr layer, 2nd Ni layer and Au layer composition, or the Ni layer be arranged in order from inside to outside, Al layer, middle Cr layer, Pt layer, Au layer forms, or the Ni layer be arranged in order from inside to outside, Al layer, 2nd Ni layer, Pt layer, Au layer forms, or the Ni layer be arranged in order from inside to outside, Al layer, Ti layer, Pt layer and Au layer composition, or the Ni layer be arranged in order from inside to outside, Al layer, Ti layer, Pt layer, Ti layer, Pt layer, Ti layer, Pt layer and Au layer composition, or the Cr layer be arranged in order from inside to outside, Al layer, middle Cr layer, Pt layer, Au layer forms, or the Cr layer be arranged in order from inside to outside, Al layer, 2nd Ni layer, Pt layer, Au layer forms.
The manufacture method of A28, III light emitting semiconductor device according to claim A27, it is characterized in that, described P type pad and N-type pad structure, further, the thickness of a wherein said Ni layer is 0.4-3nm, the thickness of Al layer is 50-300nm, and the thickness of middle Cr layer is 10-300nm, and the thickness of the 2nd Ni layer is 10-300nm, the thickness of Au layer is 50-3000nm, the thickness of Pt layer is the thickness of 10-300nm, Ti layer is 10-300nm, and the thickness of a Cr layer is 0.4-5nm.
The manufacture method of A29, III light emitting semiconductor device according to claim A19, it is characterized in that, the difference in height between described N-type pad and described P type pad is less than or equal to 300nm.
The manufacture method of A30, III light emitting semiconductor device according to claim A1, it is characterized in that, described insulating barrier is one or more insulating barriers made in alundum (Al2O3), silicon dioxide, titanium dioxide, tantalum pentoxide, niobium pentaoxide, silicon oxynitride or silicon nitride.

Claims (10)

1. a manufacture method for III light emitting semiconductor device, is characterized in that, comprises the following steps:
Substrate, resilient coating, n-type nitride semiconductor layer, active layer and p-type nitride semiconductor layer grow successively from bottom to top and form epitaxial structure, and the upper surface of described epitaxial structure is the upper surface of described p-type nitride semiconductor layer;
Utilize gold-tinted etch process to define cam pattern, then etch described p-type nitride semiconductor layer and active layer, and expose described n-type nitride semiconductor layer, finally remove photoresistance, obtain boss;
Deposit transparent conductive layer on described p-type nitride-based semiconductor or deposit transparent conductive layer on described p-type nitride-based semiconductor and between n-type nitride semiconductor layer, gold-tinted etch process is utilized to define described pattern for transparent conductive layer, etch described transparency conducting layer again, finally remove photoresistance, obtain the boss that upper surface has transparency conducting layer;
Depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier;
Gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, remove photoresistance again, make disk, wherein, described N-type electrode comprises: N-type line electrode and N-type pad, described N-type line electrode is connected with described N-type pad, described N-type line electrode is deposited on described boss, active layer below the etched or described N-type line electrode of active layer below described N-type line electrode is partially etched, described N-type pad is deposited on the top of described active layer, described P-type electrode comprises: P type pad and P molded line electrode, described P-type electrode is deposited on described boss,
Finally described disk is carried out thinning, scribing, sliver, test, sorting.
2. the manufacture method of III light emitting semiconductor device according to claim 1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer, on the upper surface of described transparency conducting layer and the surface of described boss, utilizes gold-tinted etch process to define the pattern that will participate in CURRENT DISTRIBUTION, then etches described insulating barrier, finally remove photoresistance, obtain the boss with insulating barrier.
3. the manufacture method of III light emitting semiconductor device according to claim 1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described insulating barrier and transparency conducting layer continuously again, finally remove photoresistance, obtain the boss with insulating barrier.
4. the manufacture method of III light emitting semiconductor device according to claim 1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier again, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier.
5. the manufacture method of III light emitting semiconductor device according to claim 1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer is on the upper surface of transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define pattern, the again etching isolation layer that will participate in CURRENT DISTRIBUTION, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described insulating barrier and transparency conducting layer continuously again, finally remove photoresistance, obtain the boss with insulating barrier.
6. the manufacture method of III light emitting semiconductor device according to claim 1, it is characterized in that, described depositing insulating layer is on the upper surface of described transparency conducting layer and the surface of described boss, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier and/or transparency conducting layer again, finally remove photoresistance, obtain the boss with insulating barrier, be further
Depositing insulating layer is on the upper surface of transparency conducting layer and the surface of described boss, utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer or utilize gold-tinted etch process define will with the contact patterns of described p-type nitride semiconductor layer and n-type nitride semiconductor layer, etch described insulating barrier and transparency conducting layer continuously again, gold-tinted etch process is utilized to define the pattern that will participate in CURRENT DISTRIBUTION, etch described insulating barrier again, finally remove photoresistance, obtain the boss with insulating barrier.
7. the manufacture method of III light emitting semiconductor device according to claim 1, is characterized in that, described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, then removes photoresistance, make disk, be further
Described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposits described P-type electrode and N-type electrode simultaneously, and processing procedure is peeled off in rear utilization, then removes photoresistance, makes disk.
8. the manufacture method of III light emitting semiconductor device according to claim 1, is characterized in that, described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, then removes photoresistance, make disk, be further
Gold-tinted peels off program defining P molded line electrode and N-type line electrode pattern, deposit described P molded line electrode and N-type line electrode simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining P type pad and N-type welding disk pattern, deposits described P type pad and N-type pad simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
9. the manufacture method of III light emitting semiconductor device according to claim 1, is characterized in that, described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, then removes photoresistance, make disk, be further
Gold-tinted peels off program defining P type pad and N-type welding disk pattern, deposit described P type pad and N-type pad simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining P molded line electrode and N-type line electrode pattern, deposits described P molded line electrode and N-type line electrode simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
10. the manufacture method of III light emitting semiconductor device according to claim 1, is characterized in that, described gold-tinted peels off program defining P-type electrode and N-type electrode pattern, deposit described P-type electrode and N-type electrode, processing procedure is peeled off in rear utilization, then removes photoresistance, make disk, be further
Gold-tinted peels off program defining P type pad and P molded line electrode pattern, deposit described P type pad and P molded line electrode simultaneously, processing procedure is peeled off in rear utilization, remove photoresistance again, recycling gold-tinted peels off program defining N-type pad and N-type line electrode pattern, deposits described N-type pad and N-type line electrode simultaneously, and processing procedure is peeled off in rear utilization, remove photoresistance again, make disk.
CN201510027675.XA 2015-01-20 2015-01-20 A kind of preparation method of III races light emitting semiconductor device Active CN104576867B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510027675.XA CN104576867B (en) 2015-01-20 2015-01-20 A kind of preparation method of III races light emitting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510027675.XA CN104576867B (en) 2015-01-20 2015-01-20 A kind of preparation method of III races light emitting semiconductor device

Publications (2)

Publication Number Publication Date
CN104576867A true CN104576867A (en) 2015-04-29
CN104576867B CN104576867B (en) 2017-08-29

Family

ID=53092488

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510027675.XA Active CN104576867B (en) 2015-01-20 2015-01-20 A kind of preparation method of III races light emitting semiconductor device

Country Status (1)

Country Link
CN (1) CN104576867B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105932133A (en) * 2016-04-29 2016-09-07 湘能华磊光电股份有限公司 High-brightness LED chip and preparation method thereof
WO2016177333A1 (en) * 2015-05-05 2016-11-10 湘能华磊光电股份有限公司 Manufacturing method for group iii semiconductor light-emitting component flip-chip structure
WO2016177335A1 (en) * 2015-05-05 2016-11-10 湘能华磊光电股份有限公司 Group iii semiconductor light emitting device flip-chip structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110198635A1 (en) * 2007-08-08 2011-08-18 Sang Mook Kim Light Emitting Diode With Metal Piles and Multi-Passivation Layers and Its Manufacturing Method
CN102931324A (en) * 2011-11-25 2013-02-13 俞国宏 LED chip
WO2013051326A1 (en) * 2011-10-05 2013-04-11 シャープ株式会社 Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor light emitting element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110198635A1 (en) * 2007-08-08 2011-08-18 Sang Mook Kim Light Emitting Diode With Metal Piles and Multi-Passivation Layers and Its Manufacturing Method
WO2013051326A1 (en) * 2011-10-05 2013-04-11 シャープ株式会社 Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor light emitting element
CN102931324A (en) * 2011-11-25 2013-02-13 俞国宏 LED chip

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016177333A1 (en) * 2015-05-05 2016-11-10 湘能华磊光电股份有限公司 Manufacturing method for group iii semiconductor light-emitting component flip-chip structure
WO2016177335A1 (en) * 2015-05-05 2016-11-10 湘能华磊光电股份有限公司 Group iii semiconductor light emitting device flip-chip structure
US9893040B2 (en) 2015-05-05 2018-02-13 Xiangneng Hualei Optoelectronic Co., Ltd Flip-chip structure of group III semiconductor light emitting device
US10147849B2 (en) 2015-05-05 2018-12-04 Xiangneng Hualei Optoelectronic Co., Ltd Manufacturing method of flip-chip structure of group III semiconductor light emitting device
CN105932133A (en) * 2016-04-29 2016-09-07 湘能华磊光电股份有限公司 High-brightness LED chip and preparation method thereof
CN105932133B (en) * 2016-04-29 2018-08-14 湘能华磊光电股份有限公司 A kind of high brightness LED chip and preparation method thereof

Also Published As

Publication number Publication date
CN104576867B (en) 2017-08-29

Similar Documents

Publication Publication Date Title
US9893040B2 (en) Flip-chip structure of group III semiconductor light emitting device
CN104538513B (en) A kind of preparation method of III races light emitting semiconductor device
US10147849B2 (en) Manufacturing method of flip-chip structure of group III semiconductor light emitting device
CN104659177A (en) Group III semiconductor luminescent device
US8410505B2 (en) Light-emitting diode having a reflective layer between a transparent insulating layer and an electrode
CN104821351B (en) The preparation method of III light emitting semiconductor device inverted structure
CN104810439A (en) Method for manufacturing III-group semiconductor light-emitting devices
CN104821350A (en) Manufacturing method of inversion structure of III semiconductor light-emitting device
CN104037294B (en) GaN-based light-emitting diode and manufacturing method thereof
CN106784192A (en) A kind of light-emitting diode chip for backlight unit and preparation method thereof
CN104576851A (en) Method for manufacturing group III semiconductor luminescent device
CN104576868A (en) Method for manufacturing group III semiconductor luminescent device
CN104576867A (en) Method for manufacturing group III semiconductor luminescent device
CN104795481B (en) Light emitting diode and preparation method thereof
CN102956784A (en) Light emitting diode structure and manufacturing method thereof
TW201143078A (en) Light emitting diode module with bridging electrode and manufacturing method thereof
CN116978990A (en) LED chip, preparation method thereof and LED chip
CN106848027B (en) The preparation method of the vertical flip LED chips of high reliability
CN116960252A (en) LED chip and preparation method thereof
CN108110107A (en) A kind of production method of LED chip
CN209709009U (en) Light-emitting diode chip for backlight unit
WO2016177334A1 (en) Manufacturing method for group iii semiconductor light emitting device flip-chip structure
CN215377431U (en) Light emitting diode chip structure and light emitting diode
JP3935175B2 (en) Light emitting device and manufacturing method thereof
CN113690349B (en) Anti-fracture light-emitting diode chip and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant