CN110875376B - 外延基板及其制造方法 - Google Patents
外延基板及其制造方法 Download PDFInfo
- Publication number
- CN110875376B CN110875376B CN201910509872.3A CN201910509872A CN110875376B CN 110875376 B CN110875376 B CN 110875376B CN 201910509872 A CN201910509872 A CN 201910509872A CN 110875376 B CN110875376 B CN 110875376B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- silicon
- epitaxial
- silicon carbide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 97
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 48
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 45
- 238000005468 ion implantation Methods 0.000 claims description 34
- 229910052799 carbon Inorganic materials 0.000 claims description 19
- -1 carbon ion Chemical class 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical group [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- 230000003746 surface roughness Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 93
- 230000003071 parasitic effect Effects 0.000 description 8
- 230000010287 polarization Effects 0.000 description 7
- 238000000407 epitaxy Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 230000002269 spontaneous effect Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/48—Ion implantation
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/0635—Carbides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
- C30B31/20—Doping by irradiation with electromagnetic waves or by particle radiation
- C30B31/22—Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B7/00—Single-crystal growth from solutions using solvents which are liquid at normal temperature, e.g. aqueous solutions
- C30B7/005—Epitaxial layer growth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Materials Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mechanical Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Ceramic Engineering (AREA)
- Electromagnetism (AREA)
- Inorganic Chemistry (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
技术领域
本发明涉及一种外延技术,尤其涉及一种外延基板及其制造方法。
背景技术
外延(Epitaxy)是指在晶圆上长出新结晶,以形成半导体层的技术。由于以外延工艺所形成的膜层具有纯度高、厚度控制性佳等优点,因此已经广泛应用于射频元件或功率元件的制造中。
然而,在外延和基板界面常有本身外延材料引发自发极化或者因外延和基板晶格不匹配引发压电极化或外延层原子扩散至基板,而产生外延和基板界面电阻降低(interface loss)的问题。
另外,若是需求的外延基板为硅绝缘体(Silicon-on-Insulator,SOI)基板,则于内埋氧化物层(Buried Oxide,BOX)及基板界面处易形成高导电性电荷反转层或累积层,其会降低基板电阻率且产生寄生功率损失。因此,目前亟需一种能解决上述问题的方案。
发明内容
本发明提供一种外延基板,能解决外延和基板界面电阻降低以及寄生功率损失的问题。
本发明另提供一种外延基板的制造方法,能制作出解决外延和基板界面电阻降低以及寄生功率损失等问题的基板。
在本发明的一实施例中,上述硅基板的第一表面具有单晶结构。
在本发明的一实施例中,上述碳化硅层的厚度介于100埃与4000埃之间。
在本发明的一实施例中,上述硅基板的第一表面的表面粗糙度介于0.1纳米(nm)与0.3纳米之间。
在本发明的一实施例中,上述碳化硅层为单层结构或多层结构。
在本发明的一实施例中,上述多层结构包括第一层与第二层,且第一层位于第二层与第一表面之间。
在本发明的一实施例中,上述第一层与第二层直接接触。
在本发明的一实施例中,上述第一层不直接接触第二层。
在本发明的一实施例中,上述第一层与第二层之间的距离介于100埃与500埃之间。
在本发明的一实施例中,上述第一层的碳离子浓度大于所述第二层的碳离子浓度。
在本发明的一实施例中,上述硅基板包括硅绝缘体(SOI)基板。
本发明的外延基板的制造方法包括提供具有相对的第一表面与第二表面的硅基板,然后对硅基板的第一表面进行离子注入工艺,以于硅基板内注入碳离子,再进行高温退火处理,以使碳离子扩散并于硅基板内形成碳化硅层,其中碳化硅层与第一表面之间的距离介于100埃与500埃之间。
在本发明的另一实施例中,上述离子注入工艺的注入能量介于5KeV与15KeV之间。
在本发明的另一实施例中,上述离子注入工艺中的离子注入剂量介于1×1012cm-2与5×1015cm-2之间。
在本发明的另一实施例中,上述离子注入工艺中的离子注入浓度介于2×1017cm-3与2.7×1021cm-3之间。
在本发明的另一实施例中,上述高温退火处理的温度介于1200度(℃)与1300℃之间。
在本发明的另一实施例中,上述高温退火处理的时间介于5小时与10小时之间。
在本发明的另一实施例中,上述高温退火处理的气氛为氩气、氮气或其组合。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1为依照本发明的第一实施例的一种外延基板的剖面示意图。
图2为制造第一实施例的外延基板的步骤图。
图3为依照本发明的第二实施例的一种外延基板的剖面示意图。
图4为依照本发明的第三实施例的一种外延基板的剖面示意图。
附图标号说明:
10、20、30:外延基板
110:硅基板
110a:第一表面
110b:第二表面
120:碳化硅层
120a:第一层
120b:第二层
200、202、204:步骤
d1、d2:距离
t、t1、t2:厚度
具体实施方式
以下将参考附图来全面地描述本发明的例示性实施例,但本发明还可按照多种不同形式来实施,且不应解释为限于本文所述的实施例。在附图中,为了清楚起见,各区域、部位及层的大小与厚度可不按实际比例示出。为了方便理解,下述说明中相同的元件将以相同的符号标示来说明。
图1为依照本发明的第一实施例的一种外延基板的剖面示意图。图2为制造图1的外延基板的步骤图。
请参考图1及图2,在步骤200中,提供硅基板110。本实施例的硅基板110具有相对的第一表面110a与第二表面110b。硅基板110的材料例如硅、碳化硅或是其他含有硅的材料,但本发明不限于此。在其他实施例中,硅基板110也可以是注入例如碳、氧或氮的硅基板。硅基板110可依后续外延需求选用晶向为(111)较佳,但本发明并不限于此。在另一实施例中,硅基板110可为硅绝缘体(SOI)基板。在本实施例中,硅基板110的第一表面110a具有单晶结构,且作为外延面。若以外延质量佳的观点来看,硅基板110的第一表面110a的表面粗糙度例如介于0.1纳米与0.3纳米之间。
然后,在步骤202中,对硅基板110的第一表面110a进行离子注入工艺,以于硅基板110内注入碳离子。由于碳离子与硅基板110中的硅原子为同族元素,因此注入碳离子的硅基板110仍可以保有高阻质特性。在本实施例中,离子注入工艺的注入能量例如小于15KeV;且以不影响第一表面110a的质量的观点来看,离子注入工艺的注入能量例如介于5KeV与15KeV之间。在本实施例中,离子注入工艺中的离子注入剂量例如介于1×1012cm-2与5×1015cm-2之间;离子注入工艺中的离子注入浓度例如介于2×1017cm-3与2.7×1021cm-3之间。由于碳离子注入硅基板110的能量不高,因此不会影响硅基板110的第一表面110a的结构,进而不会影响之后在第一表面110a的外延质量。
随后,在步骤204中,进行高温退火处理,以使碳离子扩散,并于硅基板110内形成碳化硅层120,至此大致完成外延基板10。在本实施例中,高温退火处理的温度例如介于1200度(℃)与1300℃之间。高温退火处理的时间例如介于5小时与10小时之间。高温退火处理的气氛例如氩气、氮气或其组合,但本发明不限于此。
在步骤204中的高温退火处理的参数可根据需求作调变,且可通过参数的不同来控制碳化硅层120与第一表面110a之间的距离d1在100埃以上,其中较佳的距离介于100埃与500埃之间,更佳的距离介于183埃与499埃之间。举例来说,上述离子注入工艺的注入能量如为5KeV、离子注入剂量如为1×1012cm-2、离子注入浓度如为2×1017cm-3,所得到的距离d1约为183埃。另外,上述离子注入工艺的注入能量如为15KeV、离子注入剂量如为5×1015cm-2、离子注入浓度如为2.7×1021cm-3,所得到的距离d1则约499埃。在本实施例中,碳化硅层120的厚度t例如介于100埃与4000埃之间。
基于上述,通过接近外延面的碳化硅层120,可以改善应用于射频元件或功率元件的外延基板10的绝缘性和散热性,进而增加元件效能。此外,由于碳化硅层120能产生缺陷以捕捉电子,因此能解决在外延面因自发或压电极化而产生的界面电阻降低的问题,也能解决寄生通道造成元件频率耗损的问题。
图3为依照本发明的第二实施例的一种外延基板的剖面示意图。在此必须说明的是,第二实施例沿用图1的实施例的元件符号与部分内容,其中采用相同或近似的元件符号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,下述实施例不再重复赘述。
图3的实施例与图1的实施例的区别的特点在于:碳化硅层120为多层结构。
请参考图3,在本实施例的外延基板20中,碳化硅层120为多层结构,其中多层结构包括第一层120a与第二层120b。第一层120a位于第二层120b与第一表面110a之间。在本实施例中,第一层120a与第二层120b直接接触。在本实施例中,第一层120a的厚度t1与第二层120b的厚度t2分别介于100埃与4000埃之间。第一层120a的厚度t1与第二层120b的厚度t2可以相同或是不相同。第一层120a与第二层120b的碳离子浓度可以相同或是不相同;举例来说,第一层120a的碳离子浓度若是大于第二层120b的碳离子浓度,能加强元件绝缘性和散热性。
虽然图3仅示出碳化硅层120的多层结构包括两层碳化硅层,但本发明不限于此。在其他实施例中,碳化硅层120的多层结构可以包括三层以上的碳化硅层。通过外延基板20包括碳化硅层120,可以改善射频元件或功率元件的绝缘性和散热性,增加元件效能。此外,由于碳化硅层120能产生缺陷以捕捉电子,因此能解决在外延面因自发或压电极化而产生的界面电阻降低的问题,也能解决寄生通道造成元件频率耗损的问题。
在本实施例中,外延基板20的制造方法大致与外延基板10的制造方法相同。通过不同的离子注入工艺的注入能量、离子注入剂量以及离子注入浓度,来形成具有多层结构的碳化硅层120。
图4为依照本发明的第三实施例的一种外延基板的剖面示意图。在此必须说明的是,图4的实施例沿用图3的第二实施例的元件标号与部分内容,其中采用相同或近似的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,下述实施例不再重复赘述。
图4的实施例与图3的实施例的区别的特点在于:第一层120a不直接接触第二层120b。
请参考图4,在本实施例的外延基板30中,第一层120a与第二层120b不直接接触,且第一层120a与第二层120b之间具有距离d2,其中距离d2例如介于100埃与500埃之间。而且,通过控制形成第一层120a的离子注入工艺的注入能量以及形成第二层120b的离子注入工艺的注入能量的大小,可改变第一层120a与第二层120b的位置,并藉此调整第一层120a与第二层120b之间的距离d2。
虽然图4仅示出碳化硅层120的多层结构包括两层碳化硅层,但本发明不限于此。第一层120a与第二层120b的碳离子浓度可以相同或是不相同;举例来说,第一层120a的碳离子浓度若是大于第二层120b的碳离子浓度,能加强元件绝缘性和散热性。在其他实施例中,碳化硅层120的多层结构可以包括三层以上的碳化硅层。通过外延基板30包括碳化硅层120,可以改善射频元件或功率元件的绝缘性和散热性,增加元件效能。此外,由于碳化硅层120能产生缺陷以捕捉电子,因此能解决在外延面因自发或压电极化而产生的界面电阻降低的问题,也能解决寄生通道造成元件频率耗损的问题。
在本实施例中,外延基板30的制造方法大致与外延基板10的制造方法相同。在本实施例中,通过不同的离子注入工艺的注入能量、离子注入剂量以及离子注入浓度,形成具有多层结构的碳化硅层120。
综上所述,本发明通过于硅基板内形成单层或多层的碳化硅层,且碳化硅层与硅基板的第一表面之间的距离介于100埃与500埃之间,可以在改善射频元件或功率元件的绝缘性和散热性的同时,还能够不影响硅基板的外延面质量,以增加元件效能。而且,本发明是将碳离子注入硅基板内,由于碳离子与硅原子为同族元素,所以可使硅基板保有高阻质特性。此外,由于碳化硅层能产生缺陷以捕捉电子,因此能解决在外延面(即硅基板的第一表面)因自发或压电极化而产生的界面电阻降低的问题,也能解决寄生通道造成元件频率耗损的问题。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中的技术人员,在不脱离本发明的精神和范围内,当可作些许的更改与润饰,故本发明的保护范围当视权利要求所界定的为准。
Claims (12)
1.一种外延基板,其特征在于,包括:
硅基板,具有相对的第一表面与第二表面,其中所述第一表面为外延面,其中所述硅基板的所述第一表面具有单晶结构;以及
碳化硅层,位于所述硅基板内,且所述碳化硅层与所述第一表面之间的距离介于100埃与500埃之间,其中所述碳化硅层为多层结构,所述多层结构包括第一层与第二层,所述第一层位于所述第二层与所述第一表面之间,所述第一层不直接接触所述第二层,且所述第一层的碳离子浓度大于所述第二层的碳离子浓度。
2.根据权利要求1所述的外延基板,其中所述碳化硅层的厚度介于100埃与4000埃之间。
3.根据权利要求1所述的外延基板,其中所述硅基板的所述第一表面的表面粗糙度介于0.1纳米与0.3纳米之间。
4.根据权利要求1所述的外延基板,其中所述第一层与所述第二层之间的距离介于100埃与500埃之间。
5.根据权利要求1所述的外延基板,其中所述硅基板包括硅绝缘体基板。
6.一种制造如权利要求1~5中任一所述的外延基板的方法,其特征在于,包括:
提供硅基板,所述硅基板具有相对的第一表面与第二表面;
对所述硅基板的所述第一表面进行离子注入工艺,以于所述硅基板内注入碳离子;以及
进行高温退火处理,以使所述碳离子扩散并于所述硅基板内形成碳化硅层,其中所述碳化硅层与所述第一表面之间的距离介于100埃与500埃之间。
7.根据权利要求6所述的外延基板的制造方法,其中所述离子注入工艺的注入能量介于5KeV与15KeV之间。
8.根据权利要求6所述的外延基板的制造方法,其中所述离子注入工艺中的离子注入剂量介于1′1012cm-2与5′1015cm-2之间。
9.根据权利要求6所述的外延基板的制造方法,其中所述离子注入工艺中的离子注入浓度介于2′1017cm-3与2.7′1021cm-3之间。
10.根据权利要求6所述的外延基板的制造方法,其中所述高温退火处理的温度介于1200℃与1300℃之间。
11.根据权利要求6所述的外延基板的制造方法,其中所述高温退火处理的时间介于5小时与10小时之间。
12.根据权利要求6所述的外延基板的制造方法,其中所述高温退火处理的气氛为氩气、氮气或其组合。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107130825A TWI698912B (zh) | 2018-09-03 | 2018-09-03 | 磊晶基板及其製造方法 |
TW107130825 | 2018-09-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110875376A CN110875376A (zh) | 2020-03-10 |
CN110875376B true CN110875376B (zh) | 2023-05-02 |
Family
ID=69640243
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910509872.3A Active CN110875376B (zh) | 2018-09-03 | 2019-06-13 | 外延基板及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11538681B2 (zh) |
CN (1) | CN110875376B (zh) |
TW (1) | TWI698912B (zh) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201218250A (en) * | 2010-04-08 | 2012-05-01 | Shinetsu Handotai Kk | Silicon epitaxial wafer, method for manufacturing silicon epitaxial wafer, and method for manufacturing semiconductor element or integrated circuit |
CN103489779A (zh) * | 2012-06-12 | 2014-01-01 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
CN104282777A (zh) * | 2013-07-09 | 2015-01-14 | 新日光能源科技股份有限公司 | 具掺杂碳化硅层的结晶硅太阳能电池及其制造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002353434A (ja) * | 2001-05-22 | 2002-12-06 | Sony Corp | 固体撮像装置の製造方法 |
US6784072B2 (en) * | 2002-07-22 | 2004-08-31 | International Business Machines Corporation | Control of buried oxide in SIMOX |
US6831350B1 (en) * | 2003-10-02 | 2004-12-14 | Freescale Semiconductor, Inc. | Semiconductor structure with different lattice constant materials and method for forming the same |
US7247583B2 (en) * | 2004-01-30 | 2007-07-24 | Toshiba Ceramics Co., Ltd. | Manufacturing method for strained silicon wafer |
US7382023B2 (en) * | 2004-04-28 | 2008-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fully depleted SOI multiple threshold voltage application |
TW200803678A (en) * | 2006-06-12 | 2008-01-01 | Toppoly Optoelectronics Corp | Electronic device, display apparatus, flexible circuit board and fabrication method thereof |
EP1901345A1 (en) * | 2006-08-30 | 2008-03-19 | Siltronic AG | Multilayered semiconductor wafer and process for manufacturing the same |
US7867861B2 (en) * | 2007-09-27 | 2011-01-11 | Infineon Technologies Ag | Semiconductor device employing precipitates for increased channel stress |
US20090140351A1 (en) * | 2007-11-30 | 2009-06-04 | Hong-Nien Lin | MOS Devices Having Elevated Source/Drain Regions |
JP2010062219A (ja) | 2008-08-04 | 2010-03-18 | Siltronic Ag | 炭化シリコンの製造方法 |
CN102034906A (zh) | 2009-09-24 | 2011-04-27 | 上海凯世通半导体有限公司 | 采用离子注入在单晶硅衬底上形成碳化硅薄层的方法 |
DE112011102528T5 (de) * | 2010-07-29 | 2013-06-27 | Sumitomo Electric Industries, Ltd. | Siliziumkarbid-Substrat, Halbleitervorrichtung und Verfahren zum Herstellen derselben |
US9853133B2 (en) * | 2014-09-04 | 2017-12-26 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity silicon-on-insulator substrate |
US9647071B2 (en) * | 2015-06-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFET structures and methods of forming the same |
CN106847672A (zh) | 2017-03-03 | 2017-06-13 | 上海新傲科技股份有限公司 | 高击穿电压氮化镓功率材料的外延方法 |
-
2018
- 2018-09-03 TW TW107130825A patent/TWI698912B/zh active
-
2019
- 2019-06-13 CN CN201910509872.3A patent/CN110875376B/zh active Active
- 2019-07-16 US US16/513,657 patent/US11538681B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201218250A (en) * | 2010-04-08 | 2012-05-01 | Shinetsu Handotai Kk | Silicon epitaxial wafer, method for manufacturing silicon epitaxial wafer, and method for manufacturing semiconductor element or integrated circuit |
CN103489779A (zh) * | 2012-06-12 | 2014-01-01 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
CN104282777A (zh) * | 2013-07-09 | 2015-01-14 | 新日光能源科技股份有限公司 | 具掺杂碳化硅层的结晶硅太阳能电池及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
TW202011456A (zh) | 2020-03-16 |
US11538681B2 (en) | 2022-12-27 |
CN110875376A (zh) | 2020-03-10 |
TWI698912B (zh) | 2020-07-11 |
US20200075328A1 (en) | 2020-03-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4427489B2 (ja) | 半導体装置の製造方法 | |
JP4582487B2 (ja) | SiGeオンインシュレータ基板材料 | |
US7501318B2 (en) | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal | |
US7915148B2 (en) | Method of producing a tensioned layer on a substrate | |
TWI740249B (zh) | 用於製作包含其中擴散有氮的超晶格之半導體元件之方法 | |
JP2004014856A (ja) | 半導体基板の製造方法及び半導体装置の製造方法 | |
JP4625793B2 (ja) | 半導体デバイス | |
JP4452132B2 (ja) | シリコンの酸化による欠陥低減 | |
US20080128806A1 (en) | Low defect si:c layer with retrograde carbon profile | |
JP4521327B2 (ja) | 半導体装置の製造方法 | |
US20100032684A1 (en) | ION IMPLANTATION FOR SUPPRESSION OF DEFECTS IN ANNEALED SiGe LAYERS | |
US20090085115A1 (en) | Transistor and in-situ fabrication process | |
US20060057403A1 (en) | Use of thin SOI to inhibit relaxation of SiGe layers | |
JP2014502793A (ja) | グラフェン及びカーボンナノチューブに基づく耐放射線化トランジスタ | |
JP2013187291A (ja) | トンネル電界効果トランジスタの製造方法及びトンネル電界効果トランジスタ | |
CN110875376B (zh) | 外延基板及其制造方法 | |
RU2301476C1 (ru) | Способ изготовления гетероструктуры | |
JP4289864B2 (ja) | 半導体装置及び半導体装置製造方法 | |
US20140127871A1 (en) | METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH A SiGe CHANNEL BY ION IMPLANTATION | |
JP2021170608A (ja) | 半導体素子の製造方法 | |
TW201732867A (zh) | 絕緣層上覆矽基板及其製造方法 | |
JP2009512185A (ja) | 半導体soiデバイス | |
WO2011077605A1 (ja) | 半導体装置及びその製造方法 | |
TW201732927A (zh) | 絕緣層上覆矽基板及其製造方法 | |
JP2008244261A (ja) | Soi基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |