CN110875310B - 高压cmos器件与共享隔离区的集成 - Google Patents

高压cmos器件与共享隔离区的集成 Download PDF

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CN110875310B
CN110875310B CN201910755949.5A CN201910755949A CN110875310B CN 110875310 B CN110875310 B CN 110875310B CN 201910755949 A CN201910755949 A CN 201910755949A CN 110875310 B CN110875310 B CN 110875310B
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维平达斯·帕拉
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

功率器件，包括：具有第一导电类型基片层的半导体基体，以及形成在基片层中的一个或多个横向双扩散金属氧化物半导体(LDMOS)晶体管。将LDMOS晶体管结构集成入高电压阱的隔离区。每一LDMOS晶体管通过由基片层形成的隔离器结构与功率器件基片区相隔离。每一LDMOS晶体管包括至少部分于绝缘厚层上形成的连续场电极，越过一个或多个LDMOS晶体管中的每一个，且与功率器件基片区发生导电接触。

Description

高压CMOS器件与共享隔离区的集成
技术领域
本发明的相关方面关联高电压半导体设备及其制造工艺，特别是关联带共享连续隔离区的含横向双扩散金属氧化物半导体(LDMOS)晶体管的功率器件。
背景技术
横向双扩散金属氧化物半导体(LDMOS)晶体管因其高击穿电压特性和兼容低电压CMOS技术，通用于高电压应用领域(20至1200伏)。通常来说，一个N型LDMOS晶体管包括一个多晶硅栅极、一个形成在P型体区中的N+源极区和一个N+漏极区。一个N漂移区，将N+漏极区与多晶硅栅极下方的体区中形成的通道相分离。众所周知：提高N漂移区的长度即可相应提高LDMOS晶体管的击穿电压。
高电压功率器件通常具有一个或多个LDMOS晶体管，且有必要将LDMOS器件的高电压终端(漏极)相互隔离，以使每一器件都能够独立传导电流。图1A描绘了具有多个LDMOS晶体管105(虚线区)和一个集成其它器件(如驱动器)的高电压阱113的高电压功率器件的俯瞰视图。每个LDMOS晶体管105被集成入一个高电压阱的隔离区。通过隔离器结构，将每一晶体管与功率器件基片区116和高电压阱113的井壁相隔离。为了减小电场拥堵，多个浮动导电环连续围绕功率器件高电压区且越过绝缘体厚层顶部，并穿过隔离器结构。
图1B是一剖面图，显示了作为高电压N通道横向DMOS(LDMOS)提供的现有LDMOS器件100。这一类型的器件可以形成在N型外延层、P型外延层或者P型基片中。N通道LDMOS器件100要么形成在外延层中，要么形成在P型基片112中，它包括N-深阱区107中的P阱体区114，设置于P阱体区114中的N+源极区109和设置于N-深阱区107中的深漏极区122顶部的N+漏极接触拾取区。P+体拾取区108还形成在横向邻近源极区109的P阱体区114顶上。绝缘体厚层110形成在部分深阱区107顶上，紧靠着漏极接触拾取区111和设置于P阱体区114顶部的绝缘栅极104旁边。绝缘栅极104延伸部分重叠绝缘体厚层110之上形成场电极。深阱区107至少从源极区109重叠部分延伸通过绝缘体厚层110重叠部分到深漏极区122重叠部分。P型降低表面电场(RESURF)区115形成在深阱区中。一薄层栅极氧化物(图中未显示)提供绝缘栅极104与基片112的电绝缘。对绝缘栅极104施加适当的电压时，有源通道126形成在绝缘栅极104底下的P阱体区中，从源极区109延伸至P阱体区114和深阱区107之间的P-N结。隔离器结构包括隔离绝缘体103位于隔离体结构127之上，后者将高电压LDMOS晶体管105与器件其余部分相分离。轻掺杂基片112和N阱107之间的接面形成基本的隔离体结构127。另外还显示了源极电极119、栅极电极117、漏极电极118和功率器件基片电极120。功率器件基片电极120通过重掺杂基片拾取区101连接到基片区116和底下的轻掺杂基片112。再转向图1A，多个LDMOS晶体管105中的每一晶体管具有分离的绝缘栅极104，后者不接续于功率器件的场电极102。换言之，LDMOS晶体管105的绝缘栅极104中断了场电极102。
图1C显示功率器件中LDMOS晶体管105之间隔离器结构的剖面视图。如图所示，绝缘体厚层110延伸至几乎隔离器结构的整个长度，并将LDMOS晶体管分离出重掺杂基片拾取区101和基片区116底下的轻掺杂基片区112。浮动导电环106坐落在绝缘体厚层110顶上。场电极102不延伸至该区域和绝缘体厚层110。结果，半导体在高电压运行期间暴露于感生电荷和/或场拥堵并易受其影响。
由于场拥堵和热载子注入，该现有技术器件设计易受故障模式的影响。此外，出于栅极区104和浮动导电环的设计考虑，金属引线因电荷积聚而无法越过隔离结构。
本发明示例的发生在本上下文场景之内。
发明内容
本发明涉及一个功率器件，包括：a)具有第一导电类型基片层的半导体基体；b)形成在基片层中并集成于高电压阱隔离区的一个或多个横向双扩散金属氧化物半导体(LDMOS)晶体管，其中的每一LDMOS晶体管通过基片层形成的隔离器结构与一功率器件基片区相隔离，且其中的每一LDMOS晶体管包括：在基片层中形成的与第一导电类型相反的第二导电类型深阱区，深阱区中形成的源极区、体区和漏极接触拾取区，其中的体区为第一导电类型，源极区为第二导电类型，且漏极接触拾取区为第二导电类型；形成在体区，横向邻近源极区的体拾取区，其中的体拾取区为第一导电类型，但其掺杂要重于体区，形成在有源通道区顶上的绝缘栅极层，其中的有源通道位于源极区和结(体区与深阱区之间)之间的体区中，形成在体区和漏极接触拾取区之间基体顶上的绝缘厚层；c)至少部分于绝缘厚层上形成的连续场电极，越过一个或多个LDMOS晶体管中的每一个，且与功率器件基片区发生导电接触；以及d)形成在绝缘厚层顶上的多个电气导电浮动环，其中的多个电气导电浮动环连续越过隔离器结构和功率器件基片区。
其中，还包括形成在深阱区，且与功率器件基片区发生导电接触的第一导电类型守护阱区。
其中的守护阱区形成在通道区和漏极接触拾取区之间。
其中，还包括形成在守护阱区顶上的守护拾取区，与功率器件基片发生导电接触，守护拾取区第一导电类型的掺杂要重于守护阱区。
其中场电极与守护阱区发生接触。
其中，还包括第一导电类型的RESURF区，形成在绝缘体厚层底下,在体区和漏极接触拾取区之间。
其中的RESURF区在守护阱区和漏极接触拾取区之间。
其中，还包括第二导电类型深漏极区形成在漏极接触拾取区底下。
其中的绝缘栅极层在场电极对面的体区上。
其中的体拾取区较之源极区，更接近场电极。
其中的体区延伸到场电极下方形成守护阱。
附图说明
在阅读以下详细说明和引用随附图纸时，本发明的其他对象和优点得到清晰显现，其中包括：
图1A是一俯瞰示意图，描绘了拥有集成于高电压阱隔离区中一个或多个传统型N通道LDMOS晶体管的功率器件部分。
图1B是一剖面示意图，图解说明了沿图1A B-B线，集成于高电压阱隔离区的功率器件中的传统型N通道LDMOS晶体管。
图1C是一剖面示意图，图解说明了沿图1A C-C线，功率器件中的传统型隔离器结构，该器件具有集成于高电压阱隔离区的一个或多个N通道LDMOS晶体管。
图2A是一俯瞰示意图，描绘了按照本发明的相关方面，带共享连续隔离区和守护区，含有一个或多个N通道LDMOS晶体管的功率器件部分；该隔离区和守护区集成于高电压阱的隔离区。
图2B是一剖面示意图，图解说明了按照本发明的相关方面，沿图2AB-B线，带共享连续隔离区和守护区的N通道LDMOS晶体管；该隔离区和守护区集成于高电压阱的隔离区。
图2C是一剖面示意图，图解说明了按照本发明的相关方面，沿图2AC-C线，带共享连续隔离区和守护区，含有一个或多个N通道LDMOS晶体管的功率器件中的传统型隔离器结构。
图3A是一俯瞰示意图，描绘了按照本发明的相关方面，带共享连续隔离区和守护区，含有一个或多个N通道LDMOS晶体管的功率器件部分。
图3B是一剖面示意图，图解说明了按照本发明的相关方面，沿图3A B-B线，带共享连续隔离区和身体接触守护区的N通道LDMOS晶体管。
图3C是一剖面示意图，图解说明了按照本发明的相关方面，沿图3A C-C线，带共享连续隔离区和身体接触守护区，含有一个或多个N通道LDMOS晶体管的功率器件中的传统型隔离器结构。
具体实施方式
在以下详细说明中，对随附图纸加以引用，从而形成本文件的一部分；通过图解说明，于其中显示了实际操作本发明方法时的具体示例。在此方面，就说明图表的定向，使用了方向术语，如“顶部”、“底部”、“前面”、“背面”、“前”、“后”等。由于本发明的示例部件可以在数个不同定向上定位，可以应用方向术语进行图解说明，且无限制作用。应当了解：可以利用其他示例，可以在不离开本发明范围的情况下作出结构或逻辑变更，包括处理步骤顺序的变更。因而以下详细说明没有作出限制的意思，且本发明的范围由附录要求定义。
器件
现有技术功率器件中的不连续场电极创造出可能发生场拥堵和载流注入的区域。具体地说，隔离区中的暴露厚绝缘体可致使场电极边缘和栅极上产生场拥堵和电荷注入。按照本发明的相关方面，可以通过从场电极处分离功率器件中每一LDMOS晶体管的绝缘栅极，同时在功率器件高电压区域周围生成连续场电极，来降低LDMOS器件中的场拥堵和载流注入。
图2A图解说明了经改进功率器件的示例，其中的LDMOS器件按照本发明的相关方面集成入高电压阱的隔离区。该功率器件中的场电极202与LDMOS晶体管的绝缘栅极201相分离。场电极202在LDMOS晶体管上连续，并接入功率器件的重掺杂基片拾取区101,和功率器件基片电极120一样通过重掺杂基片拾取区101连接到和基片区116和底下的轻掺杂基片112。这样的连续场电极202降低了场拥堵和热载子注入。与功率器件基片拾取区101导电接触的守护拾取区204可进一步降低某些示例中场拥堵和热载子注入的发生。
图2B是一示意图，图解说明了按照本发明的某一方面，将N通道LDMOS器件200集成入高电压阱113的隔离区的可能示例。形成在P型基片112中的N通道LDMOS器件200包括多个LDMOS晶体管,每个LDMOS晶体管包括设置于P阱体区210中的N+源极区208，以及深阱区205中设置于可选深漏极区122顶部的N+漏极接触拾取区111。另外还在邻近源极区208的P阱体区210顶部形成P+体拾取区207。就在漏极接触拾取区111旁边的深阱区205的顶部形成了绝缘体厚层211。在P阱体区210和深阱区205顶部设置绝缘栅极201，且该绝缘栅极从源极区208重叠部分延伸至守护阱区214重叠部分终止。可通过一薄层栅极氧化物(图中未显示)，使栅极201与基体组合230电绝缘。在栅极201上施加适当电压时，通道区226形成在栅极201底下的体区中，且从源极区208延伸至P阱体区210和深阱区205之间的P-N结。守护阱区214形成在深阱区205上部,位于在绝缘体厚层211下的RESURF区215和深阱区205中的体区210之间，并与体区分离。守护阱区可以是P导电类型的轻掺杂。在本实例中，深阱区205会是轻掺杂N区。场电极202部分形成在守护阱区214上部。连续的场电极202与守护阱区214部分重叠，并与这些区域发生导电接触。在某些示例中，场电极通过诸如金属引线触点或者非绝缘区域与基片拾取区101的接触等手段，与基片区电极120,220发生导电接触。可以用诸如多晶硅或金属之类的导电材料构建连续场电极202。如上所述，连续场电极202可以连续延伸到绝缘体厚层211和绝缘体厚层211底下的RESURF区215的顶上。绝缘栅极层201的一部分也可与守护阱区214重叠。显然，栅极电极217与绝缘栅极产生导电接触。
图2C显示按照本发明相关方面的经改进功率器件LDMOS晶体管之间隔离器区的剖面侧视图。与现有技术器件形成对比，守护阱区214扩展形成在深阱区205以外的基片112中,并延伸充满整个隔离器区不被绝缘体厚层211覆盖的长度。场电极202在LDMOS晶体管区外的功率器件基片区116处的厚绝缘体上，在隔离器结构上和LDMOS晶体管上保持连续。场电极202和守护阱区214与功率器件基片区电极120,220产生导电接触。在隔离器结构中添加连续场电极202和守护阱区214减少了可能发生场拥堵和载流子注入的绝缘体厚层211之无保护边缘。图2A-C中所示LDMOS器件中的其他结构与图1A-C中所示器件保持类似。
在本发明的替代示例中，可以按图3A-C中描绘的，将体拾取区307和阱体区314用作守护区，以进一步节省空间。在该示例中，体拾取区307和源极区308的位置进行了切换，致使体拾取区307靠近连续场电极302。绝缘栅极层位于场电极302对面的阱体区314上。现在来看图3B，绝缘栅极301重叠一部分隔离绝缘体306、一部分深阱区305、一部分阱体区314和一部分源极区308。这样，当适当的电压施加于栅极时，有源通道326就会形成在绝缘栅极301下方的阱体区，在源极区308和绝缘体厚层310对面的阱体区一侧的隔离器结构之间。该示例中的绝缘体厚层310紧邻阱体区314，且可越过阱体区一部分顶部。类似地，RESURF区315位于体区314旁边，绝缘体厚层310底下。连续场电极302的位置从体拾取区307的边沿部分,越过阱体区314延伸到绝缘体厚层310上。如图3B和3C所示，场电极302与功率器件基片区电极320,120发生导电接触。源极电极317与源极区308和体拾取区307发生导电接触。同样地，栅极电极319转移至场电极302对面的阱体区314，以匹配栅极301。
图3C按照本发明的相关方面，显示功率器件LDMOS晶体管之间隔离器区的横截面。本示例中的绝缘体厚层310贯穿从高端驱动器的高压阱113的井壁到功率器件基片区116的边沿之间的LDMOS晶体管全长。连续场电极302越过隔离器区中的绝缘体厚层310顶部，与LDMOS晶体管中的场电极相连，并延伸到基片区。在举例来说而不是限制的情况下，连续场电极通过物理接触或者将场电极接入功率器件基片区的金属引线(例如：通过金属线)，与基片区电极320产生导电接触。加入连续场电极起到这样的作用：减少致使发生场拥堵和载流子注入的边缘。
制造
可以应用制造传统型LDMOS的传统型方法(带有一些附加步骤)，制造图2A-C和3A-C中显示的功率器件。
在传统过程中，通常会通过硅P-基片112形成有N通道LDMOS，在基片上可以有N型或者P型外延层或者没有外延层的基体组合。
N型注入形成深阱区205。N型注入形成深阱区之后，在基体组合230表面形成绝缘体厚(例如：氧化物)层211。氧化物厚层在守护阱区214旁边形成，并延伸至漏极区或者(可选)深漏极区将随后形成的位置。可应用硅(LOCOS)工艺的局部氧化，形成氧化物厚层211。在替代示例中，也可应用CVD进行回蚀和填沟。随后发生的P型注入在深阱区205上部形成阱体区210。此时，可以选择在深阱区205上部形成轻掺杂的深漏极区122。按照如图2A-C所示示例，在形成绝缘体厚层211之后，于深阱区205的上部形成P型守护阱区214；且在守护阱区214的上部形成重掺杂P型守护拾取区204。守护拾取区204的掺杂重于守护阱区214的掺杂。也可在邻近守护阱区处形成P型RESURF区215。
下一步，可在基体组合230表面上,在一层栅极氧化物薄层顶上，形成栅极201。按照如图2A-B所示示例,可以通过导电材料(如多晶硅或铝、铜之类的金属)沉积和造型，在体区210的一部分和栅极区214的一部分之上，形成栅极201。可以通过与栅极201相同的沉积和造型过程，形成位于绝缘体厚层211边缘之上，与守护阱214区部分重叠的连续多晶硅场电极202。场电极可以与守护区发生导电接触。在举例来说而不是限制的情况下，形成栅极201和场电极202的导电材料可以通过物理气相沉积法(PVD)发生沉积。导电材料可以无掩膜沉积并进行图案化蚀刻，以同时形成栅极电极201和场电极202。如图3A-B中所示示例，绝缘多晶硅栅极301形成在隔离绝缘体306和阱体区314顶上。可以通过在基体表面形成氧化物层，然后在氧化物层顶上形成栅极，来绝缘栅极201；还可在栅极顶上形成第二层氧化物，使之与器件上放置的任何其他导电层相隔离。连续场电极302可在绝缘体厚层310的一部分上生长，并与体区314的一部分相重叠。场电极302与功率器件的基片区发生导电接触。在图2A-C和3A-C的两项示例中，场电极202和302分别连续通过隔离器区并围绕功率器件的高电压区。此外，可以在绝缘体厚层211上，由多晶硅形成导电的浮动环106。导电的浮动环106也连续围绕功率器件的高电压区。
可以在P阱体区210表面中邻近P+体拾取区207的区域中形成掺杂有高浓度N-型掺杂剂的源极区208，例如：经由掩膜注入或者无掩膜注入。在深阱区205表面中形成也掺杂有高浓度N-型掺杂剂的漏极接触拾取区111。结果，源极区208和漏极接触拾取区111形成在厚绝缘体211的对面，并相互隔离。应当注意到，深阱区205、源极区208、阱体区210、体拾取区207和漏极接触拾取区111的位置在基片层内部生成了隔离体结构227，将LDMOS晶体管与功率器件的基片区相隔离。隔离器绝缘体203可以沉积在隔离体结构227处基体组合230的表面上,形成隔离器结构。隔离器绝缘体203可以是任何电阻材料，例如：生长于基体表面上的氧化物层。既然已就图2A、图2B和图2C解释了这些区域的形成，应当能够理解：图3A、图3B和图3C中讨论的示例中这些区域的产生过程实质相同，仅仅是在基片内区域的位置不同。
图2A-B中描绘的示例中源极区208的形成设定了源极区208、体拾取区207和阱体区210，并进一步通过绝缘厚层211容纳附加守护结构。在图3A-B中描绘的示例中，源极区308和体拾取307的位置相对于绝缘体厚层310发生切换。如所示，源极区308邻近隔离绝缘体306，而不是绝缘体厚层310。栅极、体、源极和漏极电极因而形成，构成整个器件。此外，在某些示例中，也可形成基片电极。最后，可在器件表面形成金属互连。
应当注意到：以上技艺的描述是就N型LDMOS器件而言的，但可以应用于N型和P型LDMOS两者。
以上是关于本发明首选示例的完整描述，但同时也可以对其采用替代、修改和等效物。因此，本发明的应用范围不应当参照上述说明加以确定，而应参照连同其完整等效物范围在内的附加要求一起加以确定。任何特性，无论是否为首选，都可与无论首选与否的任何其他特性相组合。在以下要求中，除另外明文规定之外，不定冠词“A”或“An”指的是冠词后面一项或多项事物的数量。所附要求不应被解释为包括手段加功能限制，除非此类限制在给定要求中应用词组“手段方式”加以明确叙述。

Claims (11)

1.一个功率器件，包括：
a)具有第一导电类型基片层的半导体基体；
b)形成在基片层中并集成于高电压阱隔离区的多个横向双扩散金属氧化物半导体(LDMOS)晶体管，其中的每一LDMOS晶体管通过基片层形成的隔离器结构与一功率器件基片区相隔离，且其中的每一LDMOS晶体管包括：
在基片层中形成的与第一导电类型相反的第二导电类型深阱区，
深阱区中形成的源极区、体区和漏极接触拾取区，其中的体区为第一导电类型，源极区为第二导电类型，且漏极接触拾取区为第二导电类型；
形成在体区，横向邻近源极区的体拾取区，其中的体拾取区为第一导电类型，但其掺杂要重于体区，
形成在有源通道顶上的绝缘栅极层，其中的有源通道位于体区中，在源极区和体区与深阱区之间的结之间，
形成在体区和漏极接触拾取区之间基体顶上的绝缘厚层；
c)至少部分于绝缘厚层上形成的连续场电极，越过多个LDMOS晶体管中的每一个，且与功率器件基片区发生导电接触；以及
d)形成在绝缘厚层顶上的多个电气导电浮动环，其中的多个电气导电浮动环连续越过隔离器结构和功率器件基片区。
2.权利要求1所述之器件，还包括形成在深阱区，且与功率器件基片区发生导电接触的第一导电类型守护阱区。
3.权利要求2所述之器件，其中的守护阱区形成在有源通道区和漏极接触拾取区之间。
4.权利要求2所述之器件，还包括形成在守护阱区顶上的守护拾取区，与功率器件基片发生导电接触，守护拾取区第一导电类型的掺杂要重于守护阱区。
5.权利要求2所述之器件，其中场电极与守护阱区发生接触。
6.权利要求1所述之器件，还包括第一导电类型的RESURF区，形成在绝缘体厚层底下,在体区和漏极接触拾取区之间。
7.权利要求6所述之器件，其中的RESURF区在守护阱区和漏极接触拾取区之间。
8.权利要求1所述之器件，还包括第二导电类型深漏极区形成在漏极接触拾取区底下。
9.权利要求1所述之器件，其中的绝缘栅极层在场电极对面的体区上。
10.权利要求9所述之器件，其中的体拾取区较之源极区，更接近场电极。
11.权利要求10所述之器件，其中的体区延伸到场电极下方形成守护阱。
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