CN110854197B - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN110854197B CN110854197B CN201811621023.9A CN201811621023A CN110854197B CN 110854197 B CN110854197 B CN 110854197B CN 201811621023 A CN201811621023 A CN 201811621023A CN 110854197 B CN110854197 B CN 110854197B
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- CN
- China
- Prior art keywords
- semiconductor layer
- semiconductor
- layer
- type
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/051—Forming charge compensation regions, e.g. superjunctions
- H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/156—Drain regions of DMOS transistors
- H10D62/157—Impurity concentrations or distributions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018154251A JP7029364B2 (ja) | 2018-08-20 | 2018-08-20 | 半導体装置 |
| JP2018-154251 | 2018-08-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110854197A CN110854197A (zh) | 2020-02-28 |
| CN110854197B true CN110854197B (zh) | 2024-01-02 |
Family
ID=69523027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811621023.9A Active CN110854197B (zh) | 2018-08-20 | 2018-12-28 | 半导体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US10720523B2 (https=) |
| JP (1) | JP7029364B2 (https=) |
| CN (1) | CN110854197B (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7337469B1 (ja) * | 2022-03-03 | 2023-09-04 | 三菱電機株式会社 | 半導体装置および電力変換装置 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007149736A (ja) * | 2005-11-24 | 2007-06-14 | Toshiba Corp | 半導体装置 |
| CN103681882A (zh) * | 2012-09-12 | 2014-03-26 | 株式会社东芝 | 电力半导体装置 |
| CN104882474A (zh) * | 2014-02-27 | 2015-09-02 | 株式会社东芝 | 半导体装置 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0817274B1 (en) * | 1996-07-05 | 2004-02-11 | STMicroelectronics S.r.l. | Asymmetric MOS technology power device |
| US20030209741A1 (en) | 2002-04-26 | 2003-11-13 | Wataru Saitoh | Insulated gate semiconductor device |
| US6700156B2 (en) | 2002-04-26 | 2004-03-02 | Kabushiki Kaisha Toshiba | Insulated gate semiconductor device |
| JP3935042B2 (ja) | 2002-04-26 | 2007-06-20 | 株式会社東芝 | 絶縁ゲート型半導体装置 |
| JP5183857B2 (ja) | 2004-03-29 | 2013-04-17 | 古河電気工業株式会社 | 電界効果トランジスタおよび製造方法 |
| JP5407182B2 (ja) * | 2008-05-29 | 2014-02-05 | 富士電機株式会社 | 高耐圧縦型mosfet |
| JP2010103337A (ja) | 2008-10-24 | 2010-05-06 | Toshiba Corp | 電力用半導体装置 |
| JP2011003609A (ja) * | 2009-06-16 | 2011-01-06 | Toshiba Corp | 電力用半導体素子 |
| JP5136674B2 (ja) | 2010-07-12 | 2013-02-06 | 株式会社デンソー | 半導体装置およびその製造方法 |
| JP7029710B2 (ja) * | 2017-06-16 | 2022-03-04 | 富士電機株式会社 | 半導体装置 |
-
2018
- 2018-08-20 JP JP2018154251A patent/JP7029364B2/ja active Active
- 2018-12-28 CN CN201811621023.9A patent/CN110854197B/zh active Active
-
2019
- 2019-01-07 US US16/241,057 patent/US10720523B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007149736A (ja) * | 2005-11-24 | 2007-06-14 | Toshiba Corp | 半導体装置 |
| CN103681882A (zh) * | 2012-09-12 | 2014-03-26 | 株式会社东芝 | 电力半导体装置 |
| CN104882474A (zh) * | 2014-02-27 | 2015-09-02 | 株式会社东芝 | 半导体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US10720523B2 (en) | 2020-07-21 |
| CN110854197A (zh) | 2020-02-28 |
| US20200058786A1 (en) | 2020-02-20 |
| JP2020031088A (ja) | 2020-02-27 |
| JP7029364B2 (ja) | 2022-03-03 |
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| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |