CN110838522A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110838522A
CN110838522A CN201910022134.6A CN201910022134A CN110838522A CN 110838522 A CN110838522 A CN 110838522A CN 201910022134 A CN201910022134 A CN 201910022134A CN 110838522 A CN110838522 A CN 110838522A
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semiconductor layer
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layer
semiconductor
semiconductor device
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CN110838522B (zh
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下条亮平
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Abstract

半导体装置具备：第1导电型第1半导体层；第2导电型第2半导体层，选择性地设置在第1半导体层上；第1导电型第3半导体层，选择性地设置在第2半导体层上；第1绝缘膜，覆盖第1半导体层与第3半导体层之间的一部分第2半导体层；控制电极，隔着第1绝缘膜与一部分第2半导体层相对；第2导电型第4半导体层，设置在第1半导体层的下表面侧；第1导电型第5半导体层，在沿第1半导体层下表面的第1方向上与第4半导体层并列；第6半导体层，设置在第1半导体层与第5半导体层之间，与第4半导体层相连，连接部分，为在第1半导体层与第5半导体层之间不存在第6半导体层的部分。第6半导体层与第4半导体层相比第2导电型杂质的有效浓度低。

Description

半导体装置
本申请主张以日本专利申请第2018-152946号(申请日：2018年8月15日)及日本专利申请第2018-215265号(2018年11月16日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及半导体装置。
背景技术
控制高耐压大电流的电力变换器使用IGBT(Insulated Gate BipolarTransistor：绝缘栅型双极型晶体管)等开关元件及二极管元件而构成。例如，通过使用将开关元件及二极管元件单芯片化的半导体装置，能够简化电力变换器的结构，实现小型化。但是，在这样的半导体装置中，要求降低开关损耗及导通损耗。
发明内容
实施方式提供将IGBT及二极管一体化而成的低损耗的半导体装置。
实施方式的半导体装置具备：第1导电型的第1半导体层；第2导电型的第2半导体层，选择性地设置在所述第1半导体层上；第1导电型的第3半导体层，选择性地设置在所述第2半导体层上；第1绝缘膜，覆盖位于所述第1半导体层与所述第3半导体层之间的所述第2半导体层的一部分；控制电极，隔着所述第1绝缘膜而与所述第2半导体层的一部分相对；第2导电型的第4半导体层，设置在所述第1半导体层的下表面侧；第1导电型的第5半导体层，在沿着所述第1半导体层的下表面的第1方向上与所述第4半导体层并列配置；以及第6半导体层，设置在所述第1半导体层与所述第5半导体层之间，与所述第4半导体层相连。所述第6半导体层具有从第2导电型杂质的浓度减去第1导电型杂质浓度而得的第2导电型杂质的补偿浓度，所述第6半导体层中的所述第2导电型杂质的补偿浓度比所述第4半导体层中的第2导电型杂质的补偿浓度低。所述半导体装置包含在所述第1半导体层与所述第5半导体层之间不存在所述第6半导体层的部分。
附图说明
图1是表示实施方式的半导体装置的示意剖视图。
图2A～图2C是表示实施方式的半导体装置的示意图。
图3A及图3B是表示实施方式的半导体装置的特性的示意图。
图4A～图4D是表示实施方式的半导体装置的制造过程的示意剖视图。
图5A及图5B是表示实施方式的第1变形例的半导体装置的示意图。
图6是表示实施方式的第2变形例的半导体装置的示意剖视图。
图7是表示实施方式的第3变形例的半导体装置的示意剖视图。
具体实施方式
以下，参照附图对实施方式进行说明。对于附图中的相同部分赋予相同符号而适当省略其详细说明，对不同部分进行说明。另外，附图是示意性或概念性的图，各部分的厚度与宽度的关系、部分间的大小的比率等不一定与实际情况相同。此外，即使是表示相同部分的情况，有时也通过附图将各自的尺寸、比率不同地表示。
进而，利用各图中表示的X轴、Y轴及Z轴说明各部分的配置及结构。X轴、Y轴、Z轴相互正交，分别表示X方向、Y方向、Z方向。此外，有时将Z方向设为上方、将其相反方向设为下方进行说明。
图1是表示实施方式的半导体装置1的示意剖视图。半导体装置1例如是将IGBT与二极管一体化而成的功率半导体装置。
如图1所示，半导体装置1具备N型基极层10、P型基极层20及N型发射极层30。P型基极层20选择性地设置在N型基极层10之上。N型发射极层30选择性地设置在P型基极层20之上。N型发射极层30包含与N型基极层10的N型杂质相比更高浓度的N型杂质。
半导体装置1还具备栅极电极40及栅极绝缘膜45。栅极电极40例如设置在栅极沟槽47的内部，该栅极沟槽47具有从N型发射极层30的上表面到达N型基极层10的深度。栅极绝缘膜45在栅极沟槽47的内部，使栅极电极40与N型基极层10、P型基极层20及N型发射极层30电绝缘。栅极电极40例如以隔着栅极绝缘膜45而与N型基极层10、P型基极层20及N型发射极层30相对的方式形成。
半导体装置1还具备P型集电极层50及N型缓冲层60。P型集电极层50设置在N型基极层10的下表面侧。P型集电极层50例如包含与p型基极层20的p型杂质相比更高浓度的p型杂质。N型缓冲层60设置在N型基极层10与P型集电极层50之间。N型缓冲层60包含与N型基极层10的N型杂质相比更高浓度的N型杂质。
半导体装置1还具备N型阴极层70及P型势垒层80。N型阴极层70设置在N型缓冲层60的下表面侧，在沿着N型缓冲层60的下表面的方向(例如X方向)上与P型集电极层50并列配置。N型阴极层70例如包含与N型缓冲层60的N型杂质相比更高浓度的N型杂质。P型势垒层80设置在N型缓冲层60与N型阴极层70之间。P型势垒层80包含有效浓度比P型集电极层50的P型杂质低的P型杂质。另外，P型势垒层80以与P型集电极层50相连的方式设置。
在此，将包含N型杂质及P型杂质这两者且P型杂质浓度高于N型杂质浓度的半导体层中的P型杂质的“有效浓度”定义为从P型杂质浓度减去N型杂质浓度而得的补偿浓度。
半导体装置1在N型缓冲层60的下表面侧包括在N型缓冲层60与N型阴极层70之间不存在P型势垒层80的部分(以下，称为N型连接部75)。N型阴极层70经由N型连接部75而与N型缓冲层60连接。
半导体装置1还包括发射极电极90及集电极电极95。
发射极电极90设置在N型发射极层30之上及栅极电极40的上方。发射极电极90与N型发射极层30电连接，通过层间绝缘膜46而与栅极电极40电绝缘。
发射极电极90与p型接触层35电连接。另外，发射极电极90经由P型接触层35而与P型基极层20电连接。P型接触层35例如在X方向上设置在N型发射极层30之间，与P型基极层20及发射极电极90双方相接触。P型接触层35包含与P型基极层20的P型杂质相比更高浓度的P型杂质。
集电极电极95设置在P型集电极层50及N型阴极层70的下表面侧。集电极电极95与P型集电极层50及N型阴极层70双方相接触。集电极电极95与p型集电极层50及N型阴极层70双方电连接。
半导体装置1例如在对发射极电极90施加了负电位、对集电极电极95施加了正电位的情况下，作为IGBT进行动作。另一方面，在对发射极电极90施加了正电位、对集电极电极95施加了负电位的情况下，半导体装置1作为二极管动作。
图2A～图2C是表示实施方式的半导体装置1的示意图。图2A是表示半导体装置1的另一剖视图。图2B是表示沿着图2A中所示的A-A线的截面的示意图。图2C是表示沿着图2A中所示的B-B线的截面的示意图。
如图2A所示，在N型基极层10之上设置有MOS构造MS。MOS构造MS包括P型基极层20、N型发射极层30、栅极电极40及栅极绝缘膜45。
如图2B所示，P型集电极层50及N型阴极层70例如在Y方向上延伸且在X方向上交替地配置。P型集电极层50的配置周期WP例如比栅极电极40的配置周期WG(参照图2A)宽。
如图2C所示，P型势垒层80在Y方向上延伸，配置在P型集电极层50之间。N型连接部75设置在P型势垒层80之间，例如沿Y方向延伸。N型连接部75设置在与P型集电极层50分离的位置。
N型连接部75的X方向的宽度WN例如为P型集电极层50的配置周期WP的5％以下，优选为0.5％以上且1％以下。若N型连接部75的宽度WN变宽，则电子容易从N型缓冲层60经由N型连接部75向N型阴极层70流动。因此，从P型集电极层50向N型基极层10的空穴注入被抑制，IGBT动作被阻碍。结果，半导体装置1的导通电压变大，导通损耗增加。另外，若N型连接部75的宽度变窄，则在后述的二极管动作中，正向电流的骤回变大，导通损耗变大。
图3A及图3B是表示实施方式的半导体装置1的特性的曲线图及示意图。图3A是表示二极管动作时的集电极·发射极间的电压VCE与正向电流ICE的关系的曲线图。图3B是表示从N型阴极层70经由N型缓冲层60注入到N型基极层10的电子电流Ie1及Ie2的示意图。
半导体装置1例如在对发射极电极90施加了正电位、对集电极电极95施加了负电位的情况下，作为二极管进行动作。此时，N型基极层10与P型基极层20之间的PN结正偏，在发射极电极90与集电极电极95之间流动正向电流ICE。
图3A中所示的电流特性IF1、IF2及IF3表示使P型势垒层80的Z方向的厚度TP变化时的正向电流ICE。若使P型势垒层80的厚度TP变厚，则正向电流ICE从电流特性IF1向IF3变化。即，电流值的骤回(snap back)变大。
例如，在正向电流ICE的电平低的情况下，经由N型连接部75流动的电子电流Ie1从N型阴极层70向N型基极层10注入。而且，随着集电极·发射极间的电压VCE变高，N型阴极层70与P型势垒层80之间的势垒变低，电子电流Ie2开始流动。此时，集电极·发射极间的电压VCE开始降低，产生电流值的骤回。因此，骤回的大小(VCE的峰值)依赖于P型势垒层80的厚度TP。
例如，若骤回增大，则二极管导通时的导通损耗变大。因此，优选通过适当地设定P型势垒层80的厚度TP来抑制骤回。由此，能够降低导通损耗。P型势垒层80的厚度TP例如为0.5μm以下，优选为0.2μm以下。
接着，参照图4A～图4D，对半导体装置1的制造方法进行说明。
图4A～图4D是依次表示实施方式的半导体装置1的制造过程的示意剖视图。
如图4A所示，在半导体晶片SB的表面侧形成MOS构造MS及发射极电极90之后，通过对背面侧进行研削或研磨来将半导体晶片SB加工成规定的厚度。
半导体晶片SB例如是N型硅晶片，具有电阻率30～1000Ωcm。半导体晶片SB包含与N型基极层10相同浓度的N型杂质。P型基极层20、N型发射极层30、P型接触层35例如通过对半导体晶片SB进行P型杂质及N型杂质的离子注入而形成。
栅极电极40例如是导电性的多晶硅，栅极绝缘膜45例如是硅氧化膜或硅氮化膜。发射极电极90例如是包含铝的金属层。
如图4B所示，在半导体晶片SB的背面进行N型杂质例如磷(P)的离子注入，形成注入层IR1。N型杂质例如在注入能量200～2000keV、剂量1×1012～1×1014cm-2的条件下被注入。
如图4C所示，在半导体晶片SB的背面选择性地进行P型杂质例如硼(B)的离子注入，形成注入层IR2。在半导体晶片SB的背面上设置有注入掩模13。注入掩模13配置在将要形成N型连接部75的区域上。注入层IR2形成在比注入层IR1浅的位置。P型杂质例如在注入能量10～200keV、剂量1×1013～1×1015cm-2的条件下被注入。
如图4D所示，在半导体晶片SB的背面选择性地进行N型杂质例如磷(P)的离子注入，形成注入层IR3。在半导体晶片SB的背面上设置有注入掩模15。注入掩模15配置在将要形成P型集电极层50的区域上。注入层IR3形成在比注入层IR2浅的位置。N型杂质例如在注入能量为10～100keV、剂量为1×1015～1×1016cm-2的条件下被注入。
接着，通过实施热处理，使注入的N型杂质及P型杂质活性化。热处理例如使用激光退火法而实施。由此，在注入层IR1所位于的部分形成N型缓冲层60。在注入层IR3所位于的部分形成有N型阴极层70。在Z方向上注入层IR2与注入层IR3重叠的部分形成P型势垒层80。在P型势垒层80中，P型杂质被N型杂质补偿。P型势垒层80具有P型的导电性，具有从P型杂质的浓度减去N型杂质的浓度而得的p型杂质的有效浓度。
另外，在注入层IR2与注入层IR3不重叠的部分形成有P型集电极层50及N型连接部75。P型集电极层50形成于未设置注入层IR3的部分，N型连接部75形成于未设置注入层IR2的部分。P型集电极层50具有比P型势垒层80中的P型杂质的有效浓度高的P型杂质的有效浓度。
图5A及图5B是表示实施方式的第1变形例的半导体装置2的示意图。图5A是表示与沿着图2A中所示的A-A线的剖面相当的剖面的示意图。图5B是表示与沿着图2A中所示的B-B线的剖面相当的剖面的示意图。
如图5A所示，P型集电极层50及N型阴极层70例如在Y方向上延伸且在X方向上交替地配置。
另外，如图5B所示，P型势垒层80在Y方向上延伸，配置在P型集电极层50之间。N型连接部75设置在P型势垒层80中，配置在与P型集电极层50分离的位置。在该例子中，多个N型连接部75沿Y方向配置。多个N型连接部75在Y方向上相互分离地配置。
P型集电极层50、P型势垒层80及N型连接部75的平面配置并不限定于图2C及图5B所示的例子。例如，只要是各自的面积比被保持且N型连接部75与P型集电极层50分离的配置即可。
图6是表示实施方式的第2变形例的半导体装置3的示意剖视图。半导体装置3是具有平面(Planer)型MOS构造的逆导通型IGBT。
如图6所示，在N型基极层10之上选择性地设置有P型基极层20。N型发射极层30选择性地设置在P型基极层20上。栅极电极40以隔着栅极绝缘膜45而与位于P型基极层20之间的N型基极层10的一部分、P型基极层20的一部分及N型发射极层30的一部分相对的方式形成。
在N型基极层10的背面侧设置有P型集电极层50、N型缓冲层60、N型阴极层70、P型势垒层80。N型阴极层70在沿着N型基极层10的背面的方向上与P型集电极层50并列配置。
N型缓冲层60设置在N型基极层10与P型集电极层50之间、以及N型基极层10与N型阴极层70之间。P型势垒层80配置在N型缓冲层与N型阴极层70之间。另外，P型势垒层80以与P型集电极层50相连的方式设置。
进而，半导体装置3具有在N型缓冲层60与N型阴极层70之间不存在P型势垒层80的部分(N型连接部75)。由此，在半导体装置3中能够进行将IGBT及二极管一体化的动作。
图7是表示实施方式的第3变形例的半导体装置4的示意剖视图。半导体装置4是具有沟槽栅极型MOS构造的逆导通型IGBT。另外，MOS构造并不限定于此，也可以是平面栅极型。
如图7所示，在N型基极层10的背面侧设置有P型集电极层50、N型缓冲层60、N型阴极层70、P型势垒层80。N型阴极层70在沿着N型基极层10的背面的方向上与P型集电极层50并列配置。
N型缓冲层60设置在N型基极层10与P型集电极层50之间、以及N型基极层10与N型阴极层70之间。P型势垒层80配置在N型缓冲层与N型阴极层70之间。另外，P型势垒层80以与P型集电极层50相连的方式设置。
进而，半导体装置4具有在N型缓冲层60与N型阴极层70之间不存在P型势垒层80的部分(N型连接部75)。
该例子的P型势垒层80包括第1区域80a、第2区域80b及第3区域80c。第1区域80a、第2区域80b及第3区域80c依次配置在P型集电极层50与N型连接部75之间。第1区域80a与P型集电极层50相连，第3区域80c与N型连接部75相邻。
第1区域80a的Z方向的厚度TP1被设置为比第2区域80b的Z方向的厚度TP2厚。第2区域80b的厚度TP2被设置为比第3区域80c的Z方向的厚度TP3厚。由此，能够提高二极管动作时的骤回的控制性。
另外，半导体装置4例如也可以构成为，使第1区域80a、第2区域80b及第3区域80c的Z方向的厚度恒定，第1区域80a中的P型杂质的有效浓度比第2区域80b中的P型杂质的有效浓度高，第2区域80b中的P型杂质的有效浓度比第3区域80c中的P型杂质的有效浓度高。
另外，半导体装置4例如也可以构成为，第1区域80a、第2区域80b及第3区域80c的Z方向的厚度如图7所示那样变化，第1区域80a中的P型杂质的有效浓度比第2区域80b中的P型杂质的有效浓度高，第2区域80b中的P型杂质的有效浓度比第3区域80c中的P型杂质的有效浓度高。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子提示的，并不意欲限定发明的范围。这些新的实施方式能够以其他各种形态实施，在不脱离发明主旨的范围内，能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围及主旨中，并且包含在权利要求所记载的发明及其等同范围中。

Claims (15)

1.一种半导体装置，其中，具备：
第1导电型的第1半导体层；
第2导电型的第2半导体层，选择性地设置在所述第1半导体层上；
第1导电型的第3半导体层，选择性地设置在所述第2半导体层上；
第1绝缘膜，覆盖位于所述第1半导体层与所述第3半导体层之间的所述第2半导体层的一部分；
控制电极，隔着所述第1绝缘膜而与所述第2半导体层的一部分相对；
第2导电型的第4半导体层，设置在所述第1半导体层的下表面侧；
第1导电型的第5半导体层，在沿着所述第1半导体层的下表面的第1方向上与所述第4半导体层并列配置；
第6半导体层，设置在所述第1半导体层与所述第5半导体层之间，与所述第4半导体层相连；以及
连接部分，是位于所述第1半导体层与所述第5半导体层之间且不隔有所述第6半导体层的部分，用于将所述第5半导体层与所述第1半导体层电连接，
所述第6半导体层具有从第2导电型杂质的浓度减去第1导电型杂质的浓度而得的第2导电型杂质的补偿浓度，所述第6半导体层中的所述第2导电型杂质的补偿浓度比所述第4半导体层中的第2导电型杂质的补偿浓度低。
2.如权利要求1所述的半导体装置，其中，
所述半导体装置还具备：
第1电极，与所述第3半导体层电连接，覆盖所述控制电极；
第2绝缘膜，将所述控制电极与所述第1电极电绝缘；以及
第2电极，与所述第4半导体层及所述第5半导体层电连接。
3.如权利要求2所述的半导体装置，其中，
所述控制电极设置成，在从所述第1电极朝向所述第2电极的第2方向上延伸，并隔着所述第1绝缘膜而与所述第1半导体层、所述第2半导体层及所述第3半导体层相对。
4.如权利要求1所述的半导体装置，其中，
所述第5半导体层经由所述连接部分而与所述第1半导体层电连接。
5.如权利要求1所述的半导体装置，其中，
所述第4半导体层及所述第5半导体层在沿着所述第1半导体层的下表面的所述第1方向上交替地配置。
6.如权利要求1所述的半导体装置，其中，
所述连接部分设置于在沿着所述第1半导体层的下表面的所述第1方向上与所述第4半导体层分离的位置。
7.如权利要求5所述的半导体装置，其中，
所述连接部分沿着所述第1半导体层的下表面在与所述第1方向交叉的第3方向上并列配置有多个，
所述第4半导体层沿着所述第1半导体层的下表面在所述第3方向上延伸，
所述连接部分位于在所述第1方向上相邻的第4半导体层之间。
8.如权利要求1所述的半导体装置，其中，
所述半导体装置还具备：
第7半导体层，设置在所述第1半导体层与所述第4半导体层之间、以及所述第1半导体层与所述第6半导体层之间，包含与所述第1半导体层的第1导电型杂质相比更高浓度的第1导电型杂质，
所述第5半导体层经由所述连接部分而与所述第7半导体层连接。
9.如权利要求8所述的半导体装置，其中，
所述第5半导体层包含与所述第7半导体层的第1导电型杂质相比更高浓度的第1导电型杂质。
10.如权利要求1所述的半导体装置，其中，
所述第4半导体层包含与所述第2半导体层的第2导电型杂质相比更高浓度的第2导电型杂质。
11.如权利要求2所述的半导体装置，其中，
所述半导体装置还具备：
第8半导体层，选择性地设置在所述第2半导体层与所述第1电极之间，包含与所述第2半导体层的第2导电型杂质相比更高浓度的第2导电型杂质，
所述第8半导体层与所述第2半导体层相接触，与所述第1电极电连接。
12.如权利要求1所述的半导体装置，其中，
所述第6半导体层包括在所述第1方向上并列的第1部分、第2部分及第3部分，
所述第1部分与所述第4半导体层相连，所述第2部分位于所述第1部分与所述第3部分之间，
从所述第1半导体层朝向所述第5半导体层的第2方向上的所述第1部分的第1厚度比所述第2方向上的所述第2部分的第2厚度厚，所述第2厚度比所述第2方向上的所述第3部分的第3厚度厚。
13.如权利要求12所述的半导体装置，其中，
所述第1部分的第2导电型杂质的补偿浓度比所述第2部分的第2导电型杂质的补偿浓度高，所述第2部分的所述第2导电型杂质的补偿浓度比所述第3部分的第2导电型杂质的补偿浓度高。
14.如权利要求1所述的半导体装置，其中，
所述第6半导体层包括在所述第1方向上并列的第1部分、第2部分及第3部分，
所述第1部分与所述第4半导体层相连，所述第2部分位于所述第1部分与所述第3部分之间，
所述第1部分的第2导电型杂质的补偿浓度比所述第2部分的第2导电型杂质的补偿浓度高，所述第2部分的所述第2导电型杂质的补偿浓度比所述第3部分的第2导电型杂质的补偿浓度高。
15.如权利要求14所述的半导体装置，其中，
所述第6半导体层的所述第3部分与所述连接部分相邻。
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