CN110828578A - Thin film transistor, preparation method thereof and display device - Google Patents

Thin film transistor, preparation method thereof and display device Download PDF

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Publication number
CN110828578A
CN110828578A CN201910981955.2A CN201910981955A CN110828578A CN 110828578 A CN110828578 A CN 110828578A CN 201910981955 A CN201910981955 A CN 201910981955A CN 110828578 A CN110828578 A CN 110828578A
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layer
thin film
film transistor
barrier layer
forming
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CN110828578B (en
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罗传宝
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Abstract

The invention discloses a thin film transistor, comprising: a substrate; a gate electrode; a gate insulating layer; an active layer; a barrier layer; a source drain electrode; a passivation layer; and the blocking layer is positioned above the active layer and below the source drain electrode, the blocking layer is siloxane containing polar functional groups, and the polar functional groups are at least one of sulfydryl, amino and halogenated alkyl. The barrier layer can effectively prevent Cu ions from diffusing into the active layer to form defects in the subsequent high-temperature process and deteriorate the electrical performance of the device, and the method is simple and convenient to operate, low in cost and short in process time.

Description

Thin film transistor, preparation method thereof and display device
Technical Field
The invention relates to the field of display panels, in particular to a thin film transistor, a preparation method thereof and a display device.
Background
The advantages of large size, high frame rate processing, high transmittance in the visible light range, and the like have wide application prospects in the fields of Active Matrix Liquid Crystal Display (AMLCD), active matrix organic electroluminescent diodes (AMOLED), and the like. With the increase of the size of the TV panel, the capacitance-resistance Delay effect (RC Delay) of the metal wiring needs to be reduced, and the metal Cu is widely used due to low resistance and low cost, but Cu ions are easily diffused into the active layer (IGZO or a-Si) in the subsequent high temperature process to form defects, which deteriorates the electrical performance of the device. In order to block the influence of Cu ion diffusion on the performance of devices, Mo, Ti or MoTi alloy is generally adopted as a blocking layer material in the industry at present to avoid the influence of Cu ion diffusion.
However, the method of stopping the diffusion of Cu ions using Mo, Ti or MoTi alloy still has some drawbacks: 1. at present, barrier layer materials such as Mo or Ti and the like are generally prepared by physical vapor deposition methods such as sputtering and the like, vacuum equipment is expensive, and the processing time (Tacttime) is relatively long; mo is used as a barrier layer to carry Cu, undercutting (undercut) is easily caused by electrochemical oxygen absorption corrosion after Cu/Mo etching, and wiring in a subsequent process is disconnected due to serious undercutting, so that the electrical performance of a device is influenced; MoTi has no undercutting, but the Tail end (Tail) of about 0.2um is easy to appear after etching; if the tail end is longer, when the TFT is smaller, the channel region of the active layer is correspondingly narrowed, and the performance of the device is lost due to the Short circuit (Short) of the source/drain electrode which is longer because of the tail end; cu acid has a relatively slow Mo or MoTi etching rate of about 1/10 of the Cu etching rate, the etching time is short, Mo residue is easy to appear, the CD Loss is large due to long time, and the requirements of fine TFT design are exceeded.
Disclosure of Invention
The embodiment of the invention provides a thin film transistor, which can effectively reduce the possibility that Cu ions in a metal electrode are diffused to an active layer to form defects in a high-temperature process to influence the electrical property of a device.
In order to solve the above problem, in a first aspect, the present invention provides a thin film transistor, including:
a substrate;
a gate electrode disposed on the substrate;
a gate insulating layer disposed on the gate;
an active layer disposed on the gate insulating layer;
a barrier layer disposed over the active layer;
a source and a drain disposed on the barrier layer;
a passivation layer disposed on the source and the drain;
and a pixel electrode disposed on the passivation layer,
wherein the barrier layer is a siloxane containing a polar functional group, and the polar functional group is at least one of a mercapto group, an amine group, and a halogenated alkyl group.
Further, the siloxane contains at least one branch chain, and the branch chain contains 3 or more carbon atoms.
Further, the siloxane is selected from any one of 3-mercaptopropyltrimethoxysilane, 3,3, 3-fluoropropyltrimethoxysilane and 3-aminopropyltrimethoxysilane.
Further, the thickness of the barrier layer is 600-1000 angstroms.
On the other hand, the invention also provides a preparation method of the thin film transistor, which comprises the following steps:
s1, forming a grid electrode on the substrate;
s2, forming a gate insulating layer on the gate;
s3, forming an active layer on the gate insulation layer;
s4, forming a barrier layer on the active layer, wherein the barrier layer is siloxane containing polar functional groups, and the polar functional groups are at least one of mercapto, amino and halogenated alkyl;
s5, forming a source electrode and a drain electrode on the barrier layer;
s6, forming a passivation layer on the source electrode and the drain electrode; and
and S7, forming a pixel electrode on the passivation layer.
Further, in step S4, the method for forming a barrier layer on the active layer includes:
coating a layer of composite liquid on the active layer to obtain a first intermediate thin film transistor;
and then thermally curing the first intermediate thin film transistor,
wherein the composite liquid is a mixed liquid of the siloxane and an organic solvent.
Further, before the step S4 is performed, an ultraviolet lamp is used to irradiate the surface of the active layer.
Further, in step S5, the step of forming the source and the drain includes: depositing a metal film on the barrier layer, exposing and developing, etching the metal film to form corresponding source and drain patterns,
the etching is wet etching, and the liquid medicine of the wet etching is hydrogen peroxide system liquid medicine.
Further, before performing step S6, dry plasma treatment is applied to the source-drain electrode surface, and the gas used is a reducing gas.
In another aspect, the present invention further provides a display device including the foregoing thin film transistor.
Has the advantages that: according to the invention, the barrier layer is arranged between the active layer and the source drain electrode, the barrier layer is made of siloxane containing polar functional groups, and the polar functional groups are at least one of sulfydryl, amido and halogenated alkyl.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
fig. 2 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;
fig. 3A-3D are structural flow charts of a method for fabricating a thin film transistor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the invention. In the following description, details are set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the invention with unnecessary detail. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
A preferred embodiment of the present invention provides a thin film transistor, which is described in detail below with reference to fig. 1.
The thin film transistor includes:
a substrate 101, wherein the material of the substrate 101 may be glass, quartz, resin, polyimide, or other materials commonly used in the art;
a gate 102 disposed on the substrate 101, wherein the gate 102 is usually made of a metal such as molybdenum, aluminum, molybdenum-tungsten alloy, aluminum-nickel alloy, chromium or copper, and the thickness of the gate 102 can be 800-3000 angstroms;
a gate insulating layer 103 covering the gate 102, wherein the gate insulating layer 103 may be silicon oxide, silicon nitride or a stacked structure of silicon oxide and silicon nitride, and a film thickness of the gate insulating layer 103 may be 1500-4000 angstroms;
an active layer 104 disposed on the gate insulating layer 103, wherein the active layer 104 is made of indium gallium tin oxide (IGZO) or amorphous silicon (α -Si), and the thickness of the active layer may be 300-;
a barrier layer 105 disposed on the active layer 104 and completely covering the active layer 104, wherein the material of the barrier layer 105 may be siloxane containing polar functional groups, the polar functional groups are at least one of thiol, amine and alkyl halide, the material body adopts Si-O molecules to enhance affinity with the gate insulating layer 103 (silicon oxide, silicon nitride material), on the other hand, the material contains polar functional groups with strong subversibility such as S, F, N, etc. which have strong chemical bonds or intermolecular forces with Cu to increase adhesion with the source 1061 and the drain 1062,
in a preferred embodiment, the siloxane contains at least one branch chain, the branch chain contains 3 or more carbon atoms, the longer the branch chain is, the longer the path for copper ions to diffuse is relatively, the better the barrier property for copper ions is,
in a preferred embodiment, the siloxane may be any one of 3-mercaptopropyltrimethoxysilane, 3,3, 3-fluoropropyltrimethoxysilane, and 3-aminopropyltrimethoxysilane,
in a preferred embodiment, the barrier layer 105 may be 600-1000 angstroms;
a source 1061 and a drain 1062, wherein the source 1061 and the drain 1062 are disposed on the barrier layer 105, and the source 1061 and the drain 1062 have a channel located above the insulating layer 104, the source 1061 and the drain 1062 are made of copper,
a passivation layer 107 disposed on the source 1061 and the drain 1062, wherein the passivation layer 107 has an open slot disposed on the drain 1062, the passivation layer 107 may be silicon oxide, silicon nitride or a stacked structure of silicon oxide and silicon nitride, and a film thickness of the passivation layer 107 may be 1500-;
and a pixel electrode 108 located on the passivation layer 107 and completely covering the open slot of the passivation layer, wherein the material of the pixel electrode 108 may be indium tin oxide.
The invention also provides a preferred embodiment of a preparation method of the thin film transistor, the preparation method is shown in fig. 2, the detailed preparation process is shown in fig. 3A-3D, and the following concrete description is provided:
the method for manufacturing the thin film transistor provided by the preferred embodiment includes the following steps:
s1: providing a substrate 201, forming a first metal layer on the substrate 201 by adopting a physical vapor deposition method, wherein the first metal layer can be made of molybdenum, aluminum, molybdenum-tungsten alloy, aluminum-nickel alloy, chromium or copper, and then performing photoresist coating, exposure under a mask, development, etching and photoresist stripping to form a gate 202;
s2: forming a gate insulating layer 203 on the gate 202 by using a chemical vapor deposition method, wherein the gate insulating layer 202 may be made of silicon oxide, silicon nitride, or a mixture of silicon oxide and silicon nitride;
s3: depositing a layer of semiconductor material on the gate insulating layer 203, performing photoresist coating, exposing under a mask, developing, etching, and stripping photoresist to form an active layer 104, wherein the semiconductor material may be IGZO or amorphous silicon, and when the semiconductor material is IGZO, performing physical vapor deposition, and when the semiconductor material is amorphous silicon, performing chemical vapor deposition to form the structure shown in fig. 3A;
s4: a barrier layer 205 is coated on the active layer 204 and completely covers the active layer 204, the barrier layer 205 is a siloxane containing a polar functional group, the polar functional group is at least one of a thiol group, an amine group and a halogenated alkyl group, the barrier layer 205 can be 600-1000 angstroms, and the structure shown in fig. 3B is formed,
in a preferred embodiment, the siloxane contains at least one branch chain, the branch chain contains 3 or more carbon atoms, the longer the branch chain is, the longer the path for copper ions to diffuse is relatively, the better the barrier property for copper ions is,
in a preferred embodiment, the siloxane may be any one of 3-mercaptopropyltrimethoxysilane, 3,3, 3-fluoropropyltrimethoxysilane, and 3-aminopropyltrimethoxysilane,
in a preferred embodiment, the step of applying a barrier layer 205 comprises applying a layer of the siloxane to the active layer, which may be by liquid knife coating,
in a preferred embodiment, the step of coating a barrier layer 205 comprises coating a composite liquid of the siloxane and an organic solvent with a mass fraction of 80-95% on the active layer 204 by using a coater, curing the composite liquid on a hot plate at 70-100 ℃ for 1-2h, and cleaning the composite liquid,
in a preferred embodiment, before step S4 is performed, an ultraviolet lamp is used to irradiate the surface of the active layer 205, so as to remove organic contamination on the surface of the active layer 205 and increase interfacial adhesion;
s5: depositing a second metal layer by physical vapor deposition, wherein the second metal layer covers the barrier layer 205, the second metal layer is made of copper, and then performing photoresist coating, exposure under a mask, development, etching, and photoresist stripping to form a source 2061 and a drain 2062, the source 2061 and the drain 2062 are separated by a channel above the active layer 204, forming the structure shown in fig. 3C,
in a preferred embodiment, the etching mode of the second metal layer is wet etching, and the adopted liquid medicine is hydrogen peroxide system liquid medicine;
s6: depositing a passivation layer 207 on the source electrode 2061 and the drain electrode 2062 by chemical vapor deposition, wherein the passivation layer 207 is made of silicon oxide, silicon nitride or a mixture of silicon oxide and silicon nitride, and forming a through hole on the passivation layer 207 by coating photoresist, exposing under a mask, developing, etching and stripping the photoresist, wherein the through hole exposes the drain electrode 2062 at the lower layer,
in a preferred embodiment, before step S6, dry plasma treatment is applied to the surfaces of the source electrode 2061 and the drain electrode 2062, the used gas is a reducing gas, and the metal oxide on the surfaces of the source electrode 2061 and the drain electrode 2062 is removed to avoid electrical deviation of the device;
s7: depositing an indium tin oxide film on the passivation layer by physical vapor deposition, performing photoresist coating, exposing under a mask, developing, etching, and stripping the photoresist to form a pixel electrode 208, wherein the pixel electrode covers the through hole of the passivation layer 207 and contacts the drain electrode 2062, thereby forming the structure shown in fig. 3D.
In another embodiment of the present invention, a display device is provided, which includes the above thin film transistor, and other components in the display device are selected conventionally in the art, and the present invention is not limited thereto.
It should be noted that, in the above-mentioned thin film transistor embodiment, only the above-mentioned structure is described, and it is understood that, in addition to the above-mentioned structure, the thin film transistor according to the embodiment of the present invention may further include any other necessary structure as needed, and the details are not limited herein.
By adopting the thin film transistor, the preparation method thereof and the display device described in the above embodiments, a barrier layer is arranged between the active layer and the source and drain electrodes, the barrier layer is made of siloxane containing polar functional groups, and the polar functional groups are at least one of mercapto, amino and halogenated alkyl, so that the barrier effect of the material is more excellent than that of the existing Mo, Ti or MoTi alloy, the coating method is simple, and the cost and the processing time are saved; the display device comprising the structure can effectively avoid poor display caused by diffusion of copper ions to the active layer.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and parts that are not described in detail in a certain embodiment may refer to the above detailed descriptions of other embodiments, and are not described herein again.
The thin film transistor provided by the embodiment of the present invention is described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. A thin film transistor, comprising:
a substrate;
a gate electrode disposed on the substrate;
a gate insulating layer disposed on the gate;
an active layer disposed on the gate insulating layer;
a barrier layer disposed over the active layer;
a source and a drain disposed on the barrier layer;
a passivation layer disposed on the source and the drain; and
a pixel electrode disposed on the passivation layer,
the barrier layer is siloxane containing polar functional groups, and the polar functional groups are at least one of sulfydryl, amino and halogenated alkyl.
2. The thin film transistor according to claim 1, wherein the siloxane has at least one branch, and wherein the branch has 3 or more carbon atoms.
3. The thin film transistor according to claim 1 or 2, wherein the siloxane is any one selected from the group consisting of 3-mercaptopropyltrimethoxysilane, 3,3, 3-fluoropropyltrimethoxysilane, and 3-aminopropyltrimethoxysilane.
4. The thin film transistor of claim 1, wherein the thickness of the barrier layer is 600-1000 angstroms.
5. A method for manufacturing a thin film transistor includes:
s1, forming a grid electrode on the substrate;
s2, forming a gate insulating layer on the gate;
s3, forming an active layer on the gate insulation layer;
s4, forming a barrier layer on the active layer, wherein the barrier layer is siloxane containing polar functional groups, and the polar functional groups are at least one of mercapto, amino and halogenated alkyl;
s5, forming a source electrode and a drain electrode on the barrier layer;
s6, forming a passivation layer on the source electrode and the drain electrode; and
and S7, forming a pixel electrode on the passivation layer.
6. The method of manufacturing a thin film transistor according to claim 5, wherein in step S4, the method of forming a barrier layer on the active layer comprises:
coating a layer of composite liquid on the active layer to obtain a first intermediate thin film transistor;
and then thermally curing the first intermediate thin film transistor,
wherein the composite liquid is a mixed liquid of the siloxane and an organic solvent.
7. The method of manufacturing a thin film transistor according to claim 5 or 6, wherein a surface of the active layer is irradiated with an ultraviolet lamp before the step S4 is performed.
8. The method of manufacturing a thin film transistor according to claim 5, wherein in the step of S5, the step of forming the source electrode and the drain electrode includes: depositing a metal film on the barrier layer, exposing and developing, etching the metal film to form corresponding source and drain patterns,
the etching is wet etching, and the liquid medicine of the wet etching is hydrogen peroxide system liquid medicine.
9. The method of manufacturing a thin film transistor according to claim 5, wherein a dry plasma treatment is applied to the source-drain electrode surface before the step of S6, and a reducing gas is used.
10. A display device comprising the thin film transistor according to any one of claims 1 to 4.
CN201910981955.2A 2019-10-16 2019-10-16 Thin film transistor, preparation method thereof and display device Active CN110828578B (en)

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CN109148303A (en) * 2018-07-23 2019-01-04 深圳市华星光电半导体显示技术有限公司 The preparation method of thin film transistor (TFT)

Cited By (3)

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Publication number Priority date Publication date Assignee Title
CN111554694A (en) * 2020-05-13 2020-08-18 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof, display panel and display device
WO2021227889A1 (en) * 2020-05-13 2021-11-18 京东方科技集团股份有限公司 Thin film transistor, manufacturing method therefor, display panel, and display device
CN114980477A (en) * 2021-02-18 2022-08-30 合肥鑫晟光电科技有限公司 Back plate, backlight source, illuminating device and display device

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