CN110768205B

CN110768205B - Overcurrent protection circuit

Info

Publication number: CN110768205B
Application number: CN201911107686.3A
Authority: CN
Inventors: 宅间彻; 高桥直树; 高桥俊太郎
Original assignee: Rohm Co Ltd
Current assignee: Rohm Co Ltd
Priority date: 2016-04-28
Filing date: 2017-03-03
Publication date: 2022-02-25
Anticipated expiration: 2037-03-03
Also published as: JPWO2017187785A1; CN109075556B; US11637420B2; US10790657B2; JP6719015B2; US20200403393A1; CN110768205A; US20220037872A1; DE112017001822T5; JP2019198226A; CN109075556A; JP6563590B2; KR20180126042A; US20230216289A1; US11183829B2; KR102083204B1; US11843235B2; KR102253458B1; WO2017187785A1; KR20200022533A

Abstract

In order to provide both instantaneous current and overcurrent protection according to the load, the overcurrent protection circuit 71 includes: a threshold generation unit 130 that switches between setting the overcurrent detection threshold Vth to a first set value (° Iref) and a second set value (° Iset) lower than the first set value, according to a threshold control signal S170; an overcurrent detection unit 140 that compares a sensing signal Vs according to the monitored current with an overcurrent detection value Vth and generates an overcurrent protection signal S71; a reference value generation unit 150 that generates a reference value VIset (. di.. di) from the second set value; a comparison unit 160 that compares the sensing signal Vs and the reference value VIset and generates a comparison signal VCMP; a threshold control unit 170 which monitors the comparison signal VCMP and generates a threshold control signal S170.

Description

Overcurrent protection circuit

The present application is a divisional application of an invention application having an application number of 201780026285.8 and a name of "overcurrent protection circuit", which is proposed on 3.3.2017.

Technical Field

The present invention relates to an overcurrent protection circuit.

Background

In general, many semiconductor integrated circuit devices are provided with an overcurrent protection circuit as their abnormality protection circuit. For example, an in-vehicle IPD (smart power device) is provided with an overcurrent protection circuit that limits the amount of output current flowing through a power transistor to not exceed an overcurrent setting value to prevent the device from being damaged in the event of a disconnection in a load connected to the power transistor. In recent years, an overcurrent protection circuit capable of adjusting an overcurrent setting value as needed by using an external resistor has been provided.

Examples of conventional techniques related to the above are disclosed in patent document 1 and patent document 2 listed below.

Documents of the prior art

Patent document

Patent document 1: japanese laid-open patent publication (JP 2015-46954)

Patent document 2: japanese patent laid-open No. 2012-211805

Disclosure of Invention

Technical problem

However, the load connected to the power transistor includes one load (such as a capacitive load) that requires a large output current to instantaneously flow in its normal operation. In the case where the target to be monitored is such an output current, with a conventional overcurrent protection circuit, having a single overcurrent setting value, it is difficult to achieve overcurrent protection that ensures the instantaneous current and the load are appropriate.

In particular, in recent years, in-vehicle ICs are required to comply with ISO26262 (international standard for producing functional safety of electrical and electronic systems in automobiles), and also for in-vehicle IPDs, higher reliability designs have become important.

The invention disclosed herein has been made in view of the above-mentioned problems found by the inventors of the present invention, and an object thereof is to provide an overcurrent protection circuit capable of simultaneously realizing overcurrent protection that ensures both an instantaneous current and a load to be appropriate.

Means for solving the problems

The overcurrent protection circuit disclosed herein includes: a threshold generator that switches between whether the overcurrent detection threshold should be a first set value or a second set value lower than the first set value according to a threshold control signal; an overcurrent detector that compares a sensing signal according to the monitoring current with an overcurrent detection threshold, thereby generating an overcurrent protection signal; a reference value generator that generates a reference value according to the second setting value; a comparison section that compares the sensing signal with a reference value, thereby generating a comparison signal; and a threshold controller that monitors the comparison signal to generate a threshold control signal (first configuration).

In the overcurrent protection circuit having the first configuration, when the overcurrent detection threshold has been set to the first set value, the threshold controller may generate the threshold control signal so that the overcurrent detection threshold is switched to the second set value (the second configuration) at a point of time when the masking period elapses in a case where the sensing signal remains above the reference value.

In the overcurrent protection circuit having the second configuration, when the overcurrent detection threshold has been set to the second set value, the threshold controller may generate the threshold control signal so that the overcurrent detection threshold is switched to the first set value at a point in time when the sense signal falls below the reference value (third configuration).

In the overcurrent protection circuit having the second or third configuration, the mask period may be a variable value (fourth configuration).

In the overcurrent protection circuit having any one of the first to fourth configurations, the first set value may be a fixed value, and the second set value may be a variable value (fifth configuration).

The semiconductor integrated circuit device disclosed herein includes a power transistor integrated therein, the power transistor switching a current path through which an output current flows between an on state and an off state; an output current monitor that generates a sense signal from the output current; a gate controller generating a driving signal of the power transistor according to the control signal; and an overcurrent protection circuit having any one of the first to fifth configurations that monitors the sensing signal to generate the overcurrent protection signal. Here, the gate controller has a function of forcibly turning off the power transistor in accordance with the overcurrent protection signal (sixth configuration).

The semiconductor integrated circuit device having the sixth configuration may further include a signal output section integrated therein that selectively outputs one of a detection result of the output current and an abnormality flag to the outside of the device as the state notification signal (seventh configuration).

The electronic apparatus disclosed herein includes a semiconductor integrated circuit device having the sixth or seventh configuration, and a load (eighth configuration) connected to the semiconductor integrated circuit device.

In the electronic device having the eighth configuration, the load may be a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor (ninth configuration).

The vehicle disclosed herein includes an electronic device having an eighth or ninth configuration (tenth configuration).

The overcurrent protection circuit disclosed herein includes: a first threshold generator that switches whether the first overcurrent detection threshold should be a first set value or a second set value lower than the first set value, in accordance with a first threshold control signal; a second threshold generator that switches whether the second overcurrent detection threshold should be a third set value or a fourth set value lower than the third set value, in accordance with a second threshold control signal; a first overcurrent detector that compares a first sensing signal according to the first monitor current with a first overcurrent detection threshold, thereby generating a first overcurrent protection signal; a second overcurrent detector that compares a second sensing signal according to the second monitor current with a second overcurrent detection threshold, thereby generating a second overcurrent protection signal; a first reference value generator that generates a first reference value according to a second setting value; a second reference value generator that generates a second reference value according to the fourth setting value; a first comparing section that compares the first sensing signal with a first reference value, thereby generating a first comparison signal; a second comparing section; which compares the second sensing signal with a second reference value, thereby generating a second comparison signal; and a threshold controller that monitors the first comparison signal and the second comparison signal, thereby generating a first threshold control signal and a second threshold control signal (eleventh configuration).

In the overcurrent protection circuit having the eleventh configuration, the threshold controller may include: an external terminal for externally connecting the capacitor; a comparator that compares a charging voltage appearing at the external terminal with a predetermined reference voltage, thereby generating an internal signal; a first trigger generating a first threshold control signal according to the internal signal and the first comparison signal; a second trigger generating a second threshold control signal according to the internal signal and the second comparison signal; a discharge controller that performs discharge control of the capacitor according to the internal signal; and a charging controller that performs charging control of the capacitor in accordance with the first comparison signal and the second comparison signal (twelfth configuration).

In the overcurrent protection circuit having the twelfth configuration, the discharge controller may accept not only input of the internal signal but also input of the first comparison signal, the second comparison signal, the first threshold control signal, and the second threshold control signal, and in a case where, after a logic level change occurs in one of the first comparison signal and the second comparison signal and a charging operation of the capacitor is started, the logic level change occurs in the other one of the first comparison signal and the second comparison signal before the charging voltage becomes higher than the reference voltage, the capacitor may be discharged (thirteenth configuration).

In the overcurrent protection circuit having the thirteenth configuration, the threshold controller may further include: a first delay section that gives a delay to the first comparison signal, thereby generating a first delayed signal; and a second delay section that gives a delay to the second comparison signal, thereby generating a second delayed signal, and the first delayed signal and the second delayed signal may be input to the first flip-flop and the second flip-flop, respectively, instead of the first comparison signal and the second comparison signal (fourteenth configuration).

In the overcurrent protection circuit having any one of the eleventh to fourteenth configurations, the first set value and the third set value may both be fixed values, and the second set value and the fourth set value may both be variable values (fifteenth configuration).

The semiconductor integrated circuit device disclosed herein includes a first power transistor integrated therein that switches a first current path through which a first output current flows between an on state and an off state; a second power transistor that switches a second current path through which the second output current flows between an on state and an off state; a first output current monitor that generates a first sense signal from a first output current; a second output current monitor that generates a second output current from the second output current; a first gate controller generating a first driving signal for the first power transistor according to a first control signal; a second gate controller generating a second driving signal for the second power transistor according to a second control signal; and an overcurrent protection circuit having any one of the eleventh to fifteenth configurations that monitors the first sensing signal and the second sensing signal to generate the first overcurrent protection signal and the second overcurrent protection signal. Here, the first gate controller and the second gate controller have a function of forcibly turning off the first power transistor and the second power transistor in accordance with the first overcurrent protection signal and the second overcurrent protection signal, respectively (sixteenth configuration).

The semiconductor integrated circuit device having the sixteenth configuration may further include a first signal output section integrated therein, the first signal output section generating one of a detection result of the first output current and an abnormality flag as the first state notification signal; a second signal output section that generates one of a detection result of the second output current and an abnormality flag as a second state notification signal; and a multiplexer that selectively outputs one of the first state notification signal and the second state notification signal to the outside of the apparatus (seventeenth configuration).

An electronic apparatus disclosed herein includes a semiconductor integrated circuit device having a sixteenth or seventeenth configuration, a first load connected to a first power transistor, and a second load connected to a second power transistor (eighteenth configuration).

In the electronic device having the eighteenth configuration, the first load and the second load may each be a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor (nineteenth configuration).

The vehicle disclosed herein includes an electronic device having an eighteenth or nineteenth configuration (twentieth configuration).

ADVANTAGEOUS EFFECTS OF INVENTION

According to the invention disclosed herein, an overcurrent protection circuit can be provided that simultaneously achieves overcurrent protection that ensures both instantaneous current and load suitability.

Drawings

Fig. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit device;

fig. 2 is a block diagram showing an example of the configuration of a signal output section;

fig. 3 is a block diagram showing an example of the configuration of a gate controller;

fig. 4 is a block diagram showing an example of the configuration of the overcurrent protection circuit;

fig. 5 is a circuit diagram showing an example of the configuration of the first current generator;

fig. 6 is a circuit diagram showing an example of the configuration of the second current generator;

fig. 7 is a circuit diagram showing an example of the configuration of the threshold voltage generator and the overcurrent detector;

fig. 8 is a diagram showing an example of an overcurrent setting value;

fig. 9 is a circuit diagram showing an example of the configuration of the reference voltage generator and the comparison section;

fig. 10 is a circuit diagram showing an example of the configuration of the threshold controller;

fig. 11 is a timing chart of an example of an overcurrent protection operation;

fig. 12 is a flowchart showing an example of the threshold switching operation;

fig. 13 is a schematic diagram showing a first use example of the overcurrent protection circuit;

fig. 14 is a schematic diagram showing a second use example of the overcurrent protection circuit;

fig. 15 is a block diagram showing a second embodiment of a semiconductor integrated circuit device;

fig. 16 is a block diagram showing an example of a configuration of a two-channel overcurrent protection circuit;

FIG. 17 is a block diagram showing a first example of a threshold controller;

fig. 18 is a timing chart showing a threshold value switching operation of the first example;

fig. 19 is a timing chart showing a disadvantage of the first example;

FIG. 20 is a block diagram of a second example of a threshold controller;

fig. 21 is a block diagram showing an example of the configuration of the discharge controller;

fig. 22 is a timing chart showing a threshold value switching operation of the second example;

fig. 23 is a timing chart showing a disadvantage of the second example;

FIG. 24 is a block diagram showing a third example of a threshold controller;

fig. 25 is a timing chart showing a threshold value switching operation of the third example;

fig. 26 is a flowchart showing an example of the threshold switching operation;

FIG. 27 is a block diagram showing an example of an ingress multiplexer; and

fig. 28 is an external view of a vehicle, showing an example of the configuration of the vehicle.

Detailed Description

< semiconductor Integrated Circuit device (first embodiment) >

Fig. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 of the present embodiment is an in-vehicle high-side switch IC (a kind of in-vehicle IPD) that realizes an on/off state between an application terminal of a power supply voltage VBB and a load 3 according to an instruction from an ECU (electronic control unit) 2

Here, the semiconductor integrated circuit device 1 includes the external terminals T1 to T4 as units for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal (VBB pin) for receiving supply of a power supply voltage VBB (e.g., 12V) from a battery, not shown. The external terminal T2 is a load connection terminal (OUT pin) for externally connecting a load 3 such as a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor. The external terminal T3 is a signal input terminal (IN pin) for receiving an external input of the external control signal Si from the ECU 2. The external terminal T4 is a signal output pin (SENSE pin) for externally outputting the state notification signal So to the ECU 2. Here, an external sense resistor 4 is externally connected between the external terminal T4 and the ground terminal.

The semiconductor integrated circuit device 1 includes an NMOSFET 10, an output current monitor 20, a gate controller 30, a control logic section 40, a signal input section 50, an internal power supply 60, an abnormality protection section 70, an output current detector 80, and a signal output section 90 integrated therein.

The NMOSFET 10 is a high withstand voltage (e.g., withstand voltage 42V) power transistor whose drain is connected to the external terminal T1 and source is connected to the external terminal T2. The NMOSFET 10 connected in this way functions as a switching element (high-side switch) that switches a current path from the application terminal of the supply voltage VBB to the ground terminal via the load 3 between an on state and an off state. The NMOSFET 10 is turned on when the gate drive signal G1 is at a high level and turned off when the gate drive signal G1 is at a low level.

The NMOSFET 10 may be designed to have an on-resistance of several tens of m Ω. However, the lower the on-resistance value of the NMOSFET 10, the more likely it is that an overcurrent flows when a ground fault of the external terminal T2 occurs (i.e., when shorted to a ground terminal or to a terminal having an equivalent low potential), which may cause abnormal heat generation. Therefore, the lower the on-resistance of the NMOSFET 10, the more important the overcurrent protection circuit 71 and the temperature protection circuit 73, both of which will be described later, become.

The output current monitor 20 includes NMOSFETs 21 and 21' and a sense resistor 22, and generates a sense voltage Vs (═ corresponding to a sense signal) from an output current Io flowing through the NMOSFET 10.

Both the NMOSFET21 and the NMOSFET21 ', which are mirror transistors connected in parallel to the NMOSFET 10, generate sense currents Is and Is', respectively, from the output current Io. The size ratio between the NMOSFET 10 and the NMOSFETs 21 and 21' is m:1 (where m > 1). Therefore, the sense currents Is and Is' are equal to 1/m of the output current Io. Like the NMOSFET 10, the NMOSFETs 21 and 21' are turned on when the gate drive signal G1 is at a high level and turned off when the gate voltage G2 is at a low level.

The sense resistor 22 (resistance: Rs) Is connected between the source of the NMOSFET21 and the external terminal T2, and Is a current/voltage conversion element that generates a sense voltage Vs (═ Is × Rs + Vo, where Vo denotes an output voltage appearing at the external terminal T2) from the sense current Is.

The gate controller 30 generates a gate driving signal G1 that increases the current capability of the gate control signal S1, and outputs the gate driving signal G1 to the gates of the NMOSFET 10 and the NMOSFET21, thereby controlling on/off of the NMOSFET 10 and the NMOSFET 21. Here, the gate controller 30 includes the following functions: in the case where the overcurrent protection signal S71 is at the logic level at the time of abnormality detection, the

NMOSFETs

10 and 21 are forcibly turned off regardless of the gate control signal S1.

The control logic 40 generates a gate control signal S1 when receiving the internal power supply voltage Vreg. For example, when the external control signal Si is at a high level (═ logic level to turn on NMOSFET), the internal power supply voltage Vreg is supplied from the internal voltage 60 so that the control logic section 40 is changed to an operating state, and the gate control signal S1 is changed to a high level (═ Vreg). On the other hand, when the external control signal Si is at a low level (═ logic level to turn off the NMOSFET 10), the internal power supply voltage Vreg is not supplied from the internal power supply 60, so that the control logic section 40 becomes a non-operating state, and the gate control signal S1 becomes a low level (═ GND). In addition, the control logic 40 monitors various abnormal protection signals (the overcurrent protection signal S71, the open protection signal 72, the temperature protection signal S73, and the voltage drop protection signal S74). The control logic unit 40 also has a function of generating the output switching signal S2 based on the monitoring results of the overcurrent protection signal S71, the open-circuit protection signal 72, and the temperature protection signal S73 among the above-mentioned abnormal protection signals.

The signal input section 50 is a schmitt trigger, and receives an external control signal Si from an external terminal T3 and transmits it to the control logic section 40 and the internal power supply 60. Here, the external control signal Si becomes a high level to turn on the NMOSFET 10, and becomes a low level to turn off the NMOSFET 10.

The internal power supply 60 generates a predetermined internal supply voltage Vreg from the supply voltage VBB and supplies it to each section of the semiconductor integrated circuit device 1. Here, whether the internal power supply 60 can operate or not is controlled according to the external control signal Si. More specifically, the internal power supply 60 is in an operating state when the external control signal Si is at a high level, and is in a non-operating state when the external control signal Si is at a low level.

The abnormality protection section 70 is a circuit block that detects various abnormalities occurring in the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and a voltage drop protection circuit 74.

The overcurrent protection circuit 71 generates an overcurrent protection signal S71 according to the monitoring result of the sense voltage Vs (whether an overcurrent abnormality of the output current Io occurs). Here, the overcurrent protection signal S71 changes to a low level when abnormality is not detected, and changes to a high level when abnormality is detected, for example.

The open-circuit protection circuit 72 generates an open-circuit protection signal S72 based on the monitoring result of the output voltage Vo (whether or not an open-circuit abnormality of the load 3 occurs). Here, for example, the open protection signal S72 becomes low level when no abnormality is detected, and the open protection signal S72 becomes high level when an abnormality is detected.

The temperature protection circuit 73 includes a temperature detection element (not shown) for detecting abnormal heat generation in the semiconductor integrated circuit device 1 (particularly, around the NMOSFET 10), and generates a temperature protection signal S73 in accordance with the detection result (whether abnormal heat generation occurs or not). Here, for example, the temperature protection signal S73 changes to a low level in the temperature protection signal S73 when no abnormality is detected, and changes to a high level in the temperature protection signal S73 when an abnormality is detected.

The voltage drop protection circuit 74 generates a voltage drop protection signal S74 according to the monitoring result of the supply voltage VBB or the internal supply voltage Vreg (whether a voltage drop abnormality occurs). Here, for example, the voltage drop protection signal S74 becomes low level when no abnormality is detected in the voltage drop protection signal S74, and becomes high level when an abnormality is detected in the voltage drop protection signal S74.

The output current detector 80 makes the source voltage of the NMOSFET21 'equal to the output voltage Vo using a bias unit (not shown), and thereby generates and outputs a sensing current Is' (═ Io/m) according to the output current Io to the signal output section 90.

Based on the output selection signal S2, the signal output section 90 selectively outputs one of a sense current Is' (corresponding to the detection result of the output current Io) and a fixed voltage V90 (corresponding to an abnormality flag not explicitly shown in the drawing) to the external terminal T4. Here, in the case of selectively outputting the sense current Is ', an output detection voltage V80(═ Is ' × R4) obtained by current/voltage converting the sense current Is ' by the external sense resistor 4 (resistance: R4) Is sent to the ECU2 as a state notification signal. Here, the output detection voltage V80 increases as the output current Io increases, and decreases as the output current Io decreases. On the other hand, when the fixed voltage V90 is selectively output, the fixed voltage V90 is sent to the ECU2 as a state notification signal.

< Signal output section >

Fig. 2 is a block diagram showing an example of the configuration of the signal output section 90. The signal output section 90 of this configuration example includes a selector 91. The selector 91 selectively outputs the sense current Is' to the external terminal T4 when the output selection signal S2 Is at a logic level (e.g., a low level) at which abnormality Is not detected, and the selector 91 selectively outputs the fixed voltage V90 to the external terminal T4 when the output selection signal S2 Is at a logic level (e.g., a high level) at which abnormality Is detected. Here, the fixed voltage V90 is set to a voltage value higher than the upper limit value of the above-described output detection voltage V80.

According to such a signal output portion 90, it is possible to transmit both the detection result of the output current Io and the abnormality flag to the ECU2 by using a single state notification signal So, and therefore, it contributes to reducing the number of external terminals. Here, in the case of reading the present value of the output current Io from the state notification signal So, a/D (analog-to-digital) conversion is performed on the state signal So. On the other hand, in the case of reading the abnormality flag from the state signal So, the logic level of the state signal So is determined by using a threshold value slightly lower than the fixed voltage V90.

< Gate controller >

Fig. 3 is a block diagram showing a configuration example of the gate controller 30. The gate controller 30 of the present configuration example includes a gate driver 31, an oscillator 32, a charge pump 33, a clamp 34, and an NMOSFET 35.

The gate driver 31 is connected between an output terminal (an application terminal of the bootstrap voltage VG) of the charge pump 33 and an external terminal T2 (an application terminal of the output voltage Vo), and generates a gate drive signal G1 that increases the current capacity of the gate control signal S1. Here, when the gate control signal S1 is at a high level, the gate driving signal G1 is at a high level (VG), and when the gate control signal S1 is at a low level, the gate driving signal G1 is at a low level.

The oscillator 32 generates a clock signal CLK of a predetermined frequency and outputs it to the charge pump 33. Whether the vibrator 32 can operate is controlled according to the enable signal Sa received from the control logic 40.

The charge pump 33 generates a bootstrap voltage VG higher than the supply voltage VBB by driving the flying capacitor using the clock signal CLK. Here, whether or not the charge pump 33 is able to operate is controlled based on the enable signal Sb received from the control logic section 40.

The clamp 34 is connected between an external terminal T1 (application terminal of the supply voltage VBB) and the gate of the NMOSFET. In the application of connecting the inductive load 3 to the external terminal T2, when the NMOSFET 10 is switched from ON to OFF, the counter electromotive force of the load 3 causes the output voltage Vo to become a negative voltage (< GND). Thus, a clamp 34 (referred to as an active clamp) is provided for energy absorption.

The drain of the NMOSFET 35 is connected to the gate of the NMOSFET 10. The source of the NMOSFET 35 is connected to the external terminal T2. The gate of the NMOSFET 35 is connected to the application terminal of the overcurrent protection signal S71.

In the gate controller 30 of the present configuration example, when the first overcurrent protection signal S71 is at a low level (no abnormal logic level is detected), the NMOSFET 35 is turned off, and accordingly the gate drive signal G1 is applied to the NMOSFET 10 in a normal manner. On the other hand, when the overcurrent protection signal S71 is at a high level (logic level when abnormality is detected), the NMOSFET turns on and accordingly short-circuits between the gate and the source of the NMOSFET 10.

In this way, the gate controller 30 of the present configuration example has the control gate drive signal G1 such that the NMOSFET is forcibly turned off when the overcurrent protection signal S71 is at a high level (logic level when abnormality is detected).

< overcurrent protection Circuit >

Fig. 4 is a block diagram showing a configuration example of the overcurrent protection circuit 71. The overcurrent protection circuit 71 of the present configuration example includes a first current generator 110, a second current generator 120, a threshold voltage generator 130, an overcurrent detector 140, a reference voltage generator 150, a comparison section 160, and a threshold controller 170.

The first current generator 110 generates a first current Iref and outputs it to the threshold voltage generator 130. The first current Iref has a current value fixed within the semiconductor integrated circuit device 1.

The second current generator 120 generates a second current Iset and outputs it to the threshold voltage generator 130. The second current Iset has a current value that is adjustable as required from outside the semiconductor current device 1.

The threshold voltage generator 130 switches between setting the threshold voltage Vth (corresponding to the overcurrent detection threshold) to an internal setting value VthH or an external setting value VthL (VthH > VthL) in accordance with the threshold control signal S170. Here, the internal set value VthH is a fixed value set in accordance with the first current Iref (corresponding to the first set value). On the other hand, the external set value VthL is a variable value set in accordance with the second current Iset (corresponding to the second set value).

The overcurrent detector 140 compares the sense voltage Vs with the threshold voltage Vth, thereby generating an overcurrent protection signal S71.

The reference voltage generator 150 sets a reference voltage vset (corresponding to a reference value) according to the second current Iset.

The comparison section 160 compares the sensing voltage Vs with the reference voltage VIset, thereby generating a comparison signal VCMP.

Threshold controller 170 monitors comparison signal VCMP, thereby generating threshold control signal S170. Here, when the internal setting value VthH should be selected as the threshold voltage Vth, the threshold control signal S170 becomes low level, and when the external setting value VthL should be selected as the threshold voltage Vth, the threshold control signal S170 becomes high level.

< first Current Generator >

Fig. 5 is a circuit diagram showing a configuration example of the first current generator 110. The first current generator 110 of the present configuration example includes an operational amplifier 111, an NMOSFET 112, and a resistor 113 (resistance: R113).

The supply terminal of the operational amplifier 111 is connected to the application terminal of the internal supply voltage Vreg. The reference potential terminal of the operational amplifier is connected to the ground terminal (GND). A non-inverting input terminal (+) of the operational amplifier 111 is connected to an application terminal of a reference voltage Vref (e.g., a bandgap reference voltage that is not susceptible to power supply variation, temperature variation, or the like). The inverting terminal (-) of the operational amplifier 111 and the source of the NMOSFET 112 are connected to a first terminal of a resistor 113. A second terminal of the resistor 113 is connected to the ground terminal GND. The output terminal of the operational amplifier 111 is connected to the gate of the NMOSFET 112. The drain of the NMOSFET 112 is connected to the output terminal of the first current Iref.

The operational amplifier 111 connected as described above controls the gate of the transistor 112 so that the inverting input terminal (+) and the non-inverting input terminal (-) are virtually short-circuited. Therefore, a first current (Vref × R113) having a fixed value flows through the resistor 113.

< second Current Generator >

Fig. 6 is a circuit diagram showing a configuration example of the second current generator 120. The second current generator 120 of the present configuration example includes an operational amplifier 121, an NMOSFET 122, a resistor 123 (resistance: R123), and an external terminal SET.

An application terminal of the internal supply voltage Vreg is connected to a supply terminal of the operational amplifier 121. The reference potential terminal of the operational amplifier 121 is connected to the ground terminal GND. A non-inverting input terminal (+) of the operational amplifier 121 is connected to an application terminal of the reference voltage Vref. The inverting input terminal (-) of the operational amplifier 121 and the source of the NMOSFET 122 are connected to the external terminal SET. The output terminal of the operational amplifier 121 is connected to the gate of the NMOSFET 122. The drain of the NMOSFET 122 is connected to the output terminal of the second current Iset. The resistor 123 is connected between the external terminal SET and the ground terminal GND outside the semiconductor integrated circuit device 1.

The operational amplifier 121 connected as described above controls the gate of the transistor 122 so that the non-inverting input terminal (+) and the inverting input terminal (-) are virtually short-circuited. Therefore, the second current Iset (═ Vref × R123) according to the resistance R123 of the resistor 123 flows through the resistor 123. That is, the second current Iset increases as the resistance R123 increases, and decreases as the resistance R123 decreases. Therefore, the second current Iset can be adjusted as needed by using the externally connected resistor 123. Here, by using a cascode circuit in the differential stage within the operational amplifier 121, the second current Iset can be set more accurately.

< threshold Voltage Generator, overcurrent Detector >

Fig. 7 is a circuit diagram showing a configuration example of the threshold voltage generator 130 and the overcurrent detector 140. The threshold voltage generator 130 includes a current source 131, a resistor 132, and a current mirror 133. On the other hand, the overcurrent detector 140 includes a comparator 141.

The current source 131 is connected between the current input terminal of the current mirror 133 and the application terminal of the constant voltage VBBM5, and selectively outputs one of the first current Iref and the second current Iset according to the threshold control current S170. More specifically, the current source 131 selectively outputs the first current Iref when the threshold control signal S170 is at a low level, and the current source 131 selectively outputs the second current Iset when the threshold control signal S170 is at a high level.

The resistor 132 is connected between the current output terminal of the current mirror 133 and the application terminal of the output voltage Vo (i.e., the external terminal T2), and the resistance value of the resistor 132 is switched to one of the first resistance Rref1 and the second resistance Rref2 according to the threshold control signal S170. More specifically, when the threshold control signal S170 is at a low level, the resistance of the resistor 132 is the first resistance Rref1, and when the threshold control signal S170 is at a high level, the resistance of the resistor 132 is the second resistance Rref 2.

The current mirror 133 operates upon receiving the supply of the constant voltage VBB _ REF and the bootstrap voltage VG, mirrors the first current Iref or the second current Iset input thereto from the current source 131, and outputs to the resistor 132. Therefore, at the current output terminal (the high potential terminal of the resistor 132) of the current mirror 133, the threshold voltage Vth is generated whose voltage value is switched in accordance with the threshold control signal S170. More specifically, when the threshold control signal S170 is at a low level, the threshold voltage Vth is an internal set value VthH (═ Iref × Rref1), and when the threshold control signal S170 is at a high level, the threshold voltage Vth is an external set value VthL (═ Iset × Rref 2). Here, the current mirror 133 also functions as a level shifter that delivers the first current Iref or the second current Iset from the first power supply system (VBB _ REF-VBBM5 system) to the second power supply system (VG-Vo system).

Here, the constant voltage VBB _ REF and the constant voltage VBBM5 are both reference voltages generated in the semiconductor integrated circuit device 1, for example, VBB _ REF ≈ VBB and VBBM5 ≈ VBB 5V.

The power supply terminal of the comparator 141 is connected to the application terminal of the bootstrap voltage VG. The reference potential terminal of the comparator 141 is connected to the application terminal (external terminal T2) of the output voltage Vo. A non-inverting input terminal (+) of the comparator 141 is connected to an application terminal of the sensing voltage Vs. The non-inverting input terminal (-) of the comparator 141 is connected to the application terminal of the threshold voltage Vth. The comparator 141 connected in this way compares the sensing voltage Vs with the threshold voltage Vth, and thereby generates the overcurrent protection signal S71. The overcurrent protection signal S71 becomes low level (logic level when overcurrent is detected) when the sense voltage Vs is lower than the threshold voltage Vth, and the overcurrent protection signal S71 becomes high level (logic level when overcurrent is not detected) when the sense voltage Vs is higher than the threshold voltage Vth.

Fig. 8 is a diagram showing an example of the overcurrent setting value. As described above, the threshold voltage Vth, which is compared with the sensing voltage Vs, is switched to one of the internal setting value VthH and the external setting value VthL according to the threshold control signal S170. This corresponds to the overcurrent setting value Iocp being compared with the output current Io being switched to one of the internal setting value IocpH and the external setting value IocpL.

Here, it is desirable that the internal set value IocpH is a fixed value (for example, about 15A) in accordance with the on-resistance of the NMOSFET 10, the device withstand voltage, and the like, so that the semiconductor integrated circuit device 1 is not damaged even in the event of a short circuit in the load 3. Therefore, the internal set value IocpH is provided for the special purpose of protecting the semiconductor integrated circuit device 1 itself, and often deviates largely from the stable value of the output current Io.

On the other hand, in view of the fact that the abnormal value of the output current Io depends on the load 3, it is desirable that the external setting value IocpL is a variable value (for example, 1A to 10A) according to the load 3. For example, when driving a bulb lamp, the output current Io is typically greater than when driving a solenoid. In view of this, when driving the bulb lamp, the external setting value IocpL should be set higher when driving the solenoid than when driving the solenoid. When driving the light emitting diode, the output current Io is generally smaller than when driving the solenoid. Therefore, the external setting value IocpL should be set lower when the light emitting diode is driven than when the solenoid is driven.

Now, the load 3 as a target driven by the semiconductor integrated circuit device 1 may be a load that requires a large output current Io to flow instantaneously in its normal operation. For example, upon starting the bulb lamp, a larger rush current flows in the bulb lamp instantaneously than in steady state operation. Depending on the load 3, the output current Io when the load 3 is activated may differ from the output current Io when in steady-state operation by several tens of times.

Therefore, in order to achieve both overcurrent protection and instantaneous current suitable for the load 3, the overcurrent setting value Iocp to which the output current Io is compared must be switched at an appropriate timing (and thus the threshold voltage Vth will be compared with the sense voltage Vs).

Hereinafter, a detailed description will be given of the means (the reference voltage generator 150, the comparison section 160, and the threshold controller 170) for realizing appropriate switching control of the threshold voltage Vth.

< reference Voltage Generator and comparison Unit >

Fig. 9 is a circuit diagram showing a configuration example of the reference voltage generator and the comparison section. The reference voltage generator 150 includes a current source 151 and a resistor 152 (resistance: R152). The comparison section 160 includes a comparator 161.

The current source 151 is connected between the application terminal of the bootstrap voltage VG and the resistor 152, and outputs the second current Iset (more precisely, a variable current equal to the second current Iset) generated by the second current generator 120.

The resistor 152 is connected between the current source 151 and the application terminal (═ external terminal T2) of the output voltage Vo, and is a current/voltage conversion element that generates a reference voltage VIset (═ Iset × R152) from the second current Iset.

The power supply terminal of the comparator 161 is connected to the application terminal of the bootstrap voltage VG. The reference potential terminal of the comparator 161 is connected to the application terminal (external terminal T2) of the output voltage Vo. A non-inverting input terminal (+) of the comparator 161 is connected to the application terminal of the sense voltage Vs. The inverting input terminal (-) of the comparator 161 is connected to the application terminal of the reference voltage VIset. The comparator 161 connected in this way compares the sense voltage Vs with the reference voltage VIset, thereby generating the comparison signal VCMP. The comparison signal VCMP becomes a low level when the sensing voltage Vs is lower than the reference voltage VIset, and becomes a high level when the sensing voltage Vs is higher than the reference voltage VIset.

Here, the resistance R152 of the resistor 152 is switched to one of the first resistance Rdet1 and the second resistance Rdet2(Rdet1> Rdet2) according to the comparison signal VCMP. More specifically, when the comparison signal VCMP is at a low level, the resistance R152 of the resistor 152 is the first resistance Rdet1, and when the comparison signal control signal is at a high level, the resistance R152 of the resistor 152 is the second resistance Rdet 2. By switching and controlling the resistor R152 in this manner, hysteresis characteristics can be given to the comparison unit 160.

< threshold controller >

Fig. 10 is a circuit diagram showing a configuration example of the threshold controller 170. The threshold controller 170 includes a comparator 171, a current source 172, a level shifter 173, an RS flip-flop 174, a discharge controller 175, an NMOSFET176, a capacitor 177, and an external terminal DLY.

The power supply terminal of the comparator 171 is connected to the application terminal of the internal power supply voltage Vreg. The reference voltage terminal of the comparator 171 is connected to the ground terminal GND. A non-inverting input terminal (+) of the comparator 171 is connected to the external terminal DLY (application terminal of the charging voltage Vd). The inverting input terminal (-) of the comparator 171 is connected to the application terminal of the mask period expiration voltage Vdref. The comparator 171 connected in this way compares the charging voltage Vd with the shielding period expiration voltage Vdref, thereby generating the internal signal Sx. When the charging voltage Vd is higher than the shielding period expiration voltage Vdref, the internal signal Sx becomes a high level, and when the charging voltage Vd is lower than the shielding period expiration voltage Vdref, the internal signal Sx becomes a low level.

The current source 172 is connected between the application terminal of the internal supply voltage Vreg and the external terminal DLY, and generates a predetermined charging current Id. Here, whether the current source 172 is operable or not is controlled according to the internal signal Sy (═ corresponding to the comparison signal VCMP after level shifting). More specifically, when the internal signal Sy is at a high level, the current source 172 is in an operating state, and when the internal signal Sy is at a low level, the current source 172 is in a non-operating state.

The level shifter 173 level-shifts the comparison signal VCMP pulse-driven between the bootstrap voltage VG and the output voltage Vo, thereby generating the internal signal Sy pulse-driven between the internal supply voltage Vreg and the ground voltage GND. Therefore, when the comparison signal VCMP is at a high level (═ VG), the internal signal Sy is also at a high level (═ Vreg), and when the comparison signal VCMP is at a low level (═ Vo), the internal signal Sy is also at a low level (═ GND).

The RS flip-flop 174 outputs the threshold control signal S170 from its output terminal (Q) according to the internal signal Sx input to its set terminal (S) and the internal signal Sy input to its reset terminal (R). More specifically, the RS flip-flop 174 sets the threshold control signal S170 to a high level at the rising timing of the internal signal Sx, while resetting the threshold control signal S170 to a low level at the falling timing of the internal signal Sy.

The discharge controller 175 generates the internal signal Sz according to the internal signal Sx. More specifically, the discharge controller 175 raises the internal signal Sz to a high level at the rising timing of the internal signal Sx, and maintains the internal signal Sz at the high level for a predetermined discharge period Tdchg.

The NMOSFET176 is a discharge switching element that realizes an on/off state between the external terminal DLY and the ground terminal GND (between two terminals of the capacitor 177) in accordance with the internal signal Sz. Here, the NMOSFET176 is turned on when the internal signal Sz is at a high level, and is turned off when the internal signal Sz is at a low level.

The capacitor 177 is connected between the external terminal DLY outside the semiconductor integrated circuit device 1 and the ground terminal GND. When the NMOSFET176 is in the off state, if the charging current Id is supplied from the current source 172, the charging voltage Vd of the capacitor 177 rises. On the other hand, when the NMOSFET176 is in the on state, the capacitor 177 is discharged via the NMOSFET176, and thus the charging voltage Vd is lowered.

< overcurrent protection Circuit >

Fig. 11 is a timing chart showing an example of the overcurrent protection operation, in which the external control signal Si, the first current Iref, the second current Iset, the sense voltage Vs, the comparison signal VCMP, the charging voltage Vd, the internal signals Sx to Sz, the threshold control signal S170, the threshold voltage Vth, and the state notification signal So are depicted in this order from the top.

At time t11, when the external control signal Si rises to the high level, the operation of generating the first current Iref starts without delay. However, at time t11, since the turning off of the semiconductor integrated circuit device 1 has not been cancelled and the NMOSFET 10 is kept in the off state, no output current Io flows in the NMOSFET 10. Therefore, the sensing voltage Vs is maintained at 0V.

At time t12, when a predetermined activation delay period Tdly (e.g., 5 μ s) has elapsed from time t11, the turning off of the semiconductor integrated circuit device 1 is cancelled. Accordingly, the NMOSFET 10 is turned on and the output current Io starts to flow, and thus the sense voltage Vs starts to rise. Further, at time t12, the operation of generating the second current Iset and generating the reference voltage VIset (in the figure, VIset ═ VthL) from the second current Iset also starts. Note that at time t12, the sense voltage Vs is lower than the reference voltage VIset, and therefore the comparison signal VCMP becomes low. Accordingly, the threshold control signal S170 becomes a low level, and thus a state is reached in which the internal set value VthH is selected as the threshold voltage Vth.

At time t13, when the sense voltage Vs becomes higher than the reference voltage VIset, the comparison signal VCMP becomes high level. Accordingly, the internal signal Sy becomes high level, and thus the charging voltage Vd starts to rise. Note that at time t13, the charging voltage Vd is lower than the shielding period expiration voltage Vdref, and therefore the internal signal Sx is maintained at a low level. Accordingly, the threshold control signal S170 is kept at the low level, and thus keeps selecting the internal setting value VthH as the threshold voltage Vth. Therefore, even if the sense voltage Vs is higher than the external set value VthL (═ VIset), no overcurrent protection is applied.

At time t14, when the charging voltage Vd becomes higher than the shielding period expiration voltage Vdref, the internal signal Sx becomes a high level. Accordingly, the threshold control signal S170 is set to a high level, and thus the threshold voltage Vth is switched to the external setting value VthL. Therefore, from time t14, overcurrent protection is applied so that the sense voltage Vs does not become higher than the external set value VthL. Further, when the internal signal Sx rises to the high level, the internal signal Sz also becomes the high level and maintains the high level for the predetermined discharging period Tdchg, and thus the charging voltage Vd is discharged to 0V. Here, the discharge period Tdchg is desirably a time (for example, 3 μ s) shorter than the above-described activation delay period Tdly.

Therefore, when the threshold voltage Vth is set to the internal set value VthH, the threshold voltage Vth is switched to the external set value VthL at a point of time when the predetermined mask period Tmask elapses (time t13 to time t14) with the sense voltage Vs kept higher than the reference voltage VIset. Therefore, overcurrent protection suitable for the load 3 can be realized.

On the other hand, although not shown in the drawing, even if the sense voltage Vs is momentarily higher than the reference voltage VIset, if the sense voltage Vs becomes lower than the reference voltage VIset again before the mask period Tmask expires, the threshold voltage Vth remains at the internally set value VthH. Therefore, no accidental overcurrent protection is applied, and thus a transient current at the time of startup can be ensured.

Further, of course, when the threshold voltage Vth is set to the internal set value VthH, if the sense voltage Vs becomes higher than the internal set value VthH, the overcurrent protection is applied without delay at that point of time. Therefore, the NMOSFET 10 can be forcibly turned off upon occurrence of an abnormality such as a short circuit in the load 3, which helps prevent damage to the semiconductor integrated circuit device 1 itself.

Here, the above-described mask period Tmask is a variable value that can be adjusted as necessary by using the capacitor 177 externally connected. More specifically, the larger the capacitance of the capacitor 177, the longer the shielding period Tmask is, and the smaller the capacitance of the capacitor 177, the shorter the shielding period Tmask is. However, as the mask period Tmask becomes longer, overcurrent protection using the external setting value VthL is started with more delay. Therefore, it is desirable to set the mask period Tmask to the minimum necessary length in consideration of the duration of the instantaneous current at the time of startup.

Further, whether or not to provide the mask period Tmask may also be appropriately selected in accordance with the purpose (kind of load 3) of using the semiconductor integrated circuit device 1. For example, when the external terminal DLY is turned on, the mask period Tmask is substantially zero, which corresponds to the case where only the external setting value VthL is supplied. Further, for example, when the external terminal DLY is short-circuited with the ground terminal GND, the mask period Tmask is infinite, which corresponds to the case where only the internal set value VthH is supplied.

At time t15, when the sense voltage Vs becomes lower than the reference voltage VIset, the comparison signal VCMP becomes low level, and thus the internal signal Sy becomes low level. Accordingly, the threshold control signal S170 is reset to a low level, and thus the threshold voltage Vth is switched to the internal set value VthH.

Therefore, when the threshold voltage Vth is set to the external set value VthL, the threshold voltage Vth is switched to the internal set value VthH at a point in time when the sensing voltage Vs becomes lower than the reference voltage VIset. That is, when the overcurrent protection operation using the external setting value VthL is cancelled, the overcurrent protection circuit 71 returns to the initial state at the time of startup.

At time t16, when the external control signal Si falls to the low level, the semiconductor integrated circuit device 1 is turned off, and thus the above-described series of operations ends.

Here, focusing on the state notification signal So, the output detection voltage V80 (see also the broken line in the drawing) corresponding to the detection result of the output current Io is selectively output in a period in which an overcurrent is not detected (a period from the time t14 to a time other than the time t 15). On the other hand, during a period in which an overcurrent is detected (a period from the time t14 to a time t15), the constant voltage V90 corresponding to the abnormality flag is selectively output instead of outputting the detection voltage V80.

Fig. 12 is a flowchart showing an example of the threshold switching operation. When the flow starts, first in step S101, the threshold voltage Vth is set to the internal set value VthH (═ Iref × Rref1) (corresponding to time t12 in fig. 11).

Next, in step S102, it is determined whether the sensing voltage Vs is higher than the reference voltage VIset. When a positive determination is made, the process proceeds to step S103. On the other hand, when negative determination is made, the flow returns to step S102, and the determination in this step (which corresponds to time t12 to time t13 of fig. 11) is repeated.

In step S103, in response to determination "yes" made in step S102, the capacitor 177 starts charging (which corresponds to time t13 of fig. 11).

Next, in step S104, it is determined whether the charging voltage Vd is higher than the shielding period expiration voltage Vdref. When a positive determination is made, the flow proceeds to step S105. On the other hand, when negative determination is made, the flow returns to step S104, and the determination in this step (which corresponds to time t13 to time t14 of fig. 11) is repeated.

In step S105, in response to a negative determination made in step S104, the capacitor 177 is discharged. In step S106, the threshold voltage Vth is switched to the external set value VthL (Iset × Rref 2). Steps S105 and S106 correspond to time t14 of fig. 11.

Next, in step S107, it is determined whether the sense voltage Vs is lower than the reference voltage VIset. When an affirmative determination is made here, the flow returns to step S101, and the threshold voltage Vth is switched to the internal set value VthH (Iref × Rref1) again (corresponding to time t15 of fig. 11). On the other hand, when negative determination is made, the flow returns to step S107, and the determination in this step (which corresponds to time t14 to time t15 of fig. 11) is repeated.

< use example >

Fig. 13 is a schematic diagram showing a first usage example of the overcurrent protection circuit 71. For example, when the load 3 is a bulb lamp, as shown by a solid line in the figure, the output current Io flowing as an instantaneous current at the time of start-up is larger than the output current Io flowing in the steady-state operation. However, by appropriately setting the above-described mask period Tmask, the instantaneous current can be excluded from the detection target, so that overcurrent protection is not applied unintentionally. That is, at the time of start-up, when an excessive instantaneous current flows, the output current Io and the first set value IocpH are compared with each other, and in steady-state operation, the output current Io and the second set value IocpL are compared with each other. Therefore, the output current Io has a drive region indicated by hatching in the figure.

Fig. 14 is a schematic diagram showing a second usage example of the overcurrent protection circuit 71. For example, when the load 3 is a motor, as shown by a solid line in the figure, an output current Io flowing as an instantaneous current when the motor is locked is larger than the output current Io in the steady-state operation. However, by appropriately setting the above-described mask period Tmask, the instantaneous current can be excluded from the detection target, and therefore overcurrent protection is not applied unintentionally. That is, when the motor is locked and an excessive transient current flows, the output current Io and the first set value IocpH are compared with each other, and in steady-state operation, the output current Io and the second set value IocpL are compared with each other. Therefore, the output current Io has a drive region indicated by hatching in the figure.

< effects and advantages >

As described above, in the overcurrent protection circuit 71, as the overcurrent setting value Iocp to be compared with the output current Io, two values, i.e., the first setting value IocpH and the second setting value IocpL are prepared, and further, the predetermined mask period Tmask is provided as a pause period before switching from the first setting value IocpH to the second setting value IocpL.

By adopting such a configuration, both instantaneous current and overcurrent protection suitable for the load 3 can be realized. In particular, during steady-state operation of the load 3, the second setting value IocpL that is sufficiently lower than the first setting value IocpH is compared with the output current Io, which helps prevent a large current that is much larger than the drive current of the load 3 from continuously flowing as the output current Io. This allows the wire harness to be connected to the load 3 to have a diameter smaller than that of the conventional wire harness.

Further, with the overcurrent protection circuit 71, it is not necessary to perform overcurrent protection suitable for the load 3 in the ECU2, and this makes it possible to reduce the burden on the ECU2 (such as continuously monitoring the output current Io), thereby realizing the ECU2 without a microcomputer.

< semiconductor Integrated Circuit device (second embodiment) >

Fig. 15 is a block diagram showing a second embodiment of the semiconductor integrated circuit device 1. The semiconductor integrated circuit device 1 of the present embodiment is based on the first embodiment (fig. 1), but has the above-described components (functional blocks 10 to 90, external terminals T1 to T4, various voltages, currents, signals, and the like) for each channel in order to drive the dual-

channel loads

3X and 3Y, respectively.

The letter "X" is attached to the end of the symbol of the component relating to the driving of the load 3X, and the letter "Y" is attached to the end of the symbol of the component relating to the driving of the load 3Y, but their operation and function are substantially the same as those of the above-described component which is represented by a symbol without the letter "X" or "Y" at the end. For example, the operation and function of the

NMOSFETs

10X and 10Y are substantially the same as those of the NMOSFET 10 described above. This also applies to other components. Accordingly, unless specifically noted otherwise, repeated descriptions of the operation and function of the components will be omitted. In addition, the output current detector 80 and the signal output section 90 are not clearly shown in the drawing, and these functional blocks will be described later.

In the semiconductor integrated circuit device 1 of the present embodiment capable of driving the dual-

channel loads

3X and 3Y, respectively, there are cases where different channels are activated at different timings. Therefore, in order to realize both the instantaneous current and overcurrent protection suitable for the load of each channel, it is necessary to correctly set the above-described mask period Tmask independently of the difference in the start timing.

The simplest configuration for achieving this is obtained by preparing the above-described overcurrent protection circuit 71 (see fig. 4) for each of the two channels, i.e., by providing

overcurrent protection circuits

71X and 71Y in parallel with each other. However, such a configuration requires two external terminals DLY to set the mask period Tmask, which may require changing the package of the semiconductor integrated circuit device 1 or cause an increase in the cost of the semiconductor integrated circuit device 1.

To prevent these disadvantages, the following proposes an overcurrent protection circuit 71 capable of correctly setting the mask period Tmask for each channel without adding another external terminal DLY.

Fig. 16 is a block diagram showing a configuration example of the overcurrent protection circuit 71 having a two-channel configuration. The overcurrent protection circuit 71 of this configuration example includes a first current generator 110, a second current generator 120,

threshold voltage generators

130X and 130Y,

overcurrent detectors

140X and 140Y,

reference voltage generators

150X and 150Y,

comparison sections

160X and 160Y, and a threshold controller 170.

Among the above components, the first current generator 110, the second current generator 120, the threshold voltage generator 130X, the overcurrent detector 140X, the reference voltage generator 150X, the comparison section 160X, and the threshold controller 170 function as the overcurrent protection circuit 71X of the first channel.

On the other hand of the above components, the first current generator 110, the second current generator 120, the threshold voltage generator 130Y, the overcurrent detector 140Y, the reference voltage generator 150Y, the comparison section 160Y, and the threshold controller 170 function as the overcurrent protection circuit 71Y of the second channel.

In this way, in the overcurrent protection circuit 71 of the present configuration example, the first current generator 110, the second current generator 120, and the threshold controller 170 are shared by the first channel and the second channel.

The first current generator 110 generates and outputs a first current Iref to the

threshold voltage generators

130X and 130Y. The first current Iref has a current value fixed inside the semiconductor integrated circuit device. The first current generator 110 is basically configured as shown in fig. 5. As means for outputting the first current Iref to both the

threshold voltage generators

130X and 130Y, a current mirror having current output terminals for two systems, for example, may be used.

The second current generator 120 generates and outputs the second current Iset to the

threshold voltage generators

130X and 130Y. The second current Iset has a current value that is adjustable as required from outside the semiconductor current device 1. The second current generator 120 is configured substantially as shown in fig. 6. As means for outputting the second current Iset to the two

threshold voltage generators

The threshold voltage generator 130X switches whether to set the threshold voltage VthX to an internal setting value VthXH or to an external setting value VthXL (where VthXH > VthXL) according to the threshold control signal S170X. The internal set value VthXH is a fixed value set according to the first current Iref (corresponding to the first set value). On the other hand, the external set value VthXL is a variable value set in accordance with the second current Iset (corresponds to the second set value).

The threshold voltage generator 130Y switches whether to set the threshold voltage VthX to an internal setting value VthXH or to an external setting value VthXL (where VthXH > VthXL) according to the threshold control signal S170X. The internal set value vthhh is a fixed value set according to the first current Iref (corresponding to the third set value). On the other hand, the external setting value vtxyl is a variable value set in accordance with the second current Iset (═ corresponds to a fourth setting value).

The overcurrent detector 140X compares the sensing voltage VsX according to the output current IoX with the threshold voltage VthX, thereby generating an overcurrent protection signal S71X.

The overcurrent detector 140Y compares the sensing voltage VsY according to the output current IoY with the threshold voltage VthY, thereby generating an overcurrent protection signal S71Y.

The reference voltage generator 150X generates a reference voltage VIsetX (═ corresponding to a first reference value) from the second current Iset.

The reference voltage generator 150Y generates a reference voltage VIsetY (═ corresponding to a second reference value) from the second current Iset.

The comparison section 160X compares the sense voltage VsX with the reference voltage VIsetX, thereby generating a comparison signal VCMPX.

The comparison section 160Y compares the sense voltage VsY with the reference voltage VIsetY, thereby generating a comparison signal VCMPY.

The threshold controller 170 monitors both the comparison signals VCMPX and VCMPY, thereby generating threshold control signals S170X and S170Y.

Here, the threshold control signal S170X becomes low level when the internal setting value VthXH should be selected as the threshold voltage VthX, and the threshold control signal S170X becomes high level when the external setting value VthXL should be selected as the threshold voltage VthX.

On the other hand, when the internal setting value vthh should be selected as the threshold voltage VthY, the threshold control signal S170Y becomes low level, and when the external setting value VthY should be selected as the threshold voltage VthY, the threshold control signal S170Y becomes high level.

< threshold controller (first example) >

Fig. 17 is a block diagram showing a first example of the threshold controller 170. The threshold controller 170 of the present example is based on fig. 10 already referred to above, and as means for realizing a dual channel configuration, the threshold controller 170 includes a comparator 171, a current source 172,

level shifters

173X and 173Y, RS flip-

flops

174X and 174Y, a discharge controller 175, an NMOSFET176, a capacitor 177, a charge controller 178, and an external terminal DLY.

The comparator 171 compares the charging voltage Vd inputted to the non-inverting input terminal (+) thereof (which is the charging voltage of the capacitor 177 appearing at the external terminal DLY) with the mask period expiration voltage Vdref inputted to the inverting input terminal (-) thereof, thereby generating the internal signal Sx. When the charging voltage Vd is higher than the shielding period expiration voltage Vdref, the internal signal Sx becomes a high level, and when the charging voltage Vd is lower than the shielding period expiration voltage Vdref, the internal signal Sx becomes a low level. This is similar to what has been described with reference to fig. 10.

The current source 172 generates a charging current Id according to the charging control signal S178. More specifically, the current source 172 outputs the charging current Id when the charging control signal S178 is at a high level, and stops the charging current Id when the charging control signal S178 is at a low level.

The level shifter 173X level-shifts the comparison signal VCMPX, thereby generating the internal signal SyX.

The level shifter 173Y level-shifts the comparison signal VCMPY, thereby generating the internal signal SyY.

The RS flip-flop 174X outputs a threshold control signal S170X from its output terminal (Q) according to the internal signal Sx input to its set terminal (S) and the internal signal SyX input to its reset terminal (R). More specifically, the RS flip-flop 174X sets the threshold control signal S170X to a high level at the rising timing of the internal signal Sx, and resets the threshold control signal S170X to a low level at the falling timing of the internal signal SyX.

The RS flip-flop 174 outputs the threshold control signal S170 from its output terminal (Q) according to the internal signal Sx input to its set terminal (S) and the internal signal Sy input to its reset terminal (R). More specifically, the RS flip-flop 174 sets the threshold control signal S170 to a high level at the rising timing of the internal signal Sx, and resets the threshold control signal S170 to a low level at the falling timing of the internal signal Sy.

The discharge controller 175 generates the internal signal Sz according to the internal signal Sx. More specifically, the discharge controller 175 raises the internal signal Sz to a high level at the rising timing of the internal signal Sx, and maintains the internal signal Sz at the high level for a predetermined discharge period Tdchg. This is similar to what has been described with reference to fig. 10.

The NMOSFET176 is a discharge switching element that realizes an on/off state between the external terminal DLY and the ground terminal GND (between two terminals of the capacitor 177) in accordance with the internal signal Sz. Here, the NMOSFET176 is turned on when the internal signal Sz is at a high level, and is turned off when the internal signal Sz is at a low level. This is also similar to what has been described with reference to fig. 10.

The capacitor 177 is connected between the external terminal DLY outside the semiconductor integrated circuit device 1 and the ground terminal GND. When the NMOSFET176 is in the off state, if the charging current Id is supplied from the current source 172, the charging voltage Vd of the capacitor 177 rises. On the other hand, when the NMOSFET176 is in the on state, the capacitor 177 is discharged via the NMOSFET176, and thus the charging voltage Vd is lowered. This is also similar to what has been described with reference to fig. 10.

The charge controller 178 generates the charge control signal S178 according to the internal signals SyX and SyY (thus comparing the signals VCMPX and VCMPY). At the rising timing of the internal signal SyX or SyY, the charge control signal S178 rises substantially to a high level (i.e., a logic level at the time of charging).

Fig. 18 is a timing chart showing a threshold switching operation of the first example, in which sensing voltages VsX and VsY, comparison signals VCMPX and VCMPY (equivalent to internal signals SyX and SyY), a charging voltage Vd, internal signals Sx and Sz, threshold control signals S170X and S170Y, and threshold voltages VthX and VthY are depicted in this order from the top.

At time t21, when the NMOSFET 10X turns on, the sense voltage VsX begins to rise. However, at time t12, the sensing voltage Vs is lower than the reference voltage VIset, and thus the comparison signal VCMPX (i.e., the internal signal SyX) becomes low. Accordingly, the threshold control signal S170X becomes low level, and thus reaches a state where the internal setting value vtxh is selected as the threshold voltage VthX. Here, at time t21, the NMOSFET 10Y remains off and the sense voltage VsY remains at 0V.

At time t2, when the sense voltage VsX becomes higher than the reference voltage VIsetX, the comparison signal VCMPX (═ internal signal SyX) becomes high level, and the charging voltage Vd starts to rise. It is to be noted that at the time t13, the charging voltage Vd is lower than the shielding period expiration voltage Vdref, and therefore the internal signal Sx is maintained at the low level. Accordingly, the threshold control signal S170 remains at the low level, and thus keeps selecting the internal setting value VthH as the threshold voltage Vth. Therefore, even if the sense voltage Vs is higher than the external set value VthXL (VIsetX), overcurrent protection is not applied. Here, at time t22, the NMOSFET 10Y remains off and the sense voltage VsY remains at 0V.

At time t23, the NMOSFET 10X turns on and the sense voltage VsY begins to rise. Here, at time t23, the sense voltage VsY is lower than the reference voltage VIsetY, and thus the comparison signal VCMPY (═ internal signal SyY) becomes a low level. Accordingly, the threshold control signal S170Y becomes low level, and thus the internal set value vthh is selected as the threshold voltage VthY.

At time t24, when the charging voltage Vd becomes higher than the shielding period expiration voltage Vdref, the internal signal Sx becomes a high level. At time t24, the comparison signal VCMPX (i.e., the internal signal SyX) has become high (i.e., the logic level at the time of reset cancellation). Accordingly, the threshold control signal S170X is set to a high level, and the threshold voltage VthX is switched to the external setting value VthXL. Therefore, from time t24, overcurrent protection starts to be applied so that the sense voltage VsX does not become higher than the external set value VthXL. Further, when the internal signal Sx rises to the high level, the internal signal Sz also becomes the high level and maintains the high level for the predetermined discharging period Tdchg, and thus the charging voltage Vd is discharged to 0V.

That is, focusing on the threshold voltage VthX, when the threshold voltage VthX is set to the internal setting value VthXH, the threshold voltage VthX is switched to the external setting value VthXL at a point of time when a predetermined masking period Tmask elapses (time t22 to time t24) while the sensing voltage Vs remains higher than the reference voltage VIXset. Therefore, overcurrent protection suitable for the load 3X can be realized.

On the other hand, at time t24, the comparison signal VCMPY (i.e., the internal signal SyY) is held at a high level (i.e., a logic level at the time of reset). Therefore, even when the internal signal Sx rises to a high level, the threshold control signal S170Y remains at a low level, and thus the internal set value vthhy is still selected as the threshold voltage VthY.

At time t25, when the sense voltage VsY becomes higher than the reference voltage VIsetY, the comparison signal VCMPY (═ internal signal SyY) becomes high level, and the charging voltage Vd starts rising again. However, since the charging voltage Vd is lower than the shielding period expiration voltage Vdref, the internal signal Sx is maintained at a low level. Accordingly, the threshold control signal S170Y remains at the low level, and thus the internal setting value vthh remains selected as the threshold voltage VthY. Therefore, even if the sensing voltage VsY is higher than the external setting value vthy (═ VIsetY), no overcurrent protection is applied.

In the following description, a period between the rising timing of the comparison signal VCMPX and the rising timing of the comparison signal VCMPY (which is a period between the first channel start timing and the second channel start timing) will be referred to as a shift period Tshift.

At time t26, when the sense voltage VsX becomes lower than the reference voltage VIsetX, the comparison signal VCMPX (═ internal signal SyX) becomes a low level. Accordingly, the threshold control signal S170X is reset to a low level, and thus the threshold voltage VthX is switched to the internal set value VthXH.

That is, focusing on the threshold voltage VthX, when the threshold voltage VthX is set to the external setting value VthXL, the threshold voltage VthX is switched to the internal setting value VthXH at a point of time when the sensing voltage VsX becomes lower than the reference voltage VIsetX.

At time t27, when the charging voltage Vd becomes higher than the shielding period expiration voltage Vdref, the internal signal Sx becomes a high level. Further, at time t27, the comparison signal VCMPY (i.e., the internal signal SyY) has become high (i.e., the logic level at the time of reset cancellation). Accordingly, the threshold control signal S170Y is set to a high level, and the threshold voltage VthY is switched to the external setting value VthXL. Therefore, from time t27, overcurrent protection is applied so that the sensing voltage Vs does not become higher than the external setting value vthy. Further, when the internal signal Sx becomes a high level, the internal signal Sz also becomes a high level and is maintained at the high level for a predetermined discharging period Tdchg, and thus the charging voltage Vd is discharged to 0V.

That is, focusing on the threshold voltage VthY, when the threshold voltage VthY is set to the internal setting value vthhy, the threshold voltage VthY is switched to the external setting value vthhyl at a point of time when a predetermined masking period Tmask elapses (time t25 to time t27) in a case where the sensing voltage Vs remains higher than the reference voltage VIYset. Therefore, overcurrent protection suitable for the load 3Y can be realized.

Here, at time t27, the comparison signal VCMPX (i.e., the internal signal SyX) has already fallen to a low level (i.e., a logic level at the time of reset). Therefore, even when the internal signal Sx rises to a high level, the threshold control signal S170X remains at a low level, and thus the internal setting value vtxh is still selected as the threshold voltage VthX.

At time t28, when the sense voltage VsY becomes lower than the reference voltage VIsetY, the comparison signal VCMPY (═ internal signal SyY) becomes a low level. Accordingly, the threshold control signal S170Y is reset to a low level, and thus the threshold voltage VthY is switched to the internal set value vthhy.

That is, focusing on the threshold voltage VthY, when the threshold voltage VthY is set to the external setting value VthY, the threshold voltage VthY is switched to the internal setting value vthhy at a point of time when the sensing voltage VsY becomes lower than the reference voltage VIsetY.

As is clear from the above-described series of threshold switching operations, with the threshold controller 170 of the present example, the mask period Tmask (from the time t22 to the time t23, and from the time t25 to the time t27) can be correctly set for each channel without adding another external terminal DLY.

The above description is given with reference to the present drawing by taking as an example the case of Tshift > Tmask; in contrast, in the case where Tshift ≦ Tmask, a problem may occur in the series of threshold switching operations described above. Hereinafter, a detailed description will be given of these problems.

Fig. 19 is a timing chart showing a problem encountered in the first example observed in the case of Tshift < Tmask, in which the behaviors of the comparison signals VCMPX and VCMPY, the internal signal Sx, and the threshold control signals S170X and S170YT are shown in this order from the top.

In the example shown in the figure, where Tshift < tmax, after the comparison signal VCMPX rises to the high level at time t31, the comparison signal VCMOY rises to the high level at time t32 before the masking period tmax elapses.

Therefore, when the mask period Tmask elapses from the time t31 and the internal signal Sx rises to the high level at the time t33, not only the comparison signal VCMPX but also the comparison signal VCMPY has become the high level. Therefore, at the time t33, the threshold control signals S170X and S170Y simultaneously become high level.

In this case, particularly, the preceding channel that starts first has no problem, but for the subsequent channel that starts after the preceding channel, the mask period Tmask becomes short due to the length of the shift period Tshift, which may make it difficult to secure the instantaneous current. Thereafter, a second example of the threshold controller 170 capable of solving this problem will be presented.

< threshold controller (second example) >

Fig. 20 is a block diagram showing a second example of the threshold controller 170. The threshold controller 170 of the present example is based on the above-described first example (fig. 17), and is characterized in that the discharge controller 175 accepts not only the input of the internal signal Sx but also the input of the internal signals SyX and SyY (equivalent to the comparison signals VCMPX and VCMPY) and the threshold control signals S170X and S170Y. The following description will focus on the configuration and operation of the discharge controller 175.

Fig. 21 is a block diagram showing a configuration example of the discharge controller 175. The discharge controller 175 shown in the present drawing includes a NOR operation unit NOR1, AND operation units AND1 to AND3, an OR operation unit OR1, inverters INV1 to INV3, a pulse generator PG1, a resistor R1, AND a capacitor C1.

The NOR operation unit NOR1 performs a NOR operation on the threshold control signals S170X and S170Y, thereby generating the logic signal SA. Therefore, when both the threshold control signals S170X and S170Y are at a low level, the logic signal SA becomes a high level, and when at least one of the threshold control signals S170X and S170Y is at a high level, the logic signal SA becomes a low level.

The AND operation unit AND1 performs an AND operation on the internal signals SyX AND SyY, thereby generating a logic signal SB. Therefore, when both the internal signals SyX and SyY are high level, the logic signal SB becomes high level, and when at least one of the internal signals SyX and SyY is low level, the logic signal SB becomes low level.

The AND operation unit AND2 performs an AND operation on the logic signals SA AND SB, thereby generating a logic signal SC. Therefore, when both the logic signals SA and SB are at a high level, the logic signal SC becomes a high level, and when at least one of the logic signals SA and SB is at a low level, the logic signal SC becomes a low level.

The inverter INV1 inverts the logic of the logic signal SC, thereby generating an inverted logic signal SCB.

The resistor R1 and the capacitor C1 generate a logic signal SD having an integrated waveform obtained by inverting the logic signal SCB passivated with a predetermined time constant τ (═ R × C).

The inverters INV2 and INV3 compare the logic signal SD with a predetermined threshold value (a logic inversion threshold value of the inverters INV2 and INV 3), thereby generating a logic signal SE having a rectangular waveform.

The AND operation unit AND3 performs an AND operation on the logic signals SC AND SE, thereby generating a logic signal SF. Therefore, when both the logic signals SC and SE are at the high level, the logic signal SF becomes the high level, and when at least one of the logic signals SC and SE is at the low level, the logic signal SF becomes the low level.

At the rising timing of the internal signal Sx, the pulse generator PG1 generates a one-shot pulse having a predetermined pulse width (corresponding to the discharge period Tdchg) in the logic signal SG.

The OR operation unit OR1 performs an OR operation on the logic signals SF and SG, thereby generating the internal signal Sz. Therefore, when both the logic signals SF and SG are at the low level, the internal signal Sz becomes the low level, and when at least one of the logic signals SF and SG is at the high level, the internal signal Sz becomes the high level.

Fig. 22 is a timing chart showing the threshold switching operation of the second example, in which comparison signals VCMPX and VCMPY (equivalent to internal signals SyX and SyY), logic signals SA to SG, an internal signal Sz, a charging voltage Vd, an internal signal Sx, and threshold control signals S170X and S170Y observed in the case of Tshift < Tmask are shown in this order from the top.

In the example shown in the figure, after the comparison signal VCMPX rises to the high level at time t41, the comparison signal VCMPY rises to the high level at time t42 before the mask period Tmask elapses. That is, at time t42, the charging voltage Vd has not reached the shielding period expiration voltage Vdref, and the internal signal Sx has not risen to the high level.

Here, focusing on the internal operation of the discharge controller 175, at time t42, both the threshold control signals S170X and S170Y are at the low level, and thus the logic signal SA is at the high level. At time t42, the comparison signals VCMPX and VCMPY (and therefore the internal signals SyX and SyY) are both at a high level, so the logic signal SB rises to a high level. Therefore, the logic signal SC rises to a high level, and the logic signal SD starts to fall with the time constant τ. However, at time t42, the logic signal SD is higher than the logic inversion threshold of the inverter INV2, and thus the logic signal SE remains at the high level.

Therefore, at time t42, since both the logic signals SC and SE become high level, the logic signal SF rises to high level, and therefore the internal signal Sz rises to high level. Accordingly, the charging voltage Vd is discharged.

In this way, after one of the comparison signals VCMPX and VCMPY rises to the high level and the charging operation of the capacitor 177 starts, the other of the comparison signals VCMPX and VCMPY rises to the high level before the charging voltage Vd becomes higher than the shielding period expiration voltage Vdref, the capacitor 177 is discharged, and thus the counting operation of the shielding period Tmask is reset.

Then, at time t43, when the logic signal SD becomes lower than the logic inversion threshold of the inverter INV2, the logic signal SE falls to the low level. Accordingly, the logic signal SF falls to the low level, and therefore the internal signal Sz falls to the low level, the above-described discharging operation stops and the charging voltage Vd starts rising again.

Here, the high level period of the logic signal SF (from time t42 to time t43) corresponds to the discharge period Tdchg2 of the charging voltage Vd. The discharge period Tdchg2 can be arbitrarily set according to the time constant τ of the resistor R1 and the capacitor C1, and may be set, for example, equal to the above-described discharge period Tdchg (e.g., 3 μ s).

Next, at time t24, when the charging voltage Vd becomes higher than the shielding period expiration voltage Vdref, the internal signal Sx becomes a high level. At this point in time, not only the comparison signal VCMPX but also the comparison signal VCMPY have become high level. Therefore, at the time t44, the threshold control signals S170X and S170Y simultaneously become high level.

With the above threshold switching operation, the length of the mask period becomes equal to the originally set length (═ Tmask) with respect to the threshold control signal S170Y of the subsequent channel. On the other hand, with respect to the threshold control signal S170X of the previous channel, the length of the mask period becomes longer than the originally set length (tmax + α).

Here, at time t44, when the internal signal Sx rises to a high level, since a one-shot pulse having a predetermined pulse width (═ Tdchg) is generated in the logic signal SG, the internal signal Sz becomes a high level, and the charging voltage Vd is discharged.

Further, at time t44, when both the threshold control signals S170X and S170Y rise to the high level, the logic signal SA falls to the low level, and the logic signal SC falls to the low level. Therefore, the logic signal SD starts to rise with the time constant τ, and the logic signal SE rises to the high level at a point of time when the logic signal SD becomes higher than the logic inversion threshold of the inverter INV 2. However, at this point in time, the logic signal SC has become low level, and thus the logic signal SF remains at low level.

As described above, with the threshold controller 170 of the present example, even in the case where Tshift < tmax, the masking period of the subsequent channel is not reduced, and therefore, there is no risk that it becomes difficult to secure the instantaneous current.

Here, the above description is given with reference to the present drawing by taking the case of Tshift < Tmask as an example; in contrast, in the case where Tshift ≈ Tmask (or Tshift ≈ Tmas), even with the second example, there is a risk of unexpected failure. This problem will be described in detail below.

Fig. 23 is a timing chart showing a problem that may be had by the second example, which sequentially shows, from the top, comparison signals VCMPX and VCMPY (equivalent to internal signals SyX and SyY), a charging voltage Vd, an internal signal Sx, and threshold control signals S170X and S170Y, which are observed in the case where Tshift is Tmask.

In the example shown in the figure, since Tshift ═ Tmask, after the comparison signal VCMPX rises to the high level at time t51, the comparison signal VCMPY rises to the high level at time t52 while the masking period Tmask elapses.

Here, if the above-described discharging operation (see time t42 in fig. 22) is not in time, the charging voltage Vd becomes higher than the shielding period expiration voltage Vdref and the internal signal Sx rises to a high level, and the threshold control signals S170X and S170Y simultaneously become a high level. Therefore, the shield channel of the subsequent channel becomes zero, and thus it becomes impossible to secure the instantaneous current. Thereafter, a third example of the threshold controller 170 capable of solving this problem will be presented.

< threshold controller (third example) >

Fig. 24 is a block diagram showing a third example of the threshold controller 170. The threshold controller 170 of the present example is based on the above-described second example (fig. 20), and is characterized by being provided with

delay sections

179X and 179Y. Therefore, the same components as in the second example will be given the same reference numerals as in fig. 20, and therefore, the repetitive description will be omitted, and the following description will focus on the

delay portions

179X and 179Y.

The delay unit 179X delays the internal signal SyX (corresponding to the comparison signal VCMPX), thereby generating a delayed signal SyXd. Here, the delay section 179X gives a delay only to the rising timing of the delayed signal SyXd, and does not give a delay to the falling timing of the delayed signal SyXd. More specifically, the delay signal SyXd rises to the high level with a delay of a delay time td (e.g., 3 μ s) after the internal signal SyX rises to the high level, and falls to the low level at the same time as the internal signal SyX falls to the low level.

The delay section 179Y gives a delay to the internal signal SyY (equivalent to the comparison signal VCMPY), thereby generating a delayed signal SyYd. Here, the delay section 179Y gives a delay only to the rising timing of the delayed signal SyYd, and does not give a delay to the falling timing of the delayed signal SyYd. More specifically, the delay signal SyYd rises to the high level with a delay of the delay time td after the internal signal SyY rises to the high level, and falls to the low level at the same time as the internal signal SyY falls to the low level.

As a result of additionally providing the

delay sections

179X and 179Y, the delay signals SyXd and SyYd are input to the RS flip-

flops

174X and 174Y, respectively, instead of the internal signals SyX and SyY.

Fig. 25 is a timing chart showing the threshold switching operation of the third example, in which the comparison signal VCMPX (equivalent to the internal signal SyX), the delay signal SyXd, the comparison signal VCMPY (equivalent to the internal signal SyY), the delay signal SyYd, the internal signal Sz, the charging voltage Vd, the internal signal Sx, and the threshold control signals S170X and S170Y observed in the case where Tshift is Tmask are shown in this order from the top.

In the example shown in the figure, where Tshift ═ Tmask, after the comparison signal VCMPX (═ SyX) rises to the high level at time t61, the comparison signal VCMPY (═ SyY) rises to the high level at time t62 while the masking period Tmask elapses. On the other hand, the delay signals SyXd and SyYd have both risen to the high level when the predetermined delay time td has elapsed from the time t61 and the time t62, respectively.

Here, at time t62, when the charging voltage Vd becomes higher than the shielding period expiration voltage Vdref, the internal signal Sx becomes a high level. At this time, the delay signal SyXd has risen high (logic level of reset cancel). Therefore, the threshold control signal S170X is set to the high level at time t 62.

On the other hand, at time t26, the delayed signal SyYd remains at the low level (i.e., the logic level at the time of reset). Therefore, even when the internal signal Sx rises to the high level, the threshold control signal S170Y remains reset to the low level.

Further, when the internal signal Sx rises to a high level, since the internal signal Sz becomes a high level and is maintained at a high level for a predetermined discharging period Tdchg, the charging voltage Vd is discharged to 0V. Then, when the internal signal Sz falls to the low level at time t63, the above-described discharging operation is stopped, and the charging voltage Vd starts rising again.

At time t64, when the charging voltage Vd becomes higher than the shielding period expiration voltage Vdref, the internal signal Sx rises to the high level again. At this time, the delay signal SyYd has already risen to a high level (i.e., a logic level at the time of reset cancellation). Therefore, the threshold control signal S170Y is set to the high level at time t 64.

Further, when the internal signal Sx rises to a high level, since the internal signal Sz becomes a high level and is maintained at a high level for a predetermined discharging period Tdchg, the charging voltage Vd is discharged to 0V. Then, when the internal signal Sz falls to the low level at time t63, the above-described discharging operation is stopped. Here, at this point in time, since the charging operation has been completed for two channels, the charging voltage Vd does not start rising again.

Then, at time t66, when the comparison signal VCMPX (═ internal signal SyX) falls to the low level, the delay signal SyXd also falls to the low level without delay. Therefore, the threshold control signal S170X is reset to the low level.

Likewise, at time t67, when the comparison signal VCMPY (i.e., the internal signal SyY) falls to the low level, the delay signal SyYd also falls to the low level without delay. Therefore, the threshold control signal S170Y is reset to the low level.

In this way, in the threshold controller 170 of the present example, the threshold control signals S170X and S170Y are generated by using the internal signal Sx and the delay signals SyXd and SyYd. Therefore, when Tshift ≦ Tmask, the charging voltage Vd is never discharged at the rising timing of the comparison signals VCMPX and VCMPY before the delay signals SyXd and SyYd each rise to the high level.

Therefore, even under the critical condition of Tshift ═ Tmask, the threshold control signals S170X and S170Y do not simultaneously become high level, and therefore the correct mask period Tmask can be set for each channel.

< flow chart >

Fig. 26 is a flowchart showing an example of the two-channel threshold value switching operation. When the flow starts, first, in step S201, the threshold voltage Vth of the already activated channel is set to an internal set value Vth × (here, "# is at least" X "or" Y ", which also applies to the following description) (corresponding to time t21 and time t23 in fig. 18).

Next, in step S202, it is determined whether one of the comparison signals VCMPX and VCMPY is at a high level (i.e., whether only one channel is activated). When the affirmative determination is made, the flow proceeds to step S203 (corresponding to time t22 in fig. 18). On the other hand, when a negative determination is made, the flow proceeds to step S208.

In step S203, in response to an affirmative determination being made in step S202, the capacitor 177 starts charging (which corresponds to time t22 in fig. 18).

Next, in step S204, it is determined whether the charging voltage Vd is higher than the shielding period expiration voltage Vdref. When the affirmative determination is made, the flow proceeds to step S205 (corresponding to time t24 in fig. 18). On the other hand, when negative determination is made, the flow returns to step S204, and the determination in this step is repeated (corresponding to time t22 to time t24 of fig. 18).

In step S205, in response to a negative determination made in step S204, the capacitor 177 is discharged. In step S206, the threshold voltage Vth of the already activated channel is switched to the external set value Vth L. Steps S205 and S206 correspond to time t24 in fig. 18.

Next, in step S207, it is determined whether the sensing voltage Vs of the activated channel is lower than the reference voltage VIset.

When an affirmative determination is made here, the flow returns to step S201, and the threshold voltage Vth is switched to the internal set value Vth H again (corresponding to time t26 of fig. 18). On the other hand, when negative determination is made, the flow returns to step S207, and the determination in this step is repeated (corresponding to time t24 to time t26 of fig. 18).

On the other hand, in step S208, in response to a negative determination in step S202, it is determined whether both of the comparison signals VCMPX and VCMPY are at a high level (i.e., whether both channels have been activated). When the affirmative determination is made, the flow proceeds to step S209 (corresponding to time t23 in fig. 18, time t42 in fig. 22, or time t62 in fig. 25). On the other hand, when negative determination is made, neither channel is activated, so the flow returns to step S201.

In step S209, in response to a negative determination made in step S208, it is determined whether one of the threshold signals S170X and S170Y is at a high level (i.e., whether the threshold voltage Vth of the previous channel has switched to the external set value Vth × L). When an affirmative determination is made here, the flow proceeds to step S203, and in steps S203 to S207, the threshold switching operation of the subsequent channel is performed (corresponding to time t25 to time t28 in fig. 18). On the other hand, when a negative determination is made, the flow proceeds to step S210.

In step S210, in response to a negative determination made in step S209, it is determined whether both the threshold signals S170X and S170Y are at the low level (i.e., whether the start timing of the subsequent channel has come before the mask period Tmask of the preceding channel has elapsed.

In step S211, in response to an affirmative determination being made in step S210, the capacitor 177 is discharged, and then charging is started again (corresponding to time t42 to time t43 in fig. 22).

Next, in step S212, it is determined whether the charging voltage Vd is higher than the shielding period expiration voltage Vdref. When the affirmative determination is made, the flow proceeds to step S213 (corresponding to time t44 in fig. 22). On the other hand, when negative determination is made, the flow returns to step S212, and the determination in this step is repeated (corresponding to time t43 to time t44 in fig. 22).

In step S213, in response to a negative determination made in step S212, the capacitor 177 is discharged. In step S214, the threshold voltages VthX and vthy of the two channels are switched to the external setting values VthXL and vthy. Steps S205 and S206 correspond to time t44 of fig. 22.

Next, in step S215, it is determined whether the sensing voltages VsX and VsY of the two channels are lower than the reference voltages VIsetX and VIsetY. When a positive determination is made, the flow returns to step S201, enters a state of waiting for the next start-up on the other hand, when a negative determination is made, the flow returns to step S215, and the determination in this step is repeated.

< multiplexer >

Fig. 27 is a block diagram showing an example of the double channelization of the semiconductor integrated circuit device 1 in which a multiplexer is introduced as the output stage of the state notification signal So and has been described So far. In the semiconductor integrated circuit device 1 of this configuration example, the output

current detectors

80X and 80Y, the

signal output sections

90X and 90Y, the multiplexer 100, and the external terminal T5 are integrated.

The output current detector 80X generates a sense current IsX 'from the output current IoX, and outputs the generated sense current IsX' to the signal output section 90X.

The output current detector 80Y generates a sense current IsY 'from the output current IoY, and outputs the generated sense current IsY' to the signal output section 90Y.

The signal output section 90X includes a selector 91X that selectively outputs one of a sense current IsX' (corresponding to the detection result of the output current IoX) and a fixed voltage V90 (corresponding to the abnormality flag) as the first state notification signal SoX based on an output selection signal S2X input from the control logic section 40X. Here, the selector 91X selectively outputs the sense current IsX' as the first state notification signal SoX when the output selection signal S2X is at a logic level (e.g., a low level) at which no abnormality is detected, and outputs the fixed voltage V90 as the first state notification signal SoX when the output selection signal S2X is at a logic level (e.g., a high level) at which an abnormality is detected.

The signal output section 90Y includes a selector 91Y that selectively outputs one of the sense current IsY' (corresponding to the detection result of the output current IoY) and the fixed voltage V90 (corresponding to the abnormality flag) as the second state notification signal SoY based on the output selection signal S2Y input from the control logic section 40Y. Here, the selector 91Y selectively outputs the sense current IsY' as the second state notification signal SoY when the output selection signal S2Y is at a logic level (e.g., a low level) at which no abnormality is detected, and outputs the fixed voltage V90 as the second state notification signal SoY when the output selection signal S2Y is at a logic level (e.g., a high level) at which an abnormality is detected.

The multiplexer 100 selectively outputs one of a first state notification signal SoX (═ sense current IsX 'or fixed voltage V90) and a second state notification signal SoY (═ sense current IsY' or fixed voltage V90) to the external terminal T4 according to an output selection signal SEL input to the external terminal T5.

In a case where the sense current IsX ' is selectively output to the external terminal T4, an output detection voltage V80X (═ IsX ' × R4) obtained by current-voltage converting the sense current IsX ' by the external sense resistor 4 is transmitted to the ECU2 as a state notification signal So. Here, the larger the output current IoX, the higher the output detection voltage V80X becomes, and the smaller the output current IoX, the lower the output detection voltage V80X becomes.

In a case where the sense current IsY ' is selectively output to the external terminal T4, an output detection voltage V80X (═ IsY ' × R4) obtained by current-voltage converting the sense current IsY ' by the external sense resistor 4 is transmitted to the ECU2 as a state notification signal So. Here, the larger the output current IoY, the higher the output detection voltage V80Y becomes, and the smaller the output current IoY, the lower the output detection voltage V80Y becomes.

On the other hand, in a case where the fixed voltage V90 is selectively output to the external terminal T4, the fixed voltage V90 is transmitted to the ECU2 as the state notification signal So. Here, the fixed voltage V90 may be set to a voltage value higher than the upper limit value of the output detection voltages V80X and V80Y.

Introducing the operation of the multiplexer 100 as described above, the detection result of the output currents IoX and IoY of any channel and the abnormality flag can be monitored from the outside.

< application to vehicle >

Fig. 28 is an external view of a vehicle, showing an example of the configuration of the vehicle. The vehicle X of the present configuration example has mounted therein a battery (not shown in the figure) and several electronic devices X11 to X18 that operate with electric power supplied from the battery. Here, for convenience of explanation, the mounting positions of the electronic devices X11 to X18 in the drawing may be different from the actual positions.

The electronic device X11 is an engine control unit that executes engine-related control (injection control, electronic throttle control, idle speed control, oxygen sensor heater control, auto cruise control, and the like).

The electronic device 12 is a lamp control unit that performs on/off control of a HID (high intensity discharge lamp) or a DRL (daytime running lamp).

The electronic device X13 is a transmission control unit that performs transmission-related control.

The electronic device X14 is a main body control unit that executes control relating to movement of the vehicle X (ABS (anti-lock brake system) control, EPS (electric power steering) control, electronic suspension control, and the like).

The electronic device X15 is a security control unit that performs drive control of a vehicle lock, an antitheft alarm, and the like.

The electronic device X16 is an electronic device incorporated in the vehicle X at the factory shipping stage as a standard device or a factory installation option, such as a wiper, a power door mirror, a power window, a damper (shock absorber), a power sunroof, a power seat, and the like.

The electronic device X17 is an electronic device optionally mounted on the vehicle X as a user option, such as an in-vehicle a/V (audio/video) apparatus, a car navigation system, ETC (electronic toll collection system), or the like.

The electronic devices 18 are electronic devices each including a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, or a battery cooling fan.

It is to be noted that the above-described semiconductor integrated circuit device 1, ECU2, and load 3 can be incorporated in any of the electronic apparatuses X11 to X18.

< other modified example >

In the above-described embodiments, the description has been given by taking the vehicle-mounted high-side switch IC as an example, but the application object of the invention disclosed herein is not limited thereto; for example, the invention disclosed herein can be widely applied not only to other vehicle-mounted IPDs (vehicle-mounted low-side switch ICs, vehicle-mounted power supply ICs, etc.), but also to semiconductor integrated circuit devices for applications other than automobiles.

Also, in addition to the above-described embodiments, various modifications can be added to various technical features disclosed herein without departing from the spirit of technical innovation. In other words, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive, and the technical scope of the present invention is indicated not by the above description of the embodiments but by the claims, and covers the claims and all modifications within the scope equivalent to the meaning of the claims.

Industrial applicability

The invention disclosed herein is applicable to, for example, onboard IPDs.

List of reference numerals

1 semiconductor integrated circuit device

2 ECU

3, 3X, 3Y load

4 external sensing resistor

10,10X,10Y NMOSFET

20,20X,20Y output current monitor

21,21′ NMOSFET

22 sensing resistor

30,30X,30Y grid controller

31 gate driver

32 oscillator

33 charge pump

34 clamping device

35 NMOSFET

40,40X,40Y control logic

50,50X,50Y signal input part

60,60X,60Y internal power supply

70,70X,70Y abnormality protecting section

71,71X,71Y overcurrent protection circuit

72 open circuit protection circuit

73 temperature protection circuit

74 step-down protection circuit

80,80X,80Y output current detector

90,90X,90Y signal output part

91,91X,91Y selector

100 multiplexer

110 first current generator

111 operational amplifier

112 NMOSFET

113 resistor

120 second current generator

121 operational amplifier

122 NMOSFET

123 resistor

130,130X,130Y threshold voltage generator

131 current source

132 resistor

133 current mirror

140,140X,140 overcurrent detector

141 comparator

150,150X,150Y reference voltage generator

151 current source

152 resistor

160,160X,160 comparison part

161 comparator

170 threshold controller

171 comparator

172 current source

173,173X 173Y level shifter

174,174X,174Y RS trigger

175 discharge controller

176 NMOSFET

177 capacitor

178 charge controller

179X,179Y delay unit

NOR1 NOR operation unit

AND 1-AND 3 AND operation unit

OR1 OR operation unit

INV 1-NV 3 inverter

PG1 pulse generator

R1 resistor

C1 capacitor

T1 to T5, SET, DLY external terminals

X vehicle

X11-X18 electronic device

Claims

1. An overcurrent protection circuit, comprising:

an overcurrent detection unit that compares a sensing signal corresponding to the current to be monitored with an overcurrent detection threshold and generates an overcurrent protection signal;

a comparison unit that compares the sensing signal with a reference value corresponding to the overcurrent detection threshold and generates a comparison signal;

and a threshold control unit that disables the overcurrent detection threshold until the comparison signal is set, and enables the overcurrent detection threshold after the comparison signal is set.

2. The overcurrent protection circuit of claim 1,

the overcurrent detection threshold is set to be valid, and the current to be monitored is allowed to be larger than the overcurrent detection threshold.

3. The overcurrent protection circuit of claim 1,

the threshold control unit sets the overcurrent detection threshold to be valid at a time point when a predetermined masking period has elapsed after the comparison signal is set.

4. The overcurrent protection circuit of claim 3,

the masking period is a variable value.

5. The overcurrent protection circuit of any one of claims 1 to 4,

the overcurrent detection threshold is a variable value.

6. The overcurrent protection circuit of any one of claims 1 to 4,

the threshold control unit is configured to enable a second overcurrent detection threshold higher than the overcurrent detection threshold when the overcurrent detection threshold is disabled, and the overcurrent detection unit is configured to compare the sense signal with the second overcurrent detection threshold to generate the overcurrent protection signal.

7. The overcurrent protection circuit of claim 6,

the threshold control unit switches the activation/deactivation of each of the overcurrent detection threshold and the second overcurrent detection threshold based on the comparison signal.

8. A semiconductor integrated circuit device is characterized in that,

the semiconductor integrated circuit device integrates a power transistor for turning on/off a current path through which an output current flows, an output current monitoring unit for generating a sense signal corresponding to the output current, a gate control unit for generating a drive signal for the power transistor based on a control signal, and the overcurrent protection circuit according to any one of claims 1 to 7 for monitoring the sense signal to generate an overcurrent protection signal,

the gate control unit has a function of forcibly turning off the power transistor in response to the overcurrent protection signal.

9. The semiconductor integrated circuit device according to claim 8,

the semiconductor integrated circuit device further includes a signal output unit that selectively outputs one of the detection result of the output current and the abnormality flag to the outside of the device as a state notification signal.

10. An electronic device, comprising:

the semiconductor integrated circuit device according to claim 8 or 9; and

and a load connected to the semiconductor integrated circuit device.

11. The electronic device of claim 10,

the load is a bulb, a relay coil, a solenoid, a light emitting diode, or a motor.

12. A vehicle, characterized in that,

an electronic device as claimed in claim 10 or 11.