CN110767667B - Image sensor structure and forming method - Google Patents
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H01L27/144—Devices controlled by radiation
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- H01L27/144—Devices controlled by radiation
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- H01L27/144—Devices controlled by radiation
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- H01L27/14643—Photodiode arrays; MOS imagers
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Abstract
The invention discloses an image sensor structure and a forming method, the image sensor structure comprises: the pixel unit array, the peripheral circuit located in the periphery of the pixel unit array, surround the composite shielding structure located between pixel unit array and peripheral circuit, the composite shielding structure has heat shielding structure and light shielding structure; the light shielding structure is provided with a metal ring for isolating light emitted by the peripheral circuit and preventing heat and light from being transmitted to the pixel unit array. The invention can avoid the problems of imaging quality deterioration and distortion caused by the luminescence and the heating of the peripheral circuit of the image sensor.
Description
Technical Field
The present invention relates to the field of image sensor technology, and more particularly, to an image sensor structure and a method for forming the same capable of preventing edge response anomalies.
Background
The image sensor refers to a device that converts an optical signal into an electrical signal, and a large-scale commercial image sensor chip includes two major types of Charge Coupled Device (CCD) and Complementary Metal Oxide Semiconductor (CMOS) image sensor chips. Compared with the traditional CCD sensor, the CMOS image sensor has the characteristics of low power consumption, low cost, compatibility with the CMOS process and the like, so that the CMOS image sensor is more and more widely applied. At present, the CMOS image sensor is not only used in the consumer electronics fields of a micro digital camera (DSC), a mobile phone camera, a video camera, a Digital Single Lens Reflex (DSLR) and the like, but also widely applied in the fields of automotive electronics, monitoring, biotechnology, medicine and the like.
Referring to fig. 1-2, fig. 1 is a layout diagram of a conventional CMOS image sensor chip, and fig. 2 is a cross-sectional view along a-B in fig. 1. As shown in fig. 1, the center of the chip is a densely arranged pixel unit array, and the pixel unit array is responsible for converting optical signals into electrical signals; various peripheral control and readout circuits are arranged around the pixel unit array, and comprise peripheral circuits such as a column-level readout circuit and a row selection control circuit. During the operation of these peripheral circuits, it is possible for recombination of electron and hole pairs to occur, the recombination process being accompanied by the generation of photons, i.e. the phenomenon of the circuit emitting light. The heat generation phenomenon is caused by that when current passes through a conductor or a semiconductor in a circuit, a part of heat is released, and the temperature of a chip is increased. The phenomena of light emission and heat generation of these peripheral circuits directly affect the performance of the image sensor. The heat generated by the circuit is transferred to the pixel unit array, so that the dark current of the pixel unit is increased; the light emission of the circuit may cause abnormal increase of the edge output signal of the pixel unit array, resulting in distortion of the image.
As shown in fig. 2, since the silicon substrate 10 is a good thermal conductor and the dielectric layer 12 is a poor thermal conductor, there is an order of magnitude difference in thermal resistance between the two. Therefore, heat generated by circuit heating propagates mainly in the silicon substrate 10, eventually reaches the photodiode 11 region for photoelectric conversion in the pixel cell region, causing dark current rise and performance degradation of the pixel cell; since the silicon substrate 10 and the dielectric layer 12 are both transparent, photons generated by circuit light emission propagate through the silicon substrate 10 and the dielectric layer 12 at the same time and finally reach the photodiode 11 region, thereby causing abnormal increase of photodiode output values at the edge of the pixel unit array region and image distortion.
Therefore, it is desirable to provide a new technique capable of preventing the peripheral circuit from emitting light and heat to cause an abnormal edge response of the image sensor.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art, and providing an image sensor structure and a forming method thereof, which avoid the problems of degradation and distortion of image quality caused by light emission and heat generation of peripheral circuits of the image sensor.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an image sensor structure comprising: the pixel unit array, the peripheral circuit located in the periphery of the pixel unit array, surround the composite shielding structure set between the pixel unit array and the peripheral circuit, the composite shielding structure is set with a heat shielding structure and a light shielding structure; the heat shielding structure is provided with a cavity, a fluid cooling medium is communicated in the cavity and used for taking away heat emitted by the peripheral circuit, and the light shielding structure is provided with a metal ring and used for isolating light emitted by the peripheral circuit so as to prevent the heat and the light from being transmitted to the pixel unit array.
Furthermore, the cavity comprises an annular first cavity and an annular second cavity which are vertically arranged in parallel, one end of the first cavity is connected with one end of the second cavity through an annular third cavity which is horizontally arranged, the other end of the first cavity is provided with a fluid cooling medium inlet, and the other end of the second cavity is provided with a fluid cooling medium outlet; the metal ring is suspended between the first cavity and the second cavity, and a supporting structure is arranged between the metal ring and the third cavity.
Further, the first cavity is located at a side close to the peripheral circuit.
Furthermore, the pixel unit array and the peripheral circuit are arranged on a device silicon wafer, the device silicon wafer comprises a silicon substrate and a back dielectric layer arranged on the surface of the front side of the silicon substrate, and a slide glass is connected to the surface of the front side of the back dielectric layer; the first cavity and the second cavity are communicated with the silicon substrate and the back medium layer, one end of the first cavity and one end of the second cavity are arranged on the back surface of the silicon substrate to form the inlet and the outlet respectively, the other end of the first cavity and the other end of the second cavity are connected and arranged with the third cavity on the front surface of the back medium layer respectively, and the third cavity and the other end of the first cavity and the other end of the second cavity are sealed by the slide glass.
Furthermore, the metal ring is of a composite structure and comprises a metal groove, a contact hole and at least one metal interconnection layer metal, wherein the metal groove, the contact hole and the at least one metal interconnection layer metal are sequentially connected and arranged in the silicon substrate.
Furthermore, a protrusion formed by extending the subsequent dielectric layer material is arranged between the upper cavity wall and the lower cavity wall of the third cavity, and the protrusion abuts against the slide glass to form the supporting structure.
Further, the fluid cooling medium is air or a cooling liquid.
Further, the pixel cell array includes: the pixel cell array includes: the photodiode and the control transistor are arranged on the front surface of the silicon substrate, and the pixel unit metal interconnection layer is arranged in the back medium layer; the peripheral circuit includes: the peripheral circuit transistor is arranged on the front surface of the silicon substrate, and the peripheral circuit metal interconnection layer is arranged in the back dielectric layer.
Further, the peripheral circuit includes a column-level readout circuit and a row selection control circuit.
An image sensor structure forming method, comprising the steps of:
providing a device silicon wafer with a silicon substrate and a back dielectric layer, forming a photodiode for light sensing in a pixel unit array, a control transistor on the front surface of the silicon substrate, forming a peripheral circuit transistor in a peripheral circuit outside the pixel unit array, and forming a metal interconnection layer in the back dielectric layer on the front surface of the silicon substrate; forming an annular contact hole surrounding the pixel unit array and one to more layers of annular metal interconnection layer metals between the pixel unit array and the peripheral circuit through layout design while forming the metal interconnection layer;
forming an annular first groove and an annular second groove which vertically penetrate through the back medium layer and surround the pixel unit array in parallel in the back medium layer on two sides of the annular contact hole and the annular metal interconnection layer metal;
forming a horizontal annular third groove surrounding the pixel unit array on the front surface of the back medium layer between the first groove and the second groove, so that two ends of the third groove are respectively connected with the upper end of the first groove and the upper end of the second groove; forming a third groove on the dielectric layer, wherein a protruding support structure is formed in the third groove by protecting the partial surface of the front surface of the back dielectric layer while the third groove is formed;
providing a carrier, and bonding the device silicon wafer and the carrier after the device silicon wafer is inverted to enable the third groove and the upper ends of the first groove and the second groove to be simultaneously covered by the carrier; wherein a third cavity is formed by the closed third trench;
thinning the silicon substrate;
forming annular fourth, fifth and sixth trenches which vertically penetrate through the silicon substrate and surround the pixel unit array in parallel in the thinned silicon substrate, respectively connecting the lower end of the fourth and sixth trenches with the lower end of the second and first trenches, and simultaneously connecting the lower end of the fifth trench with the lower end of the annular contact hole; wherein a first cavity is formed by the fourth trench and the second trench, a second cavity is formed by the sixth trench and the first trench, and a size of the fifth trench is larger than a size of the fourth trench and the sixth trench;
and filling metal in the fourth groove, and keeping the upper end of the third groove and the upper end of the fifth groove in an opening state.
According to the technical scheme, the composite shielding structure comprising the metal ring, the vertical cavity (the first cavity and the second cavity) and the horizontal cavity (the third cavity) is inserted between the pixel unit area and the peripheral circuit area, the metal ring comprises the metal filling isolation structure in the silicon substrate, the contact hole in the back-end dielectric layer and the metal interconnection layer metal from top to bottom, and the light emitting shielding of the circuit can be realized by using the light-tight characteristic of the metal because all the metal materials are metal materials. The vertical cavity and the horizontal cavity are connected with each other, so that air or cooling liquid is introduced into the cavity, circulation in the vertical cavity and the horizontal cavity can be realized, heat emitted by a peripheral circuit can be taken away, and influence of circuit heating on a pixel unit is avoided.
Drawings
Fig. 1 is a layout diagram of a conventional CMOS image sensor chip.
Fig. 2 is a schematic sectional view taken along a-B in fig. 1.
Fig. 3 is a layout diagram of an image sensor chip according to a preferred embodiment of the invention.
Fig. 4 is a schematic cross-sectional view taken along line C-D of fig. 3.
Fig. 5 is a schematic cross-sectional view taken along the line E-F in fig. 3.
Fig. 6-13 are schematic process steps of a method for forming an image sensor structure according to a preferred embodiment of the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following description of the present invention, please refer to fig. 3-5, fig. 3 is a layout diagram of an image sensor chip according to a preferred embodiment of the present invention, fig. 4 is a cross-sectional view taken along the position C-D in fig. 3, and fig. 5 is a cross-sectional view taken along the position E-F in fig. 3. As shown in fig. 3-5, an image sensor structure of the present invention can be built on a device silicon wafer and a carrier wafer bonded up and down. The image sensor chip structure comprises a pixel unit area and a peripheral circuit area surrounding the periphery of the pixel unit area. The pixel unit area is provided with a pixel unit array, and the peripheral circuit area is provided with peripheral circuits such as a column-level readout circuit and a row selection control circuit. A composite shielding structure 37 is arranged between the pixel unit area (pixel unit array) and the peripheral circuit area (peripheral circuit), and the composite shielding structure 37 is arranged around the outer side of the pixel unit array.
Please refer to fig. 3-4. The composite shielding structure 37 is provided with the heat shielding structure 32 and the light shielding structure 26. The heat shielding structure 32 has cavities 30, 27 and 34, and a fluid cooling medium is filled in the cavities 30, 27 and 34 for removing heat emitted from the peripheral circuit. The fluid cooling medium may be air or a cooling liquid. The light shielding structure 26 is provided with metal rings 25, 24, 23 and 22 for isolating light emitted from the peripheral circuit. The composite shielding structure 37 can shield light and heat generated by peripheral circuits, and prevent the heat and light from being transmitted to the pixel unit array, so that the pixel unit array is affected by light emission and heat generation.
Please refer to fig. 4. The pixel unit array and the peripheral circuit are arranged on a device silicon wafer, the device silicon wafer comprises a silicon substrate 20 and a back dielectric layer 32 arranged on the front surface of the silicon substrate 20, and a slide glass is connected with the front surface of the back dielectric layer 32.
The pixel cell array may include: a photodiode 21 and a control transistor 36 provided on the front surface of the silicon substrate 20, and a pixel unit metal interconnection layer 35 provided in the back dielectric layer 32. The peripheral circuit may include: a peripheral circuit transistor 31 provided on the front surface of the silicon substrate 20, and a peripheral circuit metal interconnection layer 33 provided in the back dielectric layer 32.
The cavities 30, 27 and 34 include a first cavity 30 and a second cavity 27 arranged vertically side by side, and a third cavity 34 arranged horizontally. The first cavity 30 and the second cavity 27 are vertically disposed and each form a ring structure around the pixel cell array. The first cavity 30 is located at a side close to the peripheral circuit. One end (lower end shown) of the first cavity 30 is connected with one end (lower end shown) of the second cavity 27 through a horizontally arranged annular third cavity 34; the other end (shown as the upper end) of the first cavity 30 is provided with a fluid cooling medium inlet 29, and the other end (shown as the upper end) of the second cavity 27 is provided with a fluid cooling medium outlet 28 (although the positions of the inlet 29 and the outlet 28 may be interchanged).
The first cavity 30 and the second cavity 27 are disposed through the silicon substrate 20 and the back dielectric layer 32. The first cavity 30 and the second cavity 27 show the upper ends thereof forming a fluid cooling medium inlet 29 and an outlet 28, respectively, on the back surface of the silicon substrate 20; the illustrated lower ends of the first and second cavities 30 and 27 are connected to a third cavity 34, respectively, which is horizontally disposed on the front surface of the back dielectric layer 32. The third cavity 34 and the lower ends of the first cavity 30 and the second cavity 27 connected with the two ends of the third cavity 34 are sealed by bonding the slide glass with the front surface of the back dielectric layer 32.
Metal rings 25, 24, 23 and 22 are suspended between first cavity 30 and second cavity 27 and above third cavity 34.
The composite shielding structure 37 shown in fig. 4 is formed by using vertical cavities (the first cavity 30 and the second cavity 27) and horizontal cavities (the third cavity 34), so that the metal rings 25, 24, 23 and 22 are suspended. In order to support the metal rings 25, 24, 23 and 22, a support structure 38 is provided between the metal rings 25, 24, 23 and 22 and the third cavity 34 for mechanically supporting the cavity structure. As shown in fig. 3, support structures 38 are provided at the turning positions of the composite shielding structure 37 (e.g., at the four corners of the composite shielding structure 37 of each chip) to support the metal rings 25, 24, 23 and 22. The cross-sectional view of the support structure 38 is shown in fig. 5, and compared with the structure in fig. 4, the horizontal cavity is not provided at the support position in fig. 5, so that the metal rings 25, 24, 23 and 22 can be supported by the underlying portion of the back dielectric layer 32 material, preventing the collapse of the entire metallic light-shielding structure 26.
Please refer to fig. 5 and fig. 3. As an alternative embodiment, the support structure 38 may be formed using the material of the back dielectric layer 32. For example, a protrusion formed by a portion of the back dielectric layer 32 extending downward may be provided between the upper and lower walls of the third cavity 34, and the lower end of the protrusion abuts against the surface of the slide to form a support structure 38, thereby lifting the back dielectric layer 32 material and the metal rings 25, 24, 23, and 22 above the third cavity 34.
Further, the metal rings 25, 24, 23, and 22 may be a composite structure. For example, metal rings 25, 24, 23, and 22 may include, from top to bottom, a metal trench 25 disposed in silicon substrate 20, a contact hole 24 disposed in subsequent dielectric layer 32, and one or more layers of metal interconnect layer 23 (formed using a conventional metal interconnect layer structure). When multiple layers of metal interconnection layer metals 23 are used, the layers of metal interconnection layer metals 23 can be connected by using the through holes 22. Since all the metal rings 25, 24, 23 and 22 of the composite structure are made of metal, the light emission of the circuit can be shielded by using the characteristic of metal light-tightness.
As shown in fig. 3, unlike the conventional contact hole and via hole, the contact hole 24 and via hole 22 of the present invention have a ring structure in a plane to effectively shield the circuit from light emission. As shown in fig. 4, the vertical cavity (the first cavity 30 and the second cavity 27) and the horizontal cavity (the third cavity 34) are connected to each other, so that air or cooling liquid is introduced into the cavities 30, 34, and 27, and circulation in the vertical cavity and the horizontal cavity can be realized, so that heat emitted by peripheral circuits can be taken away, and the influence of circuit heating on pixel units can be avoided.
A method for forming an image sensor structure according to the present invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 6-13, fig. 6-13 are schematic process steps of a method for forming an image sensor structure according to a preferred embodiment of the invention. As shown in fig. 6-13, an image sensor chip structure forming method of the present invention can be used to fabricate the image sensor chip structure such as those shown in fig. 3-5, and can include the following steps:
first, as shown in fig. 6, a conventional CMOS image sensor manufacturing process may be used to form a photodiode 21 for sensing light in a pixel cell array, a control transistor 36, a peripheral circuit transistor 31 in a peripheral circuit outside the pixel cell array on the front surface of a silicon substrate 20 of a device silicon wafer, and metal interconnection layers 35, 33 including the pixel cell metal interconnection layer 35 and the peripheral circuit metal interconnection layer 33 in a subsequent dielectric layer 32 on the front surface of the silicon substrate 20.
At the same time of forming the metal interconnection layers 35, 33, a ring-shaped contact hole 24 surrounding the pixel cell array and a two-layer ring-shaped metal interconnection layer metal 23 of the illustration can be formed between the pixel cell array and the peripheral circuit by layout design. Wherein, the two layers of ring-shaped metal interconnection layer metals 23 can be connected by using a ring-shaped through hole 22.
Next, as shown in fig. 7, by using photolithography and etching processes, a partial vertical cavity is formed in the subsequent dielectric layer 32 on both sides of the ring-shaped contact hole 24 and the ring-shaped metal interconnection layer metal 23. The vertical cavity includes a ring-shaped first trench 40 and a ring-shaped second trench 39 formed in parallel on both sides of the ring-shaped metal interconnection layer metal 23. The first trench 40 and the second trench 39 vertically penetrate through the back dielectric layer 32 and are disposed around the pixel cell array. The first trench 40 and the second trench 39 may be arranged at equal intervals on both sides of the metal interconnection layer 23 by layout design.
Subsequently, as shown in fig. 8 (wherein the left diagram in fig. 8 shows the feature of the composite shielding structure 37, and the right diagram shows the feature of the support structure 38, the same applies below), a horizontal ring-shaped third trench 41 pattern surrounding the pixel unit array is formed on the front surface of the post-channel dielectric layer 32 between the first trench 40 and the second trench 39 by photolithography and etching, so that both ends of the third trench 41 are aligned with the upper end of the first trench 40 and the upper end of the second trench 39, respectively, to achieve communication therebetween. The raised support structures 38 are formed in the third trenches 41 by protecting the surface of the front portion of the back dielectric layer 32 while forming the third trenches 41. For example, during processing, the subsequent dielectric layer 32 is protected with photoresist at all locations where the support structures 38 are formed, so that no horizontal cavity 34 pattern is formed in the subsequent dielectric layer 32 at the locations where the support structures 38 are formed.
Then, as shown in fig. 9, the device silicon wafer is inverted and bonded to the carrier wafer, so that the third trench 41 on the device silicon wafer, the upper end of the first trench 40 and the upper end of the second trench 39 which are communicated with the third trench 41 are simultaneously covered by the surface of the carrier wafer, and a horizontal third cavity 34 structure formed by the closed third trench 41 shown in the right figure is formed.
Next, as shown in fig. 10, the backside of the silicon substrate 20 on the device silicon wafer may be thinned using a conventional backside illumination process.
Subsequently, as shown in fig. 11, a ring-shaped fourth trench 42, a fifth trench 43, and a sixth trench 44 that vertically penetrate the silicon substrate 20 and surround the pixel cell array may be formed in parallel in the thinned silicon substrate 20 by photolithography and etching. Wherein the lower end of the fourth groove 42 and the lower end of the sixth groove 44 are connected to the lower end of the second groove 39 and the lower end of the first groove 40, respectively; meanwhile, the lower end of the fifth trench 43 is aligned and connected to the lower end of the annular contact hole 24. Thus, the first cavity 30 is formed by the connection of the fourth groove 42 and the second groove 39, and the second cavity 27 is formed by the connection of the sixth groove 44 and the first groove 40. Also, the size (width) of the fifth trench 43 is made much larger than the size (width) of the fourth trench 42 and the sixth trench 44.
Then, as shown in fig. 12, the fifth trench 43 is filled with metal 45 using a metal deposition procedure. During filling, the fifth trench 43 with a larger width can be filled with the metal 45, and the fourth trench 42 and the sixth trench 44 with a smaller width cannot be filled with the metal 45 due to the limitation of the deposition process capability, which keeps the upper end of the fourth trench 42 and the upper end of the sixth trench 44 in an open state. After the fifth trench 43 is filled with the metal 45, the metal trench 25 is formed.
Finally, as shown in fig. 13, an etching back or chemical mechanical polishing process may be used to remove the excess metal 45 on the back surface of the silicon substrate 20, exposing the upper end of the fourth trench 42 and the upper end of the sixth trench 44, thereby forming the inlet 29 of the first cavity 30 and the outlet 28 of the second cavity 27.
Thus, the first cavity 30, the third cavity 34 and the second cavity 27 are connected to form a heat shield structure 32 for heat insulation. A light shielding structure 26 for shielding light is composed of the annular metal trench 25 together with the annular contact hole 24 and the two-layer annular metal interconnection layer metal 23 and the via hole 22.
The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. An image sensor structure, comprising: the pixel unit array, the peripheral circuit located in the periphery of the pixel unit array, surround the composite shielding structure set between the pixel unit array and the peripheral circuit, the composite shielding structure is set with a heat shielding structure and a light shielding structure; the heat shielding structure is provided with a cavity, a fluid cooling medium is communicated in the cavity and used for taking away heat emitted by the peripheral circuit, and the light shielding structure is provided with a metal ring and used for isolating light emitted by the peripheral circuit so as to prevent the heat and the light from being transmitted to the pixel unit array.
2. The image sensor structure as claimed in claim 1, wherein the cavities include a first annular cavity and a second annular cavity, which are vertically arranged in parallel, one end of the first cavity is connected to one end of the second cavity through a third annular cavity, which is horizontally arranged, the other end of the first cavity is provided with a fluid cooling medium inlet, and the other end of the second cavity is provided with a fluid cooling medium outlet; the metal ring is suspended between the first cavity and the second cavity, and a supporting structure is arranged between the metal ring and the third cavity.
3. The image sensor structure of claim 2, wherein the first cavity is located on a side proximate to the peripheral circuitry.
4. The image sensor structure of claim 2, wherein the pixel cell array and the peripheral circuit are disposed on a device silicon wafer, the device silicon wafer comprises a silicon substrate and a back dielectric layer disposed on a front surface of the silicon substrate, and a carrier sheet is disposed on a front surface of the back dielectric layer; the first cavity and the second cavity are communicated with the silicon substrate and the back medium layer, one end of the first cavity and one end of the second cavity are arranged on the back surface of the silicon substrate to form the inlet and the outlet respectively, the other end of the first cavity and the other end of the second cavity are connected and arranged with the third cavity on the front surface of the back medium layer respectively, and the third cavity and the other end of the first cavity and the other end of the second cavity are sealed by the slide glass.
5. The image sensor structure of claim 4, wherein the metal ring is a composite structure comprising a metal trench disposed in the silicon substrate, a contact hole disposed in the subsequent dielectric layer, and one or more metal interconnect layers sequentially connected.
6. The image sensor structure of claim 4, wherein a protrusion formed by extending the back dielectric layer is disposed between the upper and lower cavity walls of the third cavity, and the protrusion abuts against the carrier to form the supporting structure.
7. The image sensor structure of claim 1, wherein the fluid cooling medium is air or a cooling liquid.
8. The image sensor structure of claim 4, wherein the array of pixel cells comprises: the photodiode and the control transistor are arranged on the front surface of the silicon substrate, and the pixel unit metal interconnection layer is arranged in the back medium layer; the peripheral circuit includes: the peripheral circuit transistor is arranged on the front surface of the silicon substrate, and the peripheral circuit metal interconnection layer is arranged in the back dielectric layer.
9. The image sensor structure of claim 1, wherein the peripheral circuitry comprises column level readout circuitry and row select control circuitry.
10. An image sensor structure forming method, characterized by comprising the steps of:
providing a device silicon wafer with a silicon substrate and a back dielectric layer, forming a photodiode for sensitization in a pixel unit array on the front surface of the silicon substrate, forming a control transistor, forming a peripheral circuit transistor in a peripheral circuit outside the pixel unit array, and forming a metal interconnection layer in the back dielectric layer on the surface of the front surface of the silicon substrate; forming an annular contact hole surrounding the pixel unit array and one to more layers of metal of the annular metal interconnection layer between the pixel unit array and the peripheral circuit through layout design while forming the metal interconnection layer;
forming an annular first groove and an annular second groove which vertically penetrate through the back medium layer and surround the pixel unit array in parallel in the back medium layer on two sides of the annular contact hole and the annular metal interconnection layer metal;
forming a horizontal annular third groove surrounding the pixel unit array on the front surface of the back medium layer between the first groove and the second groove, so that two ends of the third groove are respectively connected with the upper end of the first groove and the upper end of the second groove; forming a third groove on the dielectric layer, wherein a protruding support structure is formed in the third groove by protecting the partial surface of the front surface of the back dielectric layer while the third groove is formed;
providing a carrier, and bonding the device silicon wafer and the carrier after the device silicon wafer is inverted to enable the third groove and the upper ends of the first groove and the second groove to be simultaneously covered by the carrier; wherein a third cavity is formed by the closed third groove;
thinning the silicon substrate;
forming annular fourth, fifth and sixth trenches in parallel in the thinned silicon substrate, wherein the annular fourth, fifth and sixth trenches vertically penetrate through the silicon substrate and surround the pixel unit array, and respectively connecting the lower ends of the fourth and sixth trenches with the lower ends of the second and first trenches, and simultaneously connecting the lower end of the fifth trench with the lower end of the annular contact hole; wherein a first cavity is formed by the fourth trench and the second trench, a second cavity is formed by the sixth trench and the first trench, and the size of the fifth trench is larger than the size of the fourth trench and the sixth trench;
and filling metal in the fourth groove, and keeping the upper end of the third groove and the upper end of the fifth groove in an opening state.
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