CN110765718A - Binary memristor circuit simulator - Google Patents
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a binary memristor circuit simulator, which is formed by an operational amplifier, a current transmitter, a multiplier, a resistor and a capacitor and adapts to different working frequency ranges by selecting integral circuit parameters. The adoption of the inverting hysteresis circuit can realize the holding and switching of two resistance states of the memristor, and can change the proportion of a high resistance state and a low resistance state by adjusting the parameters of the inverting addition circuit. The circuit simulator can be directly connected with actual circuit components and parts, and is suitable for research and application of a memristor in the field of digital logic.
Description
Technical Field
The invention relates to a memristor circuit simulator, in particular to a binary memristor circuit simulator, which is suitable for the research field of memristors and memristor application circuits.
Background
Professor zeitz speculates that a fourth basic circuit element memristor exists based on the mathematical relationship between the missing flux and the charge. The nonlinear two-terminal circuit element is a nonlinear two-terminal circuit element and can be applied to the fields of nonvolatile memories, digital logic, neural networks, analog circuit design and the like. The high and low resistance states of the memristor can be regarded as '0' and '1' of digital logic, and the memristor shows attractive application prospects in the fields of digital logic circuits, nonvolatile memories and the like by virtue of unique binary characteristics. In 2008, the HP laboratory first presented the physical implementation of memristors using nanostructured passive elements. However, the production technology problem of the existing nanoscale memristor still exists, and the low-cost and high-performance memristor is still expected. The memristor circuit simulator has the advantages of easiness in implementation, low cost, controllable characteristics and the like, and can be widely applied to research of memristors and memristor application circuits. Most memristive circuit simulators are based on linear drift mathematical models and do not have non-volatile characteristics. Therefore, it is necessary to design a nonvolatile binary memristor circuit emulator.
Disclosure of Invention
The invention aims to solve the problems in the prior art, and the binary memristor circuit simulator applicable to the field of digital logic is constructed by adopting an active device and a basic circuit element.
The invention discloses a binary memristor circuit simulator which comprises a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a first current transmitter U7, a second current transmitter U8 and a first resistor R8inA second resistor Rsb1A third resistor Rsb2A fourth resistor Rsb3A fifth resistor Rsb4A sixth resistor RiA seventh resistor RmAn eighth resistor R and a ninth resistor R1A tenth resistor R2An eleventh resistor R3And a twelfth resistor R4A thirteenth resistor RwA fourteenth resistor RzCapacitor CiAnd a multiplier U9; the multiplier U9 has model number AD 633;
the output end of the first current transmitter U7 is connected with the non-inverting input end of the first operational amplifier U1 and serves as one end of the binary memristor circuit simulator; the inverting input terminal and the output terminal of the first operational amplifier U1 are connected in parallelA second resistor Rsb1One terminal of (1), a second resistor Rsb1And the other end of the first resistor and a fourth resistor Rsb3Is connected to the non-inverting input of the third operational amplifier U3, and a fourth resistor Rsb3The output end of the second current transmitter U8 is connected with the non-inverting input end of the second operational amplifier U2 and is used as the other end of the binary memristor circuit simulator, the inverting input end of the second operational amplifier U2 is connected with the output end and is connected with the third resistor R in parallelsb2One terminal of (1), a third resistor Rsb2The other end of (1) and a fifth resistor Rsb4Is connected to the inverting input of the third operational amplifier U3, and a fifth resistor Rsb4And the other end of the third resistor, the output end of the third operational amplifier U3, and a sixth resistor RiOne terminal of (1), x of multiplier U91Pin connection, sixth resistor RiAnother terminal of (1) and a capacitor CiIs connected to the inverting input of the fourth operational amplifier U4, the non-inverting input of the fourth operational amplifier U4 is grounded, and a capacitor C is connected to the inverting input of the fourth operational amplifier U4iThe other end of the first resistor is connected with the output end of a fourth operational amplifier U4 and connected in parallel with a ninth resistor R1To one end of, a ninth resistor R1Is connected to the inverting input terminal of the fifth operational amplifier U5, the non-inverting input terminal of the fifth operational amplifier U5 is connected to one end of the eighth resistor R and the seventh resistor RmIs connected to a seventh resistor RmThe other end of the eighth resistor R is connected with the output end of the fifth operational amplifier U5 and connected in parallel with the tenth resistor R2One terminal of (1), a tenth resistor R2And the other end of the resistor and an eleventh resistor R3One end of (1), a twelfth resistor R4Is connected to the inverting input terminal of the sixth operational amplifier U6, and an eleventh resistor R3Is connected to the other end with a voltage VsThe non-inverting input terminal of the sixth operational amplifier U6 is grounded, and the twelfth resistor R4And the other end of the same is connected to the output terminal of the sixth operational amplifier U6 and is connected in parallel to y of the multiplier U92Foot, x of multiplier U92Foot, y1Pin and fourteenth resistor RzIs connected to ground, a fourteenth resistor RzAnd the other end of (1) and a thirteenth resistor RwIs connected in parallel with the z pin of the multiplier U9, and a thirteenth resistor RwThe other end of the first resistor is connected with a pin w of the multiplier U9 and a non-inverting input end of a second current conveyor U8, and an inverting input end of the second current conveyor U8 is connected with the first resistor RinIs connected to the inverting input terminal of the first current conveyor U7 and the first resistor RinThe other end of the first current conveyor U7 is connected, and the non-inverting input of the first current conveyor U7 is grounded.
The two ends of the binary memristor circuit simulator are connected with a voltage follower consisting of an operational amplifier and used for isolating a rear circuit, two paths of voltages are output through a differential circuit to achieve acquisition of voltage at a model end of the memristor circuit, an output signal of the differential circuit is input into an inverting integration circuit, a signal output after inverting integration is carried out on the voltage end is proportional to magnetic flux, the signal output by the inverting hysteresis comparison circuit and an inverting addition circuit is proportional to a memristive value, wherein an operational amplifier of the inverting hysteresis comparison circuit is powered by a double power supply, and two stable voltages correspond to two resistance states of the memristor. The voltage value output by the differential circuit and the signal output by the addition circuit can output a voltage signal which is in direct proportion to the current flowing through the memristor after passing through the multiplier, and finally the voltage signal is converted into a current signal by adopting the two current transmitters, and the currents at two ends of the memristor are ensured to be equal.
Has the advantages that: the invention adopts a binary memristor circuit simulator consisting of an operational amplifier, a current transmitter, a multiplier, a resistor and a capacitor, and adapts to different working frequency ranges by selecting parameters of an integrating circuit. The adoption of the inverting hysteresis circuit can realize the holding and switching of two resistance states of the memristor, and can change the proportion of a high resistance state and a low resistance state by adjusting the parameters of the inverting addition circuit. The circuit simulator can be directly connected with actual circuit components and parts, and is suitable for research and application of a memristor in the field of digital logic.
Drawings
FIG. 1 is a schematic diagram of a binary memristor circuit emulator.
Detailed Description
The invention is further described with reference to the accompanying drawings in which:
the memristor circuit simulator comprises an operational amplifier, a current follower, a multiplier, resistors and capacitors, wherein the model of the operational amplifier is TL084, the model of a current transmitter is AD844, the model of the multiplier is AD633, A, B in the figure is two ends of the memristor circuit simulator, v is voltage at two ends of a memristor, i is current flowing through the memristor, the operational amplifier U1 and the operational amplifier U2 in a ① part form the voltage follower with an isolation effect, and the operational amplifier U3 and the four resistors R in a ② part form the voltage follower with the isolation effectsb1、Rsb2、Rsb3、Rsb4Form a differential circuit in which Rsb1＝Rsb2＝Rsb3＝Rsb4Then, the output signal of the differential circuit is:
vsub＝vA-vB＝v (1)
at this time the output voltage of the differential circuit is equal to the voltage across the memristor model, since the memristive value is related to its historical state, the operational amplifier U4 and the resistance R in section ③iCapacitor CiAn inverse integration circuit is formed, and the output signal of the differential circuit is obtained after inverse integration:
operational amplifier U5, resistor R in section ④m、R、R1An inverting hysteresis comparison circuit is formed, wherein the operational amplifier U5 adopts dual power supplies to supply power, and the positive voltage is VCCNegative voltage is VEEIn which V isEE＝-VCCThe upper and lower threshold voltages of the inverting hysteresis circuit are:
the output of the inverting hysteresis circuit depends on the inverting integration circuit, and the memristor is guaranteed to have only two stable resistance states. When v isx>vTHThe output of the inverting hysteresis circuit is VEE(ii) a When v isx<vTLThe output of the time-reversal hysteresis circuitIs a VCC(ii) a When v isTL≤vx≤vTHIn time, the output remains unchanged. The holding and switching of the resistance state of the memristor are realized through the inverting hysteresis circuit. An operational amplifier U6 and a resistor R are connected after the inverting hysteresis circuit2、R3、R4The output voltage of the adder circuit is as follows:
wherein a ═ R4/R2，b＝R3/R2，Vs＝VCCVoltage aVEE+bVsAnd aVCC+bVsRespectively corresponding to the low and high memristive values of the memristor, so that the resistance R is changed2、R3、R4The ratio of the high resistance state and the low resistance state of the memristor is adjusted by the resistance value of the memristor.
The multiplication circuit is composed of a multiplier U9 and a resistor R in the ⑤ partw、RzA resistor R for outputting a voltage signal proportional to the memristor currentw、RzThe output signal v of the multiplication circuit can be obtained according to the AD633 chip data manual by adjusting the coefficient of the multiplication circuitwComprises the following steps:
the two current transmitters U7 and U8 of section ⑥ are used to convert the output of the multiplier into current and ensure that the circuit can be connected to the ground, as can be derived from ohm's Law and the AD844 chip data Manual:
vw＝Rini (6)
the equivalent memristor value and the voltage v of the binary memristor circuit simulator can be obtained according to the formula (5) and the formula (6)GThe relationship of (a) to (b) is as follows:
G＝kGvG(7)
wherein k isG＝-(Rw+Rz)/(10RwRin) Can be obtained by modifying the resistance Rw、RzAnd RinTo adjust the equivalent memristive value of the binary-type memristor circuit emulator.
According to analysis, the state equation of the binary memristor circuit simulator is obtained as follows:
Claims (6)
1. a binary type memristor circuit emulator characterized in that: comprises a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a first current transmitter U7, a second current transmitter U8, a first resistor RinA second resistor Rsb1A third resistor Rsb2A fourth resistor Rsb3A fifth resistor Rsb4A sixth resistor RiA seventh resistor RmAn eighth resistor R and a ninth resistor R1A tenth resistor R2An eleventh resistor R3And a twelfth resistor R4A thirteenth resistor RwA fourteenth resistor RzCapacitor CiAnd a multiplier U9; the multiplier U9 has model number AD 633;
the output end of the first current transmitter U7 is connected with the non-inverting input end of the first operational amplifier U1 and serves as one end of the binary memristor circuit simulator; the inverting input end and the output end of the first operational amplifier U1 are connected in parallel with a second resistor Rsb1One terminal of (1), a second resistor Rsb1And the other end of the first resistor and a fourth resistor Rsb3Is connected to the non-inverting input of the third operational amplifier U3, and a fourth resistor Rsb3The other end of the first current transmitter U8 is grounded, and the output end of the second current transmitter U8 is connected with the non-inverting input end of the second operational amplifier U2 and used as a binary memristor circuit simulationThe other end of the device, the inverting input end and the output end of a second operational amplifier U2 are connected in parallel with a third resistor Rsb2One terminal of (1), a third resistor Rsb2The other end of (1) and a fifth resistor Rsb4Is connected to the inverting input of the third operational amplifier U3, and a fifth resistor Rsb4And the other end of the third resistor, the output end of the third operational amplifier U3, and a sixth resistor RiOne terminal of (1), x of multiplier U91Pin connection, sixth resistor RiAnother terminal of (1) and a capacitor CiIs connected to the inverting input of the fourth operational amplifier U4, the non-inverting input of the fourth operational amplifier U4 is grounded, and a capacitor C is connected to the non-inverting input of the fourth operational amplifier U4iThe other end of the first resistor is connected with the output end of a fourth operational amplifier U4 and connected in parallel with a ninth resistor R1To one end of, a ninth resistor R1Is connected to the inverting input terminal of a fifth operational amplifier U5, the non-inverting input terminal of the fifth operational amplifier U5 is connected to one end of an eighth resistor R and a seventh resistor RmIs connected to a seventh resistor RmThe other end of the eighth resistor R is connected with the output end of the fifth operational amplifier U5 and connected in parallel with the tenth resistor R2One terminal of (1), a tenth resistor R2And the other end of the resistor and an eleventh resistor R3One end of (1), a twelfth resistor R4Is connected to the inverting input terminal of the sixth operational amplifier U6, and an eleventh resistor R3Is connected to the other end with a voltage VsThe non-inverting input terminal of the sixth operational amplifier U6 is grounded, and the twelfth resistor R4And the other end of the same is connected to the output terminal of the sixth operational amplifier U6 and is connected in parallel to y of the multiplier U92Foot, x of multiplier U92Foot, y1Pin and fourteenth resistor RzIs connected to ground, a fourteenth resistor RzAnd the other end of (1) and a thirteenth resistor RwIs connected in parallel with the z pin of the multiplier U9, and a thirteenth resistor RwThe other end of the first resistor is connected with a pin w of the multiplier U9 and a non-inverting input end of a second current conveyor U8, and an inverting input end of the second current conveyor U8 is connected with the first resistor RinIs connected to the inverting input terminal of the first current conveyor U7 and the first resistor RinThe other end of the first current conveyor U7 is connected, and the non-inverting input of the first current conveyor U7 is grounded.
2. The binary-type memristor circuit emulator of claim 1, wherein: a third operational amplifier U3, a second resistor Rsb1A third resistor Rsb2A fourth resistor Rsb3A fifth resistor Rsb4Form a differential circuit in which Rsb1＝Rsb2＝Rsb3＝Rsb4The output signal of the differential circuit is: v. ofsubV, where v is the voltage across the binary memristor circuit emulator.
3. The binary-type memristor circuit emulator of claim 1, wherein: a fourth operational amplifier U4 and a sixth resistor RiCapacitor CiAn inverse integration circuit is formed, and the output signal of the differential circuit is obtained after inverse integration:
4. The binary-type memristor circuit emulator of claim 1, wherein: a fifth operational amplifier U5 and a seventh resistor RmAn eighth resistor R and a ninth resistor R1An inverting hysteresis comparison circuit is formed, wherein the fifth operational amplifier U5 is powered by dual power sources, the positive voltage is VCC, the negative voltage is VEE, wherein VEE is-VCC, and the upper and lower threshold voltages of the inverting hysteresis circuit are:
the output of the inverting hysteresis circuit depends on the inverting integration circuit, so that the memristor is ensured to have only two stable resistance states; when v isx>vTHThe output of the inverting hysteresis circuit is VEE; when v isx<vTLThe output of the inverting hysteresis circuit is VCC; when v isTL≤vx≤vTHWhen the output is not changed, the output is kept in the original state; the holding and switching of the resistance state of the memristor are realized through the inverting hysteresis circuit; a sixth operational amplifier U6 and a resistor R are connected after the inverting hysteresis circuit2、R3、R4The output voltage of the adder circuit is as follows:
wherein, a ═ R4/R2, b ═ R3/R2, VsVCC, voltage aVEE + bVsAnd aVCC + bVsRespectively corresponding to the low and high memory values of the memory resistor by changing the resistance R2、R3、R4The ratio of the high resistance state and the low resistance state of the memristor is adjusted by the resistance value of the memristor.
5. The binary-type memristor circuit emulator of claim 1, wherein: multiplier U9 and thirteenth resistor RwA fourteenth resistor RzA multiplication circuit is formed to output a voltage signal proportional to the memristor current, and a thirteenth resistor RwA fourteenth resistor RzThe output signal v is obtained according to AD633 chip data manualwComprises the following steps:
6. The binary-type memristor circuit emulator of claim 4 or 5, wherein: the first current transmitter U7 and the second current transmitter U8 convert the output of the multiplier into current, and the result is obtained according to ohm's law and AD844 chip data handbook:
vw＝Rini (3)
where i is the current flowing through the memristor;
obtaining the equivalent memristor value and the voltage v of the binary memristor circuit simulator according to the formulas (2) and (3)GThe relationship of (a) to (b) is as follows:
G＝kGvG(4)
wherein k isG＝-(Rw+Rz)/(10RwRin) Can be obtained by modifying the thirteenth resistor RwA fourteenth resistor RzAnd a first resistor RinAdjusting an equivalent memristor value of the binary memristor circuit emulator;
the state equation of the binary memristor circuit simulator is obtained according to analysis and is as follows:
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Cited By (3)
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| CN113054986A (en) * | 2021-03-11 | 2021-06-29 | 杭州电子科技大学 | Three-terminal controllable memristor simulation circuit |
| CN114758702A (en) * | 2022-04-13 | 2022-07-15 | 湘潭大学 | Memory resistance accurate writing circuit |
| CN114758702B (en) * | 2022-04-13 | 2024-06-04 | 湘潭大学 | Memristor value accurate writing circuit |
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