CN109840365B - Active memristor simulator - Google Patents
Active memristor simulator Download PDFInfo
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- CN109840365B CN109840365B CN201910041957.3A CN201910041957A CN109840365B CN 109840365 B CN109840365 B CN 109840365B CN 201910041957 A CN201910041957 A CN 201910041957A CN 109840365 B CN109840365 B CN 109840365B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses an active memristor simulator, and particularly relates to the technical field of memristor simulation. The active memristor simulator utilizes the integrated operation circuit to realize corresponding operation in the characteristics of the active memristor, and can replace the actual active memristor to realize circuit design, experiment and application related to the actual active memristor under the condition that no actual active memristor device exists. The active memristor emulator comprises a resistance network, an inverse proportion device, an inverse integrator and a multiplier; the inverse proportion device comprises a first inverse proportion device, a second inverse proportion device, a third inverse proportion device and a fourth inverse proportion device, and is configured to realize that the output voltage and the input voltage are in inverse proportion operation relation; the resistor network comprises a fourth resistor, one end of the fourth resistor is connected with the power supply input end, and the other end of the fourth resistor is connected with the first inverse proportion device through a second resistor; the inverting integrator is configured to perform an integration operation on the voltage; the multiplier is configured for enabling multiplication of two input signals.
Description
Technical Field
The invention relates to the technical field of memristor simulation, in particular to an active memristor simulator.
Background
The memristor is the fourth basic circuit element that follows the resistance, inductance, and capacitance. In 1971, cai Shaotang proposed the concept of a memristor and predicted its existence, and the realization of the memristor was first reported in the laboratory of Hewlett-packard company in 2008. The memristor has the property that any combination of other three basic circuit elements cannot be copied, is a nonlinear resistor with a memory function, and is widely applied to the fields of computer science, neural networks, electronic engineering and the like. The memristor as a fourth basic circuit element is easily applied to a circuit to generate a chaotic phenomenon, so that the design of the memristor chaotic circuit also arouses great research interest in the academic world. Since physical memristors have not been widely manufactured and applied to practical circuits, most physical memristors are currently in the form of integrated circuits, and few independent memristor elements exist. In order to better utilize the unique properties of the memristor, the design of the memristor equivalent circuit has important significance. Therefore, the memristor equivalent circuit with simple principle, easy realization and high accuracy degree is designed to have important significance.
Disclosure of Invention
The invention aims to design a simulation circuit equivalent to a memristor, the simulation circuit has the advantages of simple principle, easy realization and high precision, and the similar memristor is widely researched and applied.
The invention specifically adopts the following technical scheme:
an active memristor emulator comprises a resistance network, an inverse proportion device, an inverse integrator and a multiplier;
the inverse proportion device comprises a first inverse proportion device, a second inverse proportion device, a third inverse proportion device and a fourth inverse proportion device, and is configured to realize that the output voltage and the input voltage are in inverse proportion operation relation;
the resistor network comprises a fourth resistor, one end of the fourth resistor is connected with the power supply input end, and the other end of the fourth resistor is connected with the first inverse phase proportioner through a second resistor;
the inverting integrator is configured to implement an integration operation on a voltage;
the multiplier is configured for enabling multiplication of two input signals.
Preferably, the first inverting comparator, the second inverting comparator, the third inverting comparator and the fourth inverting comparator are respectively formed by partial pins of the first LF347 chip, the inverting integrator is formed by partial pins of the second LF347 chip, and the multiplier is formed by an AD633JN chip.
Preferably, the first inverse proportion device is composed of a first pin, a second pin and a third pin of the first LF347N chip, the second inverse proportion device is composed of a fifth pin, a sixth pin and a seventh pin of the first LF347N chip, the third inverse proportion device is composed of an eighth pin, a ninth pin and a tenth pin of the first LF347N chip, and the fourth inverse proportion device is composed of a twelfth pin, a thirteenth pin and a fourteenth pin of the first LF347N chip;
a first pin of the first LF347N chip is connected with a second pin of the first LF347N chip through a seventh resistor, the second pin of the first LF347N chip is connected with a power supply input end through a second resistor and a fourth resistor, and a third pin of the first LF347N chip is connected with the power supply input end through the first resistor and is grounded through a third resistor;
a fifth pin of the first LF347N chip is grounded, a sixth pin of the first LF347N chip is connected with a first pin of the first LF347N chip through a sixth resistor, and a seventh pin of the first LF347N chip is connected with the sixth pin of the first LF347N chip through a ninth resistor;
the eighth pin of the first LF347N chip is connected with the ninth pin of the first LF347N chip through an eighth resistor, the eighth pin of the first LF347N chip is connected with the second pin of the first LF347N chip through a second resistor, the ninth pin of the first LF347N chip is connected with the first pin of the first LF347N chip through a fifth resistor, the ninth pin of the first LF347N chip is connected with the fourteenth pin through a twelfth resistor, and the tenth pin of the first LF347N chip is grounded;
the twelfth pin of the first LF347N chip is grounded, the thirteenth pin thereof is connected to the fourteenth pin thereof through an eleventh resistor, and the fourteenth pin thereof is connected to the second pin of the second LF347 chip through a thirteenth resistor.
Preferably, the inverting integrator is formed by a first pin, a second pin and a third pin of the second LF347N chip, the first pin of the second LF347N chip is connected to the second pin thereof through a second capacitor, the second pin thereof is connected to the first pin thereof through a fifteenth resistor, and the second pin thereof is connected to the seventh pin of the first LF347N chip through a fourteenth resistor.
Preferably, the pin X1 of the AD633JN chip is connected to the first pin of the first LF347N chip, the pin Y1 of the AD633JN chip is connected to the first pin of the second LF347N chip, the pin X2 and the pin Y2 of the AD633JN chip are grounded, the pin VS + thereof is connected to the power source VCC, the pin VS-thereof is connected to the power source VEE, the pin Z thereof is grounded, and the pin W thereof is connected to the pin 13 of the inverse proportion device U1D through a tenth resistor.
Preferably, the current flowing through the fourth resistor is i M ,R 1 ～R 15 Respectively corresponding resistance values C of the first to fifteenth resistors 2 The output of the first pin of the first LF347N chip after passing through the first inverse phase proportioner is v 0 Represented by formula (1):
the seventh pin output of the first LF347N chip is-v 0 The two input signals of the multiplier are respectively v at the X1 end of the AD633JN chip 0 And the output v of the w pin of the q, AD633JN chip at the Y2 terminal w Represented by formula (2):
v w ＝qv 0 (2)；
the fourteenth pin output of the first LF347N chip is v 14 Represented by formula (3)
The eighth pin of the first LF347N chip outputs v M Is represented by formula (4)
The definition of the first pin output variable q of the second LF347N chip is expressed by formula (5)
The expression of the active memristor is represented by equation (6)
The invention has the following beneficial effects:
the active memristor simulator utilizes an analog circuit to realize the volt-ampere characteristic of an active memristor, specifically realizes the volt-ampere characteristic of the active memristor, utilizes an integrated operational circuit to realize corresponding operation in the characteristic of the active memristor, the analog circuit of the active memristor simulator comprises 5 operational amplifiers and 1 multiplier, the integrated operational amplifier is mainly used for realizing inverse integral and inverse proportional operation, and the multiplier is used for realizing the product of two input signals; the circuit is simple in structure, and under the condition that no actual active memristor device exists, the circuit can be designed, tested and applied instead of the actual active memristor, and the circuit is relevant to the actual active memristor, so that the circuit is of great significance to the research on the characteristics and the application of the active memristor.
Drawings
FIG. 1 is a block diagram of an active memristor emulator architecture;
fig. 2 is an active memristor circuit diagram.
Detailed Description
The following description of the embodiments of the present invention will be made with reference to the accompanying drawings:
the active memristor emulator is based on a general expression of memristor current-voltage characteristics:
as shown in fig. 1, an active memristor emulator includes a resistance network, an inverse proportion device, an inverse integrator, and a multiplier;
the inverse proportion device comprises a first inverse proportion device, a second inverse proportion device, a third inverse proportion device and a fourth inverse proportion device, and is configured to realize that the output voltage and the input voltage are in inverse proportion operation relation;
the resistor network comprises a fourth resistor, one end of the fourth resistor is connected with the power supply input end, and the other end of the fourth resistor is connected with the first inverse proportion device through a second resistor;
the inverting integrator is configured to perform an integration operation on the voltage;
the multiplier is configured for enabling multiplication of two input signals.
The first inverse proportion device, the second inverse proportion device, the third inverse proportion device and the fourth inverse proportion device are respectively formed by partial pins of the first LF347 chip, the inverse integral device is formed by partial pins of the second LF347 chip, the multiplier is formed by an AD633JN chip, and the fourth pin and the eleventh pin of the first LF347 chip and the fourth LF347 chip are grounded.
As shown in fig. 2, the first inverse proportion device is composed of a first pin, a second pin and a third pin of the first LF347N chip, the second inverse proportion device is composed of a fifth pin, a sixth pin and a seventh pin of the first LF347N chip, the third inverse proportion device is composed of an eighth pin, a ninth pin and a tenth pin of the first LF347N chip, and the fourth inverse proportion device is composed of a twelfth pin, a thirteenth pin and a fourteenth pin of the first LF347N chip;
a first pin of the first LF347N chip is connected with a second pin of the first LF347N chip through a seventh resistor, the second pin of the first LF347N chip is connected with a power supply input end through a second resistor and a fourth resistor, and a third pin of the first LF347N chip is connected with the power supply input end through a first resistor and is grounded through a third resistor;
a fifth pin of the first LF347N chip is grounded, a sixth pin of the first LF347N chip is connected with a first pin of the first LF347N chip through a sixth resistor, and a seventh pin of the first LF347N chip is connected with the sixth pin of the first LF347N chip through a ninth resistor;
the eighth pin of the first LF347N chip is connected with the ninth pin of the first LF347N chip through an eighth resistor, the eighth pin of the first LF347N chip is connected with the second pin of the first LF347N chip through a second resistor, the ninth pin of the first LF347N chip is connected with the first pin of the first LF347N chip through a fifth resistor, the ninth pin of the first LF347N chip is connected with the fourteenth pin through a twelfth resistor, and the tenth pin of the first LF347N chip is grounded;
the twelfth pin of the first LF347N chip is grounded, the thirteenth pin thereof is connected to the fourteenth pin thereof through an eleventh resistor, and the fourteenth pin thereof is connected to the second pin of the second LF347 chip through a thirteenth resistor.
The inverting integrator is formed by a first pin, a second pin and a third pin of the second LF347N chip, the first pin of the second LF347N chip is connected with the second pin of the second LF347N chip through a second capacitor, the second pin of the second LF347N chip is connected with the first pin of the second LF347N chip through a fifteenth resistor, and the second pin of the second LF347N chip is connected with the seventh pin of the first LF347N chip through a fourteenth resistor.
The X1 pin of the AD633JN chip is connected with the first pin of the first LF347N chip, the Y1 pin of the AD633JN chip is connected with the first pin of the second LF347N chip, the X2 pin and the Y2 pin of the AD633JN chip are grounded, the VS + pin of the AD633JN chip is connected with a power supply VCC, the VS-pin of the AD633JN chip is connected with a power supply VEE, the Z pin of the AD633JN chip is grounded, and the W pin of the AD633JN chip is connected with the 13 th pin of the inverse proportion device U1D through a tenth resistor.
The current flowing through the fourth resistor is i M ,R 1 ～R 15 Respectively corresponding resistance values C of the first to fifteenth resistors 2 The output of the first pin of the first LF347N chip after passing through the first inverse proportion device is v 0 Represented by formula (1):
wherein ε = R 7 R 4 /R 2 。
The seventh pin output of the first LF347N chip is-v 0 Two input signals of the multiplier are respectively v at the X1 end of an AD633JN chip 0 And q at the Y2 terminal, where the symbol q represents the memristor internal charge signal, the output v of the w pin of the AD633JN chip w Represented by formula (2):
v w ＝qv 0 (2)；
the fourteenth pin output of the first LF347N chip is v 14 Represented by formula (3)
The eighth pin of the first LF347N chip outputs v M Is represented by formula (4)
The definition of the first pin output variable q of the second LF347N chip is expressed by formula (5)
The expression of the active memristor is represented by equation (6)
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make various changes, modifications, additions and substitutions within the spirit and scope of the present invention.
Claims (4)
1. An active memristor emulator is characterized by comprising a resistance network, an inverse proportion device, an inverse integrator and a multiplier;
the inverse proportion device comprises a first inverse proportion device, a second inverse proportion device, a third inverse proportion device and a fourth inverse proportion device, and is configured to realize that the output voltage and the input voltage are in inverse proportion operation relation;
the resistor network comprises a fourth resistor, one end of the fourth resistor is connected with the power supply input end, and the other end of the fourth resistor is connected with the first inverse proportion device through a second resistor;
the inverting integrator is configured to perform an integration operation on a voltage;
the multiplier is configured for enabling multiplication of two input signals.
The first inverse proportion device, the second inverse proportion device, the third inverse proportion device and the fourth inverse proportion device are respectively formed by partial pins of a first LF347 chip, the inverse integrator is formed by partial pins of a second LF347 chip, and the multiplier is formed by an AD633JN chip.
The first inverse proportion device consists of a first pin, a second pin and a third pin of the first LF347N chip, the second inverse proportion device consists of a fifth pin, a sixth pin and a seventh pin of the first LF347N chip, the third inverse proportion device consists of an eighth pin, a ninth pin and a tenth pin of the first LF347N chip, and the fourth inverse proportion device consists of a twelfth pin, a thirteenth pin and a fourteenth pin of the first LF347N chip;
a first pin of the first LF347N chip is connected with a second pin of the first LF347N chip through a seventh resistor, the second pin of the first LF347N chip is connected with a power supply input end through a second resistor and a fourth resistor, and a third pin of the first LF347N chip is connected with the power supply input end through the first resistor and is grounded through a third resistor;
a fifth pin of the first LF347N chip is grounded, a sixth pin of the first LF347N chip is connected with a first pin of the first LF347N chip through a sixth resistor, and a seventh pin of the first LF347N chip is connected with the sixth pin of the first LF347N chip through a ninth resistor;
the eighth pin of the first LF347N chip is connected with the ninth pin of the first LF347N chip through an eighth resistor, the eighth pin of the first LF347N chip is connected with the second pin of the first LF347N chip through a second resistor, the ninth pin of the first LF347N chip is connected with the first pin of the fifth resistor through a fifth resistor, the ninth pin of the first LF347N chip is connected with the fourteenth pin of the fifth resistor through a twelfth resistor, and the tenth pin of the first LF347N chip is grounded;
the twelfth pin of the first LF347N chip is grounded, the thirteenth pin thereof is connected to the fourteenth pin thereof through an eleventh resistor, and the fourteenth pin thereof is connected to the second pin of the second LF347 chip through a thirteenth resistor.
2. The active memristor emulator of claim 1, wherein the inverting integrator is formed by a first pin, a second pin and a third pin of the second LF347N chip, the first pin of the second LF347N chip is connected to the second pin thereof through a second capacitor, the second pin thereof is connected to the first pin thereof through a fifteenth resistor, and the second pin thereof is connected to the seventh pin of the first LF347N chip through a fourteenth resistor.
3. The active memristor emulator of claim 1, wherein pin X1 of the AD633JN chip is connected to the first pin of the first LF347N chip, pin Y1 of the AD633JN chip is connected to the first pin of the second LF347N chip, pin X2 and pin Y2 of the AD633JN chip are grounded, pin VS + thereof is connected to the power VCC, pin VS-thereof is connected to the power VEE, pin Z thereof is connected to the ground, and pin W thereof is connected to pin 13 of the inverse scale U1D through a tenth resistor.
4. The active memristor emulator of any of claims 1-3, wherein the current flowing through the fourth resistor is i M ,R 1 ～R 15 Respectively corresponding resistance values C of the first to fifteenth resistors 2 The output of the first pin of the first LF347N chip after passing through the first inverse phase proportioner is v 0 Represented by formula (1):
the seventh pin output of the first LF347N chip is-v 0 Two input signals of the multiplier are respectively v at the X1 end of an AD633JN chip 0 And q at the Y2 terminal, where the symbol q represents the memristor internal charge signal, where e = R 7 R 4 /R 2 Output v of w pin of AD633JN chip w Represented by formula (2):
v w ＝qv 0 (2)；
the fourteenth pin output of the first LF347N chip is v 14 Represented by formula (3)
The eighth pin output of the first LF347N chip is v M Is represented by formula (4)
The definition of the first pin output variable q of the second LF347N chip is expressed by formula (5)
The expression of the active memristor is represented by equation (6)
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| CN110222425B (en) * | 2019-06-09 | 2023-04-18 | 山东科技大学 | Equivalent analog circuit with twin local active domain cubic polynomial magnetic control memristor |
| CN110110494B (en) * | 2019-06-09 | 2023-04-18 | 山东科技大学 | Equivalent analog circuit of resistor is recalled to two local active absolute value magnetic controls |
| CN110765718B (en) * | 2019-09-24 | 2024-05-03 | 杭州电子科技大学 | Binary memristor circuit simulator |
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| CN103219983A (en) * | 2013-04-16 | 2013-07-24 | 杭州电子科技大学 | Memristor equivalent simulation circuit |
| US9019030B1 (en) * | 2014-09-18 | 2015-04-28 | King Fahd University Of Petroleum And Minerals | Memristor-based emulator for use in digital modulation |
| CN108718190A (en) * | 2018-06-01 | 2018-10-30 | 杭州电子科技大学 | A kind of local active memristor emulator of exponential type |
| CN109086558A (en) * | 2018-09-29 | 2018-12-25 | 杭州电子科技大学 | The local active memristor emulator of logarithmic |
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| US8848337B2 (en) * | 2011-02-01 | 2014-09-30 | John R. Koza | Signal processing devices having one or more memristors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219983A (en) * | 2013-04-16 | 2013-07-24 | 杭州电子科技大学 | Memristor equivalent simulation circuit |
| US9019030B1 (en) * | 2014-09-18 | 2015-04-28 | King Fahd University Of Petroleum And Minerals | Memristor-based emulator for use in digital modulation |
| CN108718190A (en) * | 2018-06-01 | 2018-10-30 | 杭州电子科技大学 | A kind of local active memristor emulator of exponential type |
| CN109086558A (en) * | 2018-09-29 | 2018-12-25 | 杭州电子科技大学 | The local active memristor emulator of logarithmic |
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