CN110752251A - 复合衬底及其制造方法 - Google Patents

复合衬底及其制造方法 Download PDF

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CN110752251A
CN110752251A CN201810818803.6A CN201810818803A CN110752251A CN 110752251 A CN110752251 A CN 110752251A CN 201810818803 A CN201810818803 A CN 201810818803A CN 110752251 A CN110752251 A CN 110752251A
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substrate
holes
filling
composite substrate
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王兴民
李瑞评
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CRYSTALWISE Tech Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • BPERFORMING OPERATIONS; TRANSPORTING
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract

一种复合衬底及其制造方法,其制造方法包括有:提供一基材,该基材具有一基材表面,且于该基材表面具有多个孔洞;提供一填补层,该填补层包括有多个填补材料,该些填补材料分别填补于该些孔洞当中,从而制成该复合衬底。通过上述设计,可有效填平基材上的孔洞,提升外延质量,以及有效改善衬底的散热效果,提升耐高温能力。

Description

复合衬底及其制造方法
技术领域
本发明涉及复合衬底,尤其涉及一种可提升外延质量的复合衬底及其制造方法。
背景技术
于外延用衬底领域当中,不论是多晶衬底或是非晶衬底,其表面上时常会产生有多个孔洞缺陷,举例而言,以多晶衬底为例,其于微小单晶颗粒之间存在多个边界区(Grainboundary),且因为每颗微小颗粒的晶向并不一致,因此于进行抛光加工后,仍会有部分的微小孔洞残留,而影响后续外延质量。
是以,如何改善上述缺陷,以提升外延质量,是本发明人苦心研究的方向之一。
发明内容
有鉴于此,本发明的目的在于提供一种复合衬底及其制造方法,可有效填平衬底上的孔洞,以提升外延质量,以及提升衬底散热效果。
为了达成上述目的,本发明提供一种复合衬底,包括有:一基材,具有一基材表面,于该基材表面具有多个孔洞;以及一填补层,设置于该基材表面,该填补层具有一主体以及自该主体一侧延伸形成的多个填补材料,该主体的厚度不超过10nm,该些填补材料分别填补于该些孔洞当中。
为了达成上述目的,本发明还提供一种复合衬底,包括有:一基材,具有一基材表面,于该基材表面具有多个孔洞;多个填补材料,分别填补于该些孔洞当中。
为了达成上述目的,本发明另提供一种复合衬底的制造方法,包括有:提供一基材,该基材具有一基材表面,且于该基材表面具有多个孔洞;提供一填补层,该填补层包括有多个填补材料,该些填补材料分别填补于该些孔洞当中。
本发明的效果在于,通过上述设计,可有效填平基材上的孔洞,提升外延质量,以及有效改善衬底的散热效果,提升耐高温能力。
附图说明
图1为本发明一实施例的复合衬底的制造方法的流程图。
图2至图7为本发明一实施例的复合衬底的结构示意图。
【符号说明】
[本发明]
100复合衬底
10基材
10a基材表面 12孔洞
20填补层
22主体 24填补材料
30外延层
D厚度
具体实施方式
为能更清楚地说明本发明,现例举一较佳实施例并配合附图详细说明如后。请参图1至图4所示,为本发明一实施例的复合衬底100的制造方法流程图以及该复合衬底100的结构示意图。该制造方法包括有以下步骤:
首先,先提供一基材10。该基材10具有一基材表面10a,于该基材表面10a具有多个孔洞12。其中,于一实施例中,所述基材10厚度选用500μm至1000μm之间,于本实施例中,选用厚度为750μm的基材10;另外,于一实施例中,所述的基材10选自氮化铝、氧化铝或碳化硅等材料制成的多晶或非晶基材,于本实施例中,以多晶氮化铝(Poly-AlN)制成的基材10为例,其中,选用多晶氮化铝的好处在于,多晶氮化铝材料具备高热传导性、高电器绝缘性,且与氮化镓为例的外延层之间的晶格匹配性佳,尤其适合应用在高电压、高电流甚至高频的相关IC当中;于一实施例中,所述的该些孔洞12由该基材10的基材表面10a经研磨抛光(例如通过化学机械抛光)加工后所残留的微小孔洞(Pits)。
接着,提供一填补层20,设置或形成于该基材10的基材表面10a。其中,该填补层20包括有一主体22以及多个填补材料24,较佳者,该主体22的厚度D不超过10nm,其中,所述的厚度D指自基材10的基材表面10a起至填补层20的上表面之间的厚度;该些填补材料24自该主体22的一侧延伸形成,且该些填补材料24分别填入于该些孔洞12当中。其中,于一实施例中,所述的填补层20可以是利用旋涂式工艺(Spin-on Glass;SOG)、物理气相沉积(Physical Vapor Deposition,PVD)、化学气相沉积(Chemical Vapor Deposition,CVD)等或是其他工艺形成于该基材10的基材表面10a上,而于本实施例中,以旋涂式工艺为例;另外,所述填补层20的材料选用可选择氧化物或氮化物,举例而言,可以选用硅酸盐类(SixOy)、ZnOx、SiN等,但不以此为限,而于本实施例中,选用硅酸盐类作为填补层20的材料。另外,于一实施例中,亦可进一步薄化该填补层20,以使得该填补层20的厚度不超过10nm,以降低其对基材10的散热效果的影响。
通过上述工艺,便可制成如图3所示的复合衬底100,而通过有效地填平该些孔洞12的设计,可有助于该复合衬底100在后续外延工艺时,提升其外延质量,例如如图4所示可以在填补层20的主体22的另一侧进一步设置一外延层30,其中,该外延层30可以是GaN等但不以此为限。此外,通过该填补层20的主体22厚度不超过10nm的设计,可有助于提升该复合衬底100的散热效果,提升其整体耐高温能力。
另外,请配合图3及图5所示,于一实施例中,可进一步薄化该填补层20,以使得在该基材10的基材表面10a以上的填补层20的主体22被去除,只留下填补于该些孔洞12当中的该些填补材料24,另外,较佳者,该些填补材料24自该些孔洞12中外露的表面实质上与该基材表面10a齐平,从而获得较佳的平坦化效果,进而有助于复合衬底后续工艺的进行,例如图6所示,可在基材10的基材表面10a上设置外延层30。另外,于一实施例中,除了去除该主体22之外,亦可进一步薄化部分的基材10,例如利用抛光加工方式薄化该基材10,且该基材10自该基材表面10a被薄化或称被去除的厚度不超过6μm,较佳者,小于3μm。
另外,请配合图7,于另一复合衬底的制造方法的实施例当中,在提供具有多个孔洞12的基材10之后,可仅在该些孔洞12当中填入填补材料24,而不在不具有孔洞12的基材10表面上设置填补层20的主体22,且较佳者,该些填补材料24自该些孔洞12中外露的表面实质上与该基材表面10a齐平,于后,可进一步在该基材10的基材表面设置外延层。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (13)

1.一种复合衬底,包括有:
一基材,具有一基材表面,于该基材表面具有多个孔洞;以及
一填补层,设置于该基材表面,该填补层具有一主体以及自该主体一侧延伸形成的多个填补材料,该主体的厚度不超过10nm,该些填补材料分别填补于该些孔洞当中。
2.如权利要求1所述的复合衬底,其中该基材包括有氮化铝、氧化铝或碳化硅。
3.如权利要求1所述的复合衬底,其中该填补层包括有氧化物或氮化物。
4.如权利要求1所述的复合衬底,包括有一外延层,设置于该主体的另一侧。
5.一种复合衬底,包括有:
一基材,具有一基材表面,于该基材表面具有多个孔洞;
多个填补材料,分别填补于该些孔洞当中。
6.如权利要求5所述的复合衬底,其中该些填补材料自该些孔洞中外露的表面与该基材表面齐平。
7.如权利要求5所述的复合衬底,其中该基材包括有氮化铝、氧化铝或碳化硅。
8.如权利要求5所述的复合衬底,其中该填补材料包括有氧化物或氮化物。
9.如权利要求5所述的复合衬底,包括有一外延层,设置于该基材表面。
10.一种复合衬底的制造方法,包括有:
提供一基材,该基材具有一基材表面,且于该基材表面具有多个孔洞;
提供一填补层,该填补层包括有多个填补材料,该些填补材料分别填补于该些孔洞当中。
11.如权利要求10所述的制造方法,包括有以下步骤:薄化该填补层,使该填补层的厚度不超过10nm。
12.如权利要求10所述的制造方法,包括有以下步骤:薄化该填补层,并使该基材的该基材表面露出,且使该些填补材料自该些孔洞中外露的表面与该基材表面齐平。
13.如权利要求10所述的制造方法,其中该填补层包括有一主体,该些填补材料自该主体一侧延伸形成,该制造方法包括有以下步骤:去除该主体以及薄化该基材,且该基材自该基材表面被薄化的厚度不超过6μm。
CN201810818803.6A 2018-07-24 2018-07-24 复合衬底及其制造方法 Pending CN110752251A (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110221039A1 (en) * 2010-03-12 2011-09-15 Sinmat, Inc. Defect capping for reduced defect density epitaxial articles
CN104364905A (zh) * 2013-03-27 2015-02-18 日本碍子株式会社 半导体用复合基板的操作基板
WO2017149079A1 (fr) * 2016-03-04 2017-09-08 Saint-Gobain Lumilog Procede de fabrication d'un substrat semi-conducteur
US20180047557A1 (en) * 2016-06-24 2018-02-15 Quora Technology, Inc. Polycrystalline ceramic substrate and method of manufacture
US9978590B1 (en) * 2017-05-24 2018-05-22 National Chung Shan Institute Of Science And Technology Method of manufacturing epitaxiable heat-dissipating substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110221039A1 (en) * 2010-03-12 2011-09-15 Sinmat, Inc. Defect capping for reduced defect density epitaxial articles
CN104364905A (zh) * 2013-03-27 2015-02-18 日本碍子株式会社 半导体用复合基板的操作基板
WO2017149079A1 (fr) * 2016-03-04 2017-09-08 Saint-Gobain Lumilog Procede de fabrication d'un substrat semi-conducteur
US20180047557A1 (en) * 2016-06-24 2018-02-15 Quora Technology, Inc. Polycrystalline ceramic substrate and method of manufacture
US9978590B1 (en) * 2017-05-24 2018-05-22 National Chung Shan Institute Of Science And Technology Method of manufacturing epitaxiable heat-dissipating substrate

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