CN110718509A - Electronic component packaging structure and packaging method - Google Patents

Electronic component packaging structure and packaging method Download PDF

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Publication number
CN110718509A
CN110718509A CN201810763291.8A CN201810763291A CN110718509A CN 110718509 A CN110718509 A CN 110718509A CN 201810763291 A CN201810763291 A CN 201810763291A CN 110718509 A CN110718509 A CN 110718509A
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China
Prior art keywords
electronic component
buffer layer
packaging
stress buffer
protective layer
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CN201810763291.8A
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Chinese (zh)
Inventor
曹俊
江伟
何昌
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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Gree Electric Appliances Inc of Zhuhai
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Priority to CN201810763291.8A priority Critical patent/CN110718509A/en
Publication of CN110718509A publication Critical patent/CN110718509A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides an electronic element packaging structure and a packaging method, relates to the technical field of semiconductor devices, and solves the technical problems of chip damage and failure caused by mismatching of packaging stress between a packaging protective layer and a chip in the prior art. The packaging structure comprises an electronic element, a protective layer and a stress buffer layer, wherein the stress buffer layer is arranged between the electronic element and the protective layer, and can buffer and weaken the packaging stress applied by the protective layer to the electronic element. The stress buffer layer is arranged between the electronic element and the protective layer to buffer and weaken the packaging stress applied to the electronic element by the protective layer, the failure damage of the electronic element is reduced, the water vapor invasion is prevented, the ion pollution is isolated, and the reliability of the electronic element is improved.

Description

Electronic component packaging structure and packaging method
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an electronic element packaging structure and a packaging method.
Background
Packaging refers to the use of wire bonding of circuit pins on a silicon die to external connections for connection to other devices. The package form refers to a housing for mounting a semiconductor integrated circuit chip. The chip is not only used for mounting, fixing, sealing, protecting the chip and enhancing the electric heating performance, but also connected to pins of the packaging shell through the connection points on the chip by leads, and the pins are connected with other devices through the leads on the printed circuit board, thereby realizing the connection of the internal chip and an external circuit. Because the chip must be isolated from the outside to prevent the electrical performance degradation caused by the corrosion of the chip circuit by impurities in the air. On the other hand, the packaged chip is more convenient to mount and transport. The quality of the packaging technology is also of great importance since it directly affects the performance of the chip itself and the design and manufacture of the PCB to which it is connected.
With the development of semiconductor device technology, semiconductor devices have been developed to have high current density, high reliability and low cost. In order to achieve higher current density and cost saving, the thickness of semiconductor devices is continuously reduced, but the problem of package stress is more and more prominent. For example, referring to fig. 1 and fig. 2, an epoxy resin 3' as a protective layer of an IGBT chip 1' of an electronic component is in direct contact with the chip, the epoxy resin 3' has a thermal expansion coefficient of about 17 ppm and has a high hardness and a large elastic modulus value, while a silicon chip has a thermal expansion coefficient of only 3.5 ppm, and the chip surface is easily layered in a cold and heat circulation mode, and the internal structure of the chip is easily damaged; meanwhile, the moisture absorption rate of the epoxy resin is about 0.3%, and a series of problems such as electrical failure, ion pollution, popcorn effect and the like are easily caused when water vapor invades the surface of the chip, so that the chip is damaged and failed, and the reliability of the semiconductor device is influenced.
In order to solve the problem of package stress of the electronic element, a buffer layer is disposed on the upper surface of the electronic element to reduce local stress concentration generated by the electronic element, but this method can only improve the stress distribution on the upper surface of the electronic element, and cannot solve the problem of stress mismatch of the whole electronic element at high temperature.
Disclosure of Invention
The invention aims to provide an electronic element packaging structure and a packaging method, which are used for solving the technical problems of chip damage and failure caused by mismatching of packaging stress between a packaging protective layer and a chip in the prior art. The technical effects that can be produced by the preferred technical scheme in the technical schemes provided by the invention are described in detail in the following.
In order to achieve the purpose, the invention provides the following technical scheme:
the invention provides an electronic element packaging structure which comprises an electronic element, a protective layer and a stress buffer layer, wherein the stress buffer layer is arranged between the electronic element and the protective layer, and can buffer and weaken the packaging stress applied to the electronic element by the protective layer.
Optionally, the stress buffer layer is made of an elastic material, and a thermal expansion coefficient of a material of the stress buffer layer is greater than a thermal expansion coefficient of a material of the protection layer.
Optionally, the electronic component is a chip or a transistor.
Optionally, the electronic component is connected to a pin or other electronic component through a conductor, and the stress buffer layer covers a surface of the electronic component.
Optionally, the moisture absorption rate of the stress buffer layer is less than 0.03%.
Optionally, the stress buffer layer is formed by curing a polyimide material.
Optionally, the thickness of the stress buffer layer is less than or equal to 200 μm.
Optionally, the protective layer is manufactured by plastic package, ceramic package and/or gold package.
The invention provides a packaging method, which comprises the electronic element packaging structure, wherein the packaging process comprises the following steps:
step A: covering the stress buffer layer outside the electronic element;
and B: covering a protective layer outside the stress buffer layer, wherein the stress buffer layer is arranged between the electronic element and the protective layer.
Optionally, step a is preceded by connecting the electronic component to the pin or other electronic component through the conductor.
Optionally, the stress buffer layer is formed by heating and curing a polyimide material in a segmented manner.
Optionally, the curing method of the polyimide comprises the following steps:
step a: heating the chip covered with the polyimide to 100 ℃ from normal temperature, and heating at the speed of 2.5 ℃/m22 to heat 25m 22-35 m 22;
step b: placing the mixture in an environment at 100 ℃ and 55m 22-65 m 22;
step c: heating the mixture from 100 ℃ to 250 ℃, and heating the mixture at a speed of 5 ℃/m22 to heat the mixture to 25m 22-35 m 22;
step d: placing the mixture in an environment with the temperature of 250 ℃ and the thickness of 55m 22-65 m 22;
step e: and cooling from 250 ℃ to normal temperature, wherein 55m 22-65 m22 is needed, and the curing process is finished.
According to the electronic element packaging structure and the packaging method provided by the invention, the stress buffer layer is arranged between the electronic element and the protective layer to buffer and weaken the packaging stress applied by the protective layer to the electronic element, so that the failure damage of the electronic element is reduced, and the reliability of the electronic element is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a front view of a prior art IGBT chip package structure;
FIG. 2 is a top view of a prior art IGBT chip package structure;
FIG. 3 is a front view of an IGBT chip package structure according to an embodiment of the present invention;
FIG. 4 is a top view of an IGBT chip package structure in one embodiment of the present invention;
FIG. 5 is a schematic diagram of a top view structure of a lead frame in the packaging process of the IGBT chip;
FIG. 6 is a schematic diagram of a front view structure of a lead frame in the packaging process of the IGBT chip;
FIG. 7 is a schematic diagram of a top view structure of an IGBT chip of the invention after welding the chip in the packaging process;
FIG. 8 is a schematic diagram of a front view structure of an IGBT chip after welding the chip in the packaging process;
FIG. 9 is a schematic diagram of a top view structure of an IGBT chip of the present invention after an aluminum wire is welded in the packaging process;
FIG. 10 is a schematic diagram of a front view structure of an IGBT chip of the invention after an aluminum wire is welded in the packaging process;
FIG. 11 is a schematic diagram of a top view structure of a chip covered with polyimide in the IGBT chip packaging process according to the present invention;
FIG. 12 is a schematic diagram of a front view structure of a chip covered with polyimide in the packaging process of an IGBT chip according to the present invention;
FIG. 13 is a schematic view of a top view of a polyimide molded with epoxy during packaging of an IGBT chip according to the present invention;
FIG. 14 is a schematic structural diagram of a front view of polyimide after epoxy resin is injected outside the polyimide in the packaging process of the IGBT chip;
fig. 15 is a flowchart of a curing step of polyimide.
In fig. 1 and 2: 1', an IGBT chip; 3', epoxy resin; 4', emitter aluminum wire; 5', a lead frame; 6', a bonding material; 7', a grid aluminum wire; 8', pins;
in fig. 3-14: 1. an IGBT chip; 2. a polyimide; 3. an epoxy resin; 4. an emitter aluminum wire; 5. a lead frame; 6. a bonding material; 7. a gate aluminum line; 8. and (7) a pin.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail below. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without any inventive step, are within the scope of the present invention.
As shown in fig. 3 and 4, the present invention provides an electronic device package structure, which includes an electronic device, a protection layer, and a stress buffering layer, wherein the stress buffering layer is disposed between the electronic device and the protection layer, and the stress buffering layer can buffer and reduce the package stress applied by the protection layer to the electronic device.
The stress buffer layer is arranged between the electronic element and the protective layer to buffer and weaken the packaging stress applied by the protective layer to the electronic element, reduce the failure damage of the electronic element and improve the reliability of the electronic element.
In an alternative embodiment, the stress buffer layer is made of an elastic material, and the thermal expansion coefficient of the material of the stress buffer layer is greater than that of the material of the protective layer.
The soft-texture and good-elasticity material is adopted to form a buffer effect between the electronic element and the protective layer, so that the surface layering of the IGBT chip 1 is prevented, and the 'dark damage' in the chip is reduced.
As an alternative embodiment, the electronic component is an IGBT chip 1 or a MOSFET chip.
In an alternative embodiment, the electronic component is connected to the pin 8 or other electronic component through a conductor, and the stress buffer layer is also covered outside the connection part of the conductor and the electronic component.
The stress buffer layer also covers the outside of the connecting part of the conductor and the electronic element, so that the strength of the connecting part is improved, and the long-term reliable work of the device is ensured.
As an alternative embodiment, the moisture absorption rate of the stress buffer layer is less than 0.03%.
Because the moisture absorption rate is low, the stress buffer layer can prevent that steam from invading IGBT chip 1, and isolated ion pollutes, improves IGBT chip 1's life.
As an alternative embodiment, the stress buffer layer is coated on the surface of the electronic component.
The stress buffer layer is thinly covered on the surface of the electronic element by adopting a coating mode, so that the stress buffer layer is prevented from overflowing.
As an alternative embodiment, the stress buffer layer is formed by curing a polyimide 2 material.
The polyimide 2 has good high-temperature creep resistance at high temperature, and can reduce the thermal stress borne by the surface of the IGBT chip 1. And the polyimide 2 material has the characteristics of soft texture, good elasticity and low moisture absorption rate after being cured.
In an alternative embodiment, the stress buffer layer has a thickness of 200 μm or less.
The thickness of the stress buffer layer is controlled within 200 mu m, so that the purposes of buffering stress and reducing water vapor invasion are achieved, meanwhile, the overflow of the material of the buffer stress layer is prevented, and the waste is reduced.
As an alternative embodiment, the protective layer is molded with epoxy resin 3.
The reliability of the IGBT chip 1 is affected by physical properties such as the thermal expansion coefficient and the moisture absorption rate of the encapsulating material (protective layer), and the purpose of improving the reliability of the IGBT chip 1 is achieved by providing a stress buffer layer between the encapsulating material and the IGBT chip 1.
The invention provides a packaging method, which comprises the electronic element packaging structure, wherein the packaging process comprises the following steps:
step A: covering the stress buffer layer outside the electronic element;
and B: the protective layer is covered outside the stress buffer layer, and the stress buffer layer is arranged between the electronic element and the protective layer.
As an alternative embodiment, step a is preceded by connecting the electronic component to the pin 8 or other electronic component through a conductor.
In an alternative embodiment, the stress buffer layer is formed by heating and curing the polyimide 2 material in sections.
As shown in fig. 5 to 14, the package of the IGBT chip 1 includes: firstly, preparing a lead frame 5, wherein the lead frame 5 is an array of a plurality of products, and is convenient for automatic production; secondly, welding the IGBT chip 1 and the lead frame 5 by using a solder paste, a solder wire or nano-silver welding process to realize mechanical and electrical connection, wherein a bonding material 6 is formed between the IGBT chip 1 and the lead frame; thirdly, welding aluminum wires, and electrically connecting a grid aluminum wire 7 and an emitter aluminum wire 4 of the IGBT chip 1 to a grid pin and an emitter pin; fourthly, preparing a polyimide 2 solution, and then covering the whole IGBT chip 1 with the polyimide 2 by using a spraying or coating method; fifthly, forming a thin film protective layer after the polyimide 2 is quickly cured by using a baking method; sixthly, extruding the melted epoxy resin 3 into a preset die through an injection molding machine to play a role in protecting the IGBT chip 1 and the support frame; and seventhly, cutting off redundant connecting rods, reserving a plurality of connecting rods for the lead frame 5 to play the roles of conveying, bridging, supporting and the like for automatic production, and cutting off redundant parts in the packaging end process.
The polyimide 2 solution is uniformly arranged on the surface of the IGBT chip 1 through a spraying, coating or dispensing process to form a film with the thickness of about 0-200 mu m; the film can play the roles of stress buffering, moisture prevention and ion pollution isolation.
As an alternative embodiment, as shown in fig. 15, the curing method of the polyimide 2 includes the steps of:
step a: heating the IGBT chip 1 covered with the polyimide 2 from the normal temperature to 100 ℃, and heating at the speed of 2.5 ℃/m22 to heat 25m 22-35 m22 in total;
step b: placing the mixture in an environment at 100 ℃ and 55m 22-65 m 22;
step c: heating the mixture from 100 ℃ to 250 ℃, and heating the mixture at a speed of 5 ℃/m22 to heat the mixture to 25m 22-35 m 22;
step d: placing the mixture in an environment with the temperature of 250 ℃ and the thickness of 55m 22-65 m 22;
step e: and cooling from 250 ℃ to normal temperature, wherein 55m 22-65 m22 is needed, and the curing process is finished.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (12)

1. An electronic component packaging structure is characterized by comprising an electronic component, a protective layer and a stress buffer layer, wherein the stress buffer layer is arranged between the electronic component and the protective layer, and can buffer and weaken the packaging stress applied by the protective layer to the electronic component.
2. The electronic device package structure of claim 1, wherein the stress buffer layer is made of an elastic material, and a thermal expansion coefficient of the material of the stress buffer layer is greater than a thermal expansion coefficient of the material of the protection layer.
3. The electronic device package structure of claim 1, wherein the electronic device is a chip or a transistor.
4. The electronic component package structure according to any one of claims 1 to 3, wherein the electronic component is connected to a pin or other electronic component through a conductor, and the stress buffer layer covers a surface of the electronic component.
5. The electronic component package structure of claim 1, wherein the moisture absorption rate of the stress buffer layer is less than 0.03%.
6. The electronic component packaging structure of claim 1, wherein the stress buffer layer is formed by curing a polyimide material.
7. The electronic component package structure of claim 1, wherein the stress buffer layer has a thickness of 200 μm or less.
8. The electronic component package structure of claim 1, wherein the protective layer is manufactured by a plastic sealing, a ceramic sealing and/or a gold sealing process.
9. A packaging method comprising the electronic component packaging structure of any one of claims 1 to 8, wherein the packaging process comprises the following steps:
step A: covering the stress buffer layer outside the electronic element;
and B: covering a protective layer outside the stress buffer layer, wherein the stress buffer layer is arranged between the electronic element and the protective layer.
10. The method of claim 9, wherein step a is preceded by connecting the electronic component to the pin or other electronic component via the conductor.
11. The packaging method according to claim 9 or 10, wherein the stress buffer layer is formed by segmented thermal curing of a polyimide material.
12. The method of claim 11, wherein the polyimide curing process comprises the steps of:
step a: heating the chip covered with the polyimide to 100 ℃ from normal temperature, and heating at the speed of 2.5 ℃/m22 to heat 25m 22-35 m 22;
step b: placing the mixture in an environment at 100 ℃ and 55m 22-65 m 22;
step c: heating the mixture from 100 ℃ to 250 ℃, and heating the mixture at a speed of 5 ℃/m22 to heat the mixture to 25m 22-35 m 22;
step d: placing the mixture in an environment with the temperature of 250 ℃ and the thickness of 55m 22-65 m 22;
step e: and cooling from 250 ℃ to normal temperature, wherein 55m 22-65 m22 is needed, and the curing process is finished.
CN201810763291.8A 2018-07-11 2018-07-11 Electronic component packaging structure and packaging method Pending CN110718509A (en)

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CN1172345A (en) * 1996-07-30 1998-02-04 Lg半导体株式会社 Crack-resistant semiconductor package and fabrication method thereof and fabrication apparatus thereof
CN101116184A (en) * 2005-03-25 2008-01-30 住友电木株式会社 Semiconductor device, resin composition for buffer coating, resin composition for die bonding, and resin composition for encapsulation
CN201466021U (en) * 2009-04-03 2010-05-12 晶诚（郑州）科技有限公司 Lead frame-packaged type semiconductor device
CN208507648U (en) * 2018-07-11 2019-02-15 珠海格力电器股份有限公司 A kind of electronic element packaging structure and semiconductor devices

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