JP2013149876A - Package on package type semiconductor device and manufacturing method of the same - Google Patents
Package on package type semiconductor device and manufacturing method of the same Download PDFInfo
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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- H01L2224/45099—Material
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract
Description
本発明は、小型化、高密度実装を可能にするパッケージオンパッケージを構成する半導体装置の実装構造に係り、特に、高信頼性が必要とされる車載用途に好適な半導体装置に関する。 The present invention relates to a mounting structure of a semiconductor device that constitutes a package-on-package that enables downsizing and high-density mounting, and particularly relates to a semiconductor device suitable for in-vehicle use that requires high reliability.
電子機器の小型化と高機能化に伴い、それに使用される半導体装置は、高密度実装、高速動作が要求されている。 Along with the downsizing and higher functionality of electronic devices, semiconductor devices used for them are required to have high-density mounting and high-speed operation.
半導体装置の高密度実装に関して、半導体パッケージの実装方式でみると、ＤＩＰ（Dual In-Line Package）に代表されるピン挿入実装型からＱＦＰ（Quad Flat Package）に代表される表面実装型、ＢＧＡ（Ball Grid Array）に代表されるエリアアレイ実装型へと変遷し、さらに、現在は、ＰｏＰ（Package on Package）やＳｉＰ（Sytem in Package）に代表されるような３次元実装が実施されている。３次元実装は、平面的な実装から、縦方向に立体的に実装することで、実装密度の向上と信号配線長の短縮による動作の高速化を図ることができる。 Regarding the high-density mounting of semiconductor devices, in terms of the mounting method of the semiconductor package, from the pin insertion mounting type represented by DIP (Dual In-Line Package) to the surface mounting type represented by QFP (Quad Flat Package), BGA ( Transition to an area array mounting type represented by Ball Grid Array), and three-dimensional mounting as represented by PoP (Package on Package) and SiP (Sytem in Package) is currently being implemented. In the three-dimensional mounting, the mounting density can be improved and the operation speed can be increased by shortening the signal wiring length by mounting in three dimensions in the vertical direction from planar mounting.
複数の機能を集約し、１チップにしたシステムＬＳＩに対して、ＰｏＰやＳｉＰは、複数の半導体素子を任意に組み合わせることができ、多様化する市場ニーズへの対応するための開発期間の短縮や、すでに量産されている半導体素子を使用することにより、コストの低減が可能であるとう利点を有している。 For system LSIs that integrate multiple functions into a single chip, PoP and SiP can arbitrarily combine multiple semiconductor elements, shortening the development period to respond to diversifying market needs The use of semiconductor elements that are already mass-produced has the advantage that the cost can be reduced.
したがって、製品サイクルが短く、小型・軽量化が必要な携帯電話等の民生機器にはよく使用されている。 Therefore, it is often used in consumer devices such as mobile phones that require a short product cycle and need to be small and light.
ところで、半導体パッケージを積層して、ＰｏＰ構造を構成する場合、積層されたパッケージ間を電気的に接続する手法の一つには、半田ボールによる接続がある。半田ボールによる接続は、ワイヤボンディングを使った接続手法と比較し、配線長を短くできるため、高速動作や小型化には有利である。 Incidentally, when a PoP structure is formed by stacking semiconductor packages, one method for electrically connecting the stacked packages is connection by solder balls. Compared with a connection method using wire bonding, the connection by solder balls is advantageous for high-speed operation and miniaturization because the wiring length can be shortened.
しかし、かかる構造は、基板、半導体素子、封止樹脂等の異種材料の積層構造であるため、各材料間の線膨張係数差に起因した熱応力による歪が、半田ボールの接続箇所にかかることによって、クラックの発生や断線といった接合信頼性が悪いことが問題になることがあった。接合信頼性を高める手段として、半田ボールの接合箇所の隙間を樹脂組成物で封止し、接合部の接合信頼性を向上させるアンダーフィル技術が広く知られている（特許文献１）。 However, since such a structure is a laminated structure of different materials such as a substrate, a semiconductor element, and a sealing resin, distortion due to thermal stress due to a difference in linear expansion coefficient between the materials is applied to the connection point of the solder ball. As a result, poor bonding reliability such as generation of cracks and disconnection may be a problem. As a means for improving the bonding reliability, an underfill technique is widely known in which a gap between solder ball bonding portions is sealed with a resin composition to improve the bonding reliability of a bonded portion (Patent Document 1).
さらに、半導体パッケージの放熱性向上の観点から、発生する熱を放熱させるため放熱構造にするのが一般的であり、大電流を通電するような発熱の量の大きなパワー系の素子には有効である。これは、素子の上方もしくは下方の少なくともどちらか一方に、半導体素子が発熱する熱を逃がす放熱経路を形成することが実施されている。素子の上方に放熱経路を設けた例として特許文献２には、発熱する素子の上に熱伝導率の高いグリースや接着剤を塗布して、ヒートシンクとなる冷却部材と半導体素子を接着する構造がある。 Furthermore, from the viewpoint of improving the heat dissipation of the semiconductor package, it is common to use a heat dissipation structure to dissipate the generated heat, which is effective for power-related elements that generate a large amount of heat and conduct a large current. is there. This is performed by forming a heat dissipation path for releasing the heat generated by the semiconductor element at least one of the upper and lower sides of the element. As an example in which a heat dissipation path is provided above the element, Patent Document 2 has a structure in which a grease or an adhesive having high thermal conductivity is applied on a heat generating element to bond a cooling member serving as a heat sink and the semiconductor element. is there.
素子の下方に放熱経路を設けた例として特許文献３には、半導体素子を搭載する配線基板にヒートシンクを半田や熱伝導性の接着剤により搭載している。配線基板には熱伝導材を充填した貫通孔が有り、半導体素子とヒートシンクの間に放熱経路を形成している。 As an example in which a heat dissipation path is provided below the element, in Patent Document 3, a heat sink is mounted on a wiring board on which a semiconductor element is mounted by solder or a heat conductive adhesive. The wiring board has a through hole filled with a heat conductive material, and forms a heat dissipation path between the semiconductor element and the heat sink.
さらに、特許文献４、５には、半導体装置において、ヒートシンクとなる金属部材に直接半導体素子や電子部品を実装する構造が開示されている。 Further, Patent Documents 4 and 5 disclose a structure in which a semiconductor element and an electronic component are directly mounted on a metal member serving as a heat sink in a semiconductor device.
民生用途に限らず、車載用の電子制御モジュール例えばＥＣＵ（エンジンコントロールユニット）においても小型化が要求されている。ＥＣＵの筐体のサイズは、電子回路の規模で決まるといっても過言ではなく、ＥＣＵの小型化を実現するには、電子回路の高密度実装を可能にするＰｏＰやＳｉＰの実装技術が必要とされる。 There is a demand for downsizing not only in consumer applications but also in in-vehicle electronic control modules such as ECUs (engine control units). It is not an exaggeration to say that the size of the ECU housing is determined by the scale of the electronic circuit. In order to achieve a smaller ECU, PoP or SiP mounting technology that enables high-density mounting of the electronic circuit is required. It is said.
しかし、ＥＣＵのような車載用電子制御モジュールは、その設置場所が車室内からエンジンルーム内、さらには、エンジン直付けが求められ、環境温度が厳しくなっている。したがって、半導体素子を３次元的に積層してＰｏＰ構造にするには、高い接続信頼性が求められるのである。特許文献１にあるアンダーフィル技術により、半田ボールの隙間を樹脂組成物で埋める方法は、半田ボールの接続箇所が狭ピッチになると、隙間に均一に充填することが難しく、製造プロセスに課題があった。 However, an in-vehicle electronic control module such as an ECU is required to be installed in the engine compartment from the vehicle interior, and further directly attached to the engine, and the environmental temperature is severe. Therefore, high connection reliability is required to three-dimensionally stack semiconductor elements to form a PoP structure. In the method of filling the gap between the solder balls with the resin composition by the underfill technique disclosed in Patent Document 1, it is difficult to uniformly fill the gap when the connection locations of the solder balls are narrow, and there is a problem in the manufacturing process. It was.
また、半田リフロー時の半田ボールが一度溶融したときに潰れてしまい、積層した半導体装置間の高さを一定に確保することが難しかった。 Further, the solder balls during solder reflow are crushed once melted, and it has been difficult to ensure a constant height between the stacked semiconductor devices.
さらに、ＥＣＵの電子回路は、発熱の小さい小信号系回路と発熱の大きなパワー系の回路からなり、発熱の大きなパワー系の素子と発熱の小さい小信号系素子を組み合わせてＰｏＰ構造にするには、放熱構造を設ける必要がある。 Further, the electronic circuit of the ECU is composed of a small signal system circuit that generates a small amount of heat and a power system circuit that generates a large amount of heat. It is necessary to provide a heat dissipation structure.
特許文献２、３のようにヒートシンクとなる冷却部材を設けるには、構造とプロセスが複雑になることが課題である。また、冷却部材を接着するときに使用する接着剤は、熱抵抗が増大するので厚さや、ボイドの管理が必要となる。また、特許文献４、５は、複数の入出力回路を有し、外部入出力端子が数百ピンを超えるような場合は想定されていない。 In order to provide a cooling member serving as a heat sink as in Patent Documents 2 and 3, the problem is that the structure and process are complicated. Moreover, since the thermal resistance increases, the adhesive used when bonding the cooling member needs to manage the thickness and voids. Further, Patent Documents 4 and 5 have a plurality of input / output circuits, and it is not assumed that the external input / output terminals exceed several hundred pins.
本発明はこうした課題を鑑みてなされたものであり、その目的は、ＰｏＰ構造を有する半導体装置の製造を容易にし、過酷な使用環境である車載用途においても、使用可能な高信頼なＰｏＰ型半導体装置を提供することにある。 The present invention has been made in view of these problems, and an object of the present invention is to make it easy to manufacture a semiconductor device having a PoP structure, and to use a highly reliable PoP type semiconductor that can be used even in an in-vehicle application that is a severe usage environment. To provide an apparatus.
上記課題を解決するために、本発明では、複数の半導体装置を平面方向および高さ方向に立体的に積層して、前記複数の半導体装置を電気的に接続したパッケージオンパッケージ型半導体装置であって、前記複数の半導体装置は、第一の半導体装置と第二の半導体装置とを有し、前記第一の半導体装置は、パッケージ樹脂の底面に接続端子を有するエリアアレイ型表面実装パッケージであり、前記底面と対抗する面には、外部接続用のリードフレームの一部が前記パッケージ樹脂より露出するよう埋没しており、前記リードフレームの露出面には、前記第二の半導体装置が搭載され、前記第一の半導体装置と前記第二の半導体装置は前記パッケージ樹脂により電気的に絶縁されていることを特徴とするようパッケージオンパッケージ型半導体装置を構成する。 In order to solve the above problems, the present invention provides a package-on-package semiconductor device in which a plurality of semiconductor devices are three-dimensionally stacked in a planar direction and a height direction, and the plurality of semiconductor devices are electrically connected. The plurality of semiconductor devices include a first semiconductor device and a second semiconductor device, and the first semiconductor device is an area array type surface mount package having a connection terminal on a bottom surface of a package resin. A part of the lead frame for external connection is buried on the surface facing the bottom surface so as to be exposed from the package resin, and the second semiconductor device is mounted on the exposed surface of the lead frame. The package-on-package semiconductor, wherein the first semiconductor device and the second semiconductor device are electrically insulated by the package resin. To configure the location.
以上のように、本発明によれば、ＰｏＰ構造を有する半導体装置の製造を容易にし、過酷な使用環境である車載用途においても、放熱性、接続信頼性に優れる高信頼なＰｏＰ型半導体装置を提供できる。 As described above, according to the present invention, a highly reliable PoP type semiconductor device that facilitates the manufacture of a semiconductor device having a PoP structure and is excellent in heat dissipation and connection reliability even in an in-vehicle application that is a severe use environment. Can be provided.
以下、本発明である半導体装置の実装構造の実施例を図面を参照しながら説明する。先ず、本発明に係わる第１の実施例を、図１、図２、図８を用いて説明する。 Embodiments of a semiconductor device mounting structure according to the present invention will be described below with reference to the drawings. First, a first embodiment according to the present invention will be described with reference to FIGS.
図１は、本発明に係る半導体装置の実施例１の外観を示す鳥瞰図であり、図２は図１に示される第一の半導体装置１の内部の一部を示す一部断面図である。実施例１の半導体装置の構成は、大きくは、パッケージの底面に接続端子を有するエリアアレイ型表面実装パッケージの第一の半導体装置１と、第一の半導体装置１のパッケージ樹脂３より露出するよう埋没したリードフレーム４と、リードフレーム４上に搭載された第二の半導体装置２とで構成されている。実施例１の半導体装置の製造工程を図８の実施例１の半導体装置の製造工程を示す概略図により説明する。 FIG. 1 is a bird's-eye view showing an appearance of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a partial cross-sectional view showing a part of the inside of the first semiconductor device 1 shown in FIG. The configuration of the semiconductor device of Example 1 is roughly exposed from the first semiconductor device 1 of the area array type surface mount package having the connection terminals on the bottom surface of the package and the package resin 3 of the first semiconductor device 1. The lead frame 4 is buried and the second semiconductor device 2 is mounted on the lead frame 4. The manufacturing process of the semiconductor device of Example 1 will be described with reference to the schematic diagram showing the manufacturing process of the semiconductor device of Example 1 shown in FIG.
始めに、図８の８−Ａに示すように、第一の半導体装置１を製造すべく、ベアチップ７、とチップコンデンサ９、または、チップ抵抗からなる受動素子を高温半田や銀ペーストのような導電性ペーストによりインタポーザ５に実装する。ベアチップ７には、外部と電気的に接続するためのＡｕワイヤ８によるボンディングを行う。 First, as shown in 8-A of FIG. 8, in order to manufacture the first semiconductor device 1, a passive element including a bare chip 7 and a chip capacitor 9 or a chip resistor is used as a high temperature solder or a silver paste. The interposer 5 is mounted with a conductive paste. The bare chip 7 is bonded by an Au wire 8 for electrical connection to the outside.
なお、高温半田としたのは、この後工程で、第一の半導体装置１の半田ボール６の接続のために再度リフロー工程を通すため、鉛フリーのリフロープロファイルの最高温度以上の融点を有する半田でないと、再び溶融してしまうためである。従って、２４０℃以上の融点を有する半田であればよく、１度硬化すると不溶である熱硬化性樹脂組成物からなる銀ペーストのような導電ペーストでもよい。 Note that the high-temperature solder is a solder having a melting point equal to or higher than the maximum temperature of the lead-free reflow profile because the reflow process is performed again for the connection of the solder balls 6 of the first semiconductor device 1 in the subsequent process. Otherwise, it will melt again. Therefore, it may be a solder having a melting point of 240 ° C. or higher, and may be a conductive paste such as a silver paste made of a thermosetting resin composition that is insoluble once cured.
インタポーザ５は、厚さ０.６mmの４層のビルドアップのガラス−エポキシ基板を用いたが、他の樹脂系の有機基板、セラミック基板のような無機基板、金属基板のように金属に絶縁層を貼り合わせたものでもよく、材質や大きさは特に限定されるものではない。 The interposer 5 used was a 0.6 mm thick four-layer glass-epoxy substrate with a thickness of 0.6 mm, but other resin-based organic substrates, inorganic substrates such as ceramic substrates, and metal insulating layers such as metal substrates. The material and size are not particularly limited.
続いて、図８の８−Ｂに示すように、第一の半導体装置１を厚さ０.６４mmの銅合金からなるリードフレーム４と一体でトランスファモールド成形による片面封止を行う。リードフレーム４は銅、銅合金、鉄合金からなるものを使用すればよく、樹脂との密着性をあげるため、化学的なエッチング処理により表面を粗化している。封止する成形方法は、樹脂の流動するランナー部分が無く、余分な樹脂が出ないコンプレッションモールドでも行うことができる。パッケージ樹脂３は熱硬化性樹脂組成物であり、樹脂成分のうち７０重量％以上の無機質フィラを含むエポキシ系複合材料である。 Subsequently, as shown in FIG. 8B, the first semiconductor device 1 is integrally sealed with a lead frame 4 made of a copper alloy having a thickness of 0.64 mm by one-side sealing by transfer molding. The lead frame 4 may be made of copper, a copper alloy, or an iron alloy. The surface of the lead frame 4 is roughened by a chemical etching process in order to improve adhesion to the resin. The molding method for sealing can be performed by a compression mold in which there is no runner portion through which the resin flows and no excess resin is produced. The package resin 3 is a thermosetting resin composition, and is an epoxy-based composite material containing 70% by weight or more of inorganic fillers among the resin components.
このパッケージ樹脂３は、モールド成形前（常温）は固形、液状の何れのものでも良く、成形方法に応じて使い分ければ良い。パッケージ樹脂３の物性値は、モールド成形時の反りを低減するため、硬化収縮率の小さなものが好適である。 The package resin 3 may be either solid or liquid before molding (normal temperature), and may be properly used depending on the molding method. The physical property value of the package resin 3 is preferably a material having a small curing shrinkage rate in order to reduce warpage during molding.
また、パッケージ樹脂３の硬化後に半田リフロープロセスを通すので、ガラス転移温度が高く、吸水率が低いものが良い。本実施例で使用したパッケージ樹脂３の物性値は、１７５℃での硬化時の硬化収縮率が０.１％、硬化後のガラス転移温度が１７５℃、硬化後の飽和吸水率が０.３５％である。 Moreover, since the solder reflow process is passed after the package resin 3 is cured, it is preferable that the glass transition temperature is high and the water absorption is low. The physical properties of the package resin 3 used in this example are 0.1% for the cure shrinkage at 175 ° C., 175 ° C. for the glass transition temperature after cure, and 0.35 for the saturated water absorption after cure. %.
トランスファモールド成形は、１７５℃の金型温度内に、第一の半導体装置１とリードフレーム４をセットし、成形時間２分、成形圧力１０ＭＰａの条件で行い、離型後、１８０℃で５時間、恒温槽内に成形体を置いてアフターキュアを行う。 Transfer molding is performed by setting the first semiconductor device 1 and the lead frame 4 within a mold temperature of 175 ° C. under conditions of a molding time of 2 minutes and a molding pressure of 10 MPa, and after mold release, at 180 ° C. for 5 hours. After-cure is performed by placing the molded body in a thermostatic bath.
インサート成形は、モールドの金型構造が複雑になるが、耐熱性が１７０℃以上ある熱剥離シートを使用して、リードフレーム４を上金型に貼り付けておけば簡易に成形できる。成形後にリードフレーム４上に流動した樹脂が流れ込むことがあるが、その場合は樹脂を研磨してリードフレーム４の表面を露出させる。 Although insert molding complicates the mold structure of the mold, it can be easily molded by sticking the lead frame 4 to the upper mold using a heat release sheet having a heat resistance of 170 ° C. or higher. Resin that has flowed onto the lead frame 4 may flow after molding, but in this case, the resin is polished to expose the surface of the lead frame 4.
なお、図８では１製品の状態で図示してあるが、インタポーザ５およびリードフレーム４は、半導体のＭＡＰ（Mold Array Package）方式のように、１度の成形で複数の成形体ができる複数個取りにすることで、生産性の向上、製造コストの低減を図ることができる。 Although shown in FIG. 8 in the state of one product, the interposer 5 and the lead frame 4 can be formed into a plurality of molded bodies by a single molding as in a semiconductor MAP (Mold Array Package) system. By taking it in, it is possible to improve productivity and reduce manufacturing costs.
続いて、図８の８−Ｃに示すように、リードフレーム４の外部リード１０を曲げる工程であり、曲げ後、半田接合箇所には半田の濡れ性を向上させるため、Ｎｉ（厚さ１μｍ以上）めっきにＳｎめっき（厚さ８μｍ）処理を施す。 Subsequently, as shown in 8-C of FIG. 8, the external lead 10 of the lead frame 4 is bent, and after the bending, Ni (thickness of 1 μm or more) is used to improve the solder wettability at the solder joint portion. ) Sn plating (thickness: 8 μm) is applied to the plating.
そして、図８の８−Ｄに示すように、インタポーザ５に半田ボール６を搭載し、第一の半導体装置１が完成する。半田ボール６はＳｎ−Ａｇの鉛フリーの半田ボールで直径が７５０μｍである。半田ボール数は一個当たり２２５個であるが、回路の入出力数に応じた半田ボールを搭載すればよい。 Then, as shown in 8-D of FIG. 8, the solder ball 6 is mounted on the interposer 5 to complete the first semiconductor device 1. The solder ball 6 is a Sn-Ag lead-free solder ball having a diameter of 750 μm. The number of solder balls is 225 per one, but it is sufficient to mount solder balls according to the number of input / output of the circuit.
次に、リードフレーム４に鉛フリーの半田ペーストを塗布後、図８の８−Ｅに示すように第二の半導体装置２を搭載する工程からなる。 Next, a lead-free solder paste is applied to the lead frame 4 and then the second semiconductor device 2 is mounted as shown by 8-E in FIG.
第二の半導体装置２は、発熱量の大きいパワー系の半導体素子で、スイッチング素子であるＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）、ＩＧＢＴ（Insulated Gate Bipolar Transistor）等のトランジスタ、もしくは、ダイオードと、これら素子から過電圧保護をするツェナーダイオードが、少なくとも１つ以上実装される。実施例１では、ＭＯＳＦＥＴ２ａが２個とツェナーダイオード２ｂが２個搭載されている。第二の半導体装置２は、予めパッケージングされた半導体素子を搭載することができるため、第二の半導体装置２はモールド成形の必要が無い。 The second semiconductor device 2 is a power-type semiconductor element that generates a large amount of heat and is a switching element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), or a diode. At least one Zener diode that performs overvoltage protection from these elements is mounted. In the first embodiment, two MOSFETs 2a and two Zener diodes 2b are mounted. Since the second semiconductor device 2 can be mounted with prepackaged semiconductor elements, the second semiconductor device 2 does not need to be molded.
これら第二の半導体装置２から発生する熱は、リードフレーム４へ直接広がるため、搭載するリードフレーム４の表面積は、大きくすることで放熱効果は高まる。図２に示す如く、ＭＯＳＦＥＴ２ａのゲート電極部は、ヒートシンク２ａ−１がついており、ＭＯＳＦＥＴ２ａのゲート電極部と接合するリードフレーム４の接合箇所は、可能な限り表面積を大きくしている。 Since the heat generated from the second semiconductor device 2 spreads directly to the lead frame 4, increasing the surface area of the mounted lead frame 4 increases the heat dissipation effect. As shown in FIG. 2, the gate electrode portion of the MOSFET 2 a is provided with a heat sink 2 a-1, and the joint portion of the lead frame 4 joined to the gate electrode portion of the MOSFET 2 a has a surface area as large as possible.
かかる工程によりできたパッケージオンパッケージ型半導体装置は、図８の８−Ｆに示すように、マザーボード１１に搭載する時のリフロー工程で、第二の半導体装置２と第一の半導体装置１の半田ボール６、リードフレーム４の外部リード１０を全て１回の同一プロセスにて接合可能である。これにより、製造時間の短縮を図ることが可能となる。 The package-on-package semiconductor device formed by such a process is a reflow process when it is mounted on the mother board 11 as shown in FIG. 8F, and the solder between the second semiconductor device 2 and the first semiconductor device 1 is used. The ball 6 and the external lead 10 of the lead frame 4 can all be joined by one and the same process. This makes it possible to shorten the manufacturing time.
この時、図９に示す如く、半田ボール６とマザーボード１１との接合高さＬは、外部リード１０との接合高さｈにより決まるため、半田ボールが潰れることなく、一定の接合高さを確保することが可能になるのである。 At this time, as shown in FIG. 9, since the joining height L between the solder ball 6 and the mother board 11 is determined by the joining height h with the external lead 10, the solder ball is not crushed and a certain joining height is secured. It becomes possible to do.
なお、外部リード１０とマザーボード１１の接合は、レーザー、スポット溶接などの接合方法でも良い。 The external lead 10 and the mother board 11 may be joined by a joining method such as laser or spot welding.
この場合、半田ボール６の接合は、溶融した半田の界面張力による接続箇所が自動で適正箇所に補正される、いわゆるセルフアライメント作用を利用するため、先ず、半田リフローを行い、半田ボールの接続が終了後に、外部リード１０の溶接を行う。外部リード１０の溶接後に半田リフローを行うと、セルフアライメント作用が阻害され、半田ボールが適正位置で接合ができない。 In this case, the solder ball 6 is joined by using a so-called self-alignment function in which the connection location due to the interfacial tension of the melted solder is automatically corrected to an appropriate location. After completion, the external lead 10 is welded. When solder reflow is performed after the external lead 10 is welded, the self-alignment action is hindered, and the solder balls cannot be joined at the proper positions.
なお、第一の半導体装置１と第二の半導体装置２とは、パッケージ樹脂３によって電気的に絶縁されるよう実装されている。リードフレーム４、半田ボール６がマザーボード１１と接合されることにより、第一の半導体装置１と第二の半導体装置２とは電気的に接続され、電子回路を形成する。 The first semiconductor device 1 and the second semiconductor device 2 are mounted so as to be electrically insulated by the package resin 3. By joining the lead frame 4 and the solder balls 6 to the mother board 11, the first semiconductor device 1 and the second semiconductor device 2 are electrically connected to form an electronic circuit.
本発明では、半田ボール６の接合信頼性を高めるため、半田ボール６と外部リード１０がマザーボード１１と接合している。かかる構造により、外部応力や振動に対して、強い構造としている。従って、リードフレーム４の外部リード１０は、パッケージの対向方向に少なくとも一対配置することで、接続信頼性を向上させることができる。半田ボール６をマザーボード１１へ接合した後に、最も外部応力がかかるのは、四隅箇所に配置された半田ボールである。従って、外部リード１０は、第一の半導体装置１の四隅箇所で接続、固定することが好ましい。 In the present invention, the solder ball 6 and the external lead 10 are bonded to the mother board 11 in order to increase the bonding reliability of the solder ball 6. With this structure, the structure is strong against external stress and vibration. Therefore, the connection reliability can be improved by arranging at least one pair of the external leads 10 of the lead frame 4 in the opposing direction of the package. After the solder ball 6 is joined to the mother board 11, it is the solder balls arranged at the four corners that are most subjected to external stress. Therefore, the external leads 10 are preferably connected and fixed at the four corners of the first semiconductor device 1.
次に、本発明に係わる第２の実施例を、図３、図４を用いて説明する。図３は、本発明に係る半導体装置の実施例２の外観を示す鳥瞰図である。図４は、図３に示される半導体装置の内部の一部を示す一部断面図である。実施例１との違いは、第二の半導体装置２がリードフレーム４の内側にフェイスダウンの状態で搭載していることである。これにより、第二の半導体装置２は第一の半導体装置１のパッケージ樹脂３に完全に埋没した状態である。 Next, a second embodiment according to the present invention will be described with reference to FIGS. FIG. 3 is a bird's-eye view showing the appearance of the semiconductor device according to the second embodiment of the present invention. 4 is a partial cross-sectional view showing a part of the inside of the semiconductor device shown in FIG. The difference from the first embodiment is that the second semiconductor device 2 is mounted face-down inside the lead frame 4. As a result, the second semiconductor device 2 is completely buried in the package resin 3 of the first semiconductor device 1.
パッケージ樹脂３により、第二の半導体装置２の半田接合箇所が拘束されるため、外部応力や機械振動の影響を低減することができ、その結果、第二の半導体装置２の半田接続信頼性の向上になる。ここで、例えば、放射ノイズ等の電磁波は、樹脂内部を透過する事ができるが、金属は遮蔽することができる。従って、リードフレーム４がある面方向からの電磁波は遮断することができるため、第一の半導体装置１と第二の半導体装置２への放射ノイズによる影響を軽減する効果が期待できる。 Since the solder joint location of the second semiconductor device 2 is constrained by the package resin 3, the influence of external stress and mechanical vibration can be reduced. As a result, the reliability of solder connection of the second semiconductor device 2 can be reduced. Become an improvement. Here, for example, electromagnetic waves such as radiation noise can pass through the inside of the resin, but metal can be shielded. Therefore, since the electromagnetic wave from the surface direction with the lead frame 4 can be blocked, an effect of reducing the influence of radiation noise on the first semiconductor device 1 and the second semiconductor device 2 can be expected.
本発明に係わる第２の実施例の製造方法は、実施例１との違いは、トランスファモールド成形時に、リードフレーム４にはすでに、第二の半導体装置２が搭載されていることであり、その他は実施例１と同じである。 The manufacturing method of the second embodiment according to the present invention is different from the first embodiment in that the second semiconductor device 2 is already mounted on the lead frame 4 at the time of transfer molding. Is the same as in Example 1.
次に、本発明に係わる第３の実施例を、図６、図７を用いて説明する。図６は、本発明に係る半導体装置の実施例３の外観を示す鳥瞰図であり、図７は、図６に示される半導体装置の封止樹脂で覆う工程を説明した図である。 Next, a third embodiment according to the present invention will be described with reference to FIGS. FIG. 6 is a bird's-eye view showing the appearance of the semiconductor device according to the third embodiment of the present invention, and FIG. 7 is a diagram illustrating a process of covering the semiconductor device shown in FIG. 6 with a sealing resin.
実施例１との違いは、図６、図７に示す如く、リードフレーム４の外部リード１０が無く、Ａｌワイヤ１２によってマザーボード１１と接合し、電気的につながっていることである。 The difference from the first embodiment is that, as shown in FIGS. 6 and 7, there is no external lead 10 of the lead frame 4, and the Al 11 is joined and electrically connected to the mother board 11 by the Al wire 12.
Ａｌワイヤ１２は、直径が５００μｍのＡｌワイヤであり、流れる電流によってＡｌワイヤ１２が溶断するので、流れる電流に応じＡｌワイヤのボンディング本数を決めればよい。 The Al wire 12 is an Al wire having a diameter of 500 μm, and the Al wire 12 is melted by the flowing current. Therefore, the number of Al wires bonded may be determined according to the flowing current.
なお、特に図示はしていないが、Ａｌワイヤボンディングを行うのに、ボンディング箇所はＮｉやＡｌ等からなるボンディングパッドをリードフレーム４に設けても良いし、リードフレーム４にＮｉやＡｕのめっきを施し、めっき部へダイレクトにボンディングを行うこともできる。 Although not specifically shown, in order to perform Al wire bonding, a bonding pad made of Ni, Al, or the like may be provided on the lead frame 4 for bonding, or Ni or Au is plated on the lead frame 4. It is also possible to bond directly to the plating part.
実施例３のワイヤボンディングを使用した接合は、接合信頼性をあげるために、マザーボード１１に搭載後、図７に示すごとくＡｌワイヤ１２を封止樹脂１３により覆う、樹脂封止を実施する。封止樹脂１３は第一の半導体装置１のパッケージ樹脂３と同じ、熱硬化性樹脂組成物で良いが、線膨張係数はＡｌワイヤ１２に略近い１６×１０-6／Ｋ程度のものが好ましい。線膨張係数の近いものを選定するのには、線膨張係数の差による熱応力を低減するためである。実際、線膨張係数が８×１０-6／Ｋ程度のものであると、熱応力により、Ａｌワイヤ部に樹脂が収縮する力が働き、Ａｌワイヤが断線してしまうのである。 In the bonding using the wire bonding of the third embodiment, in order to increase the bonding reliability, after mounting on the mother board 11, resin sealing is performed by covering the Al wire 12 with the sealing resin 13 as shown in FIG. 7. The sealing resin 13 may be the same thermosetting resin composition as the package resin 3 of the first semiconductor device 1, but preferably has a linear expansion coefficient of approximately 16 × 10 −6 / K which is substantially close to the Al wire 12. . The reason for selecting a material having a similar linear expansion coefficient is to reduce thermal stress due to the difference in linear expansion coefficient. In fact, if the linear expansion coefficient is about 8 × 10 −6 / K, a force that causes the resin to contract in the Al wire portion due to thermal stress acts, and the Al wire is disconnected.
なお、封止樹脂１３による樹脂封止方法は、トランスファモールド、コンプレッションモールドのような大型の成形機を使用したものでも良いが、ディスペンサで樹脂を塗布するだけのポッティング工法でも良い。 The resin sealing method using the sealing resin 13 may be a method using a large molding machine such as a transfer mold or a compression mold, but may be a potting method in which a resin is simply applied by a dispenser.
以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims.
なお、本発明の電子制御モジュールの実装構造は、例えば、車載用ＥＣＵとして用いられるものであるが、その他、電子制御用途であってもかまわない。 The electronic control module mounting structure of the present invention is used as, for example, an in-vehicle ECU, but may be used for electronic control.
また、本発明の電子制御モジュールの実装構造は、要旨を逸脱しない範囲内で種々の変更して実施することができる。例えば、第一の半導体装置１と第二の半導体装置２の積層構造であったが、任意の数が積層され構成されていても良い。 The electronic control module mounting structure of the present invention can be implemented with various modifications without departing from the scope of the invention. For example, the first semiconductor device 1 and the second semiconductor device 2 have a stacked structure, but any number may be stacked.
１ 第一の半導体装置
２ 第二の半導体装置
３ パッケージ樹脂
４ リードフレーム
５ インタポーザ
６ 半田ボール
７ ベアチップ
８ Ａｕワイヤ
９ チップコンデンサ
１０ 外部リード
１１ マザーボード
１２ Ａｌワイヤ
１３ 封止樹脂
DESCRIPTION OF SYMBOLS 1 1st semiconductor device 2 2nd semiconductor device 3 Package resin 4 Lead frame 5 Interposer 6 Solder ball 7 Bare chip 8 Au wire 9 Chip capacitor 10 External lead 11 Motherboard 12 Al wire 13 Sealing resin
Claims (12)
前記複数の半導体装置は、第一の半導体装置と第二の半導体装置とを有し、
前記第一の半導体装置は、パッケージ樹脂の底面に接続端子を有するエリアアレイ型表面実装パッケージであり、
前記底面と対抗する面には、外部接続用のリードフレームの一部が前記パッケージ樹脂より露出するよう埋没しており、
前記リードフレームの露出面には、前記第二の半導体装置が搭載され、
前記第一の半導体装置と前記第二の半導体装置は前記パッケージ樹脂により電気的に絶縁されていることを特徴とするパッケージオンパッケージ型半導体装置。 A package-on-package semiconductor device in which a plurality of semiconductor devices are three-dimensionally stacked in a planar direction and a height direction, and the plurality of semiconductor devices are electrically connected,
The plurality of semiconductor devices include a first semiconductor device and a second semiconductor device,
The first semiconductor device is an area array type surface mount package having a connection terminal on the bottom surface of the package resin,
In the surface facing the bottom surface, a part of the lead frame for external connection is buried so as to be exposed from the package resin,
The second semiconductor device is mounted on the exposed surface of the lead frame,
The package-on-package semiconductor device, wherein the first semiconductor device and the second semiconductor device are electrically insulated by the package resin.
前記複数の半導体装置は、第一の半導体装置と第二の半導体装置とを有し、
前記第一の半導体装置は、パッケージ樹脂の底面に接続端子を有するエリアアレイ型表面実装パッケージであり、
前記底面と対抗する面には、外部接続用のリードフレームの一部が前記パッケージ樹脂より露出するよう埋没しており、
前記リードフレームの前記パッケージ樹脂に埋没している側の面には、前記第二の半導体装置が搭載され、
前記第一の半導体装置と前記第二の半導体装置は前記パッケージ樹脂により電気的に絶縁されていることを特徴とするパッケージオンパッケージ型半導体装置。 A package-on-package semiconductor device in which a plurality of semiconductor devices are three-dimensionally stacked in a planar direction and a height direction, and the plurality of semiconductor devices are electrically connected,
The plurality of semiconductor devices include a first semiconductor device and a second semiconductor device,
The first semiconductor device is an area array type surface mount package having a connection terminal on the bottom surface of the package resin,
In the surface facing the bottom surface, a part of the lead frame for external connection is buried so as to be exposed from the package resin,
The second semiconductor device is mounted on the surface of the lead frame that is buried in the package resin,
The package-on-package semiconductor device, wherein the first semiconductor device and the second semiconductor device are electrically insulated by the package resin.
前記一方の面と外部接続用のリードフレームの一部とを一体でトランスファモールド、もしくは、コンプレッションモールドにより樹脂成形する第二の工程と、
前記インタポーザの他方の面に半田ボールを搭載する第三の工程と、
前記リードフレームの樹脂成形されていない露出面に第二の半導体装置を搭載する第四の工程と、
前記半田ボールと前記リードフレームとを同一のリフロー工程で外部基板へ接合する第五の工程と、を有するパッケージオンパッケージ型半導体装置の製造方法。 A first step of mounting a plurality of elements on one side of the interposer;
A second step of integrally molding the one surface and a part of the lead frame for external connection by transfer molding or compression molding;
A third step of mounting solder balls on the other surface of the interposer;
A fourth step of mounting the second semiconductor device on the exposed surface of the lead frame which is not resin-molded;
And a fifth step of joining the solder ball and the lead frame to an external substrate in the same reflow step.
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| JP2012010585A JP2013149876A (en) | 2012-01-23 | 2012-01-23 | Package on package type semiconductor device and manufacturing method of the same |
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| JP2012010585A JP2013149876A (en) | 2012-01-23 | 2012-01-23 | Package on package type semiconductor device and manufacturing method of the same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017038344A1 (en) * | 2015-09-04 | 2017-03-09 | 日立オートモティブシステムズ株式会社 | Semiconductor device, vehicle-mounted semiconductor device, and vehicle-mounted control device |
| US10049977B2 (en) | 2014-08-01 | 2018-08-14 | Qualcomm Incorporated | Semiconductor package on package structure and method of forming the same |
| WO2020222096A1 (en) * | 2019-05-02 | 2020-11-05 | Silanna Asia Pte Ltd | Lead frame package having conductive surface with integral lead finger |
| US12000857B2 (en) | 2021-02-25 | 2024-06-04 | Seiko Epson Corporation | Sensor module having conductive bonding members with varying melting points and young's moduli |
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2012
- 2012-01-23 JP JP2012010585A patent/JP2013149876A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10049977B2 (en) | 2014-08-01 | 2018-08-14 | Qualcomm Incorporated | Semiconductor package on package structure and method of forming the same |
| WO2017038344A1 (en) * | 2015-09-04 | 2017-03-09 | 日立オートモティブシステムズ株式会社 | Semiconductor device, vehicle-mounted semiconductor device, and vehicle-mounted control device |
| JPWO2017038344A1 (en) * | 2015-09-04 | 2018-03-22 | 日立オートモティブシステムズ株式会社 | Semiconductor device, in-vehicle semiconductor device, and in-vehicle control device |
| CN108028226A (en) * | 2015-09-04 | 2018-05-11 | 日立汽车系统株式会社 | Semiconductor device, vehicle-mounted semiconductor device and on-vehicle control apparatus |
| US11004762B2 (en) | 2015-09-04 | 2021-05-11 | Hitachi Automotive Systems, Ltd. | Semiconductor device, vehicle-mounted semiconductor device, and vehicle-mounted control device |
| WO2020222096A1 (en) * | 2019-05-02 | 2020-11-05 | Silanna Asia Pte Ltd | Lead frame package having conductive surface with integral lead finger |
| US10971434B2 (en) | 2019-05-02 | 2021-04-06 | Silanna Asia Pte Ltd | Lead frame package having conductive surface with integral lead finger |
| US11694945B2 (en) | 2019-05-02 | 2023-07-04 | Silanna Asia Pte Ltd | Lead frame package having conductive surfaces |
| US12000857B2 (en) | 2021-02-25 | 2024-06-04 | Seiko Epson Corporation | Sensor module having conductive bonding members with varying melting points and young's moduli |
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