CN218867083U

CN218867083U - Packaging body structure and chip device

Info

Publication number: CN218867083U
Application number: CN202223464877.5U
Authority: CN
Inventors: 谭小春
Original assignee: Hefei Silicon Microelectronics Technology Co ltd
Current assignee: Hefei Silicon Microelectronics Technology Co ltd
Priority date: 2022-12-26
Filing date: 2022-12-26
Publication date: 2023-04-14
Anticipated expiration: 2032-12-26

Abstract

The utility model discloses an encapsulation body structure and chip device, including the encapsulation body and chip, the pin department electric connection of chip has the circuit layer, the encapsulation body encapsulates chip and circuit layer, a side surface protrusion of the encapsulation body is provided with the pad for realize the inside and outside circuit connection of encapsulation body, the surface of chip is provided with the stress buffer layer, the surface package of stress buffer layer formation chip, the expansion coefficient of stress buffer layer is less than the expansion coefficient of the encapsulation body, with the stress of buffering the encapsulation body, stress buffer layer surface leveling, the utility model discloses the application is through forming one deck plane shape or wavy stress buffer layer on the surface of chip in advance before the encapsulation, stress buffer layer parcel chip surface, and has certain thickness, both can guarantee buffering stress protection chip, can reduce the warpage cost controllable again, can also guarantee mechanical strength simultaneously, maintains stable in structure, and stress buffering effect is good.

Description

Packaging body structure and chip device

Technical Field

The utility model discloses the application belongs to the chip package technology field, especially relates to a packaging body structure and chip device.

Background

The packaging is a rear-end processing and manufacturing procedure of semiconductor production, and mainly comprises the steps of cutting, adhering crystals, connecting circuits, encapsulating and forming an IC on a wafer processed by a front-end processing procedure, so as to protect a chip assembly and be used for the assembly and assembly process of a circuit board.

The packaging material is various, such as polymer material (plastic) or ceramic, more than 97% of the polymer material (plastic package) is Epoxy resin plastic package material, the Epoxy resin plastic package material is commonly used as semiconductor packaging agent due to excellent properties in aspects of high strength and high adhesive strength, thermal property, chemical resistance, processability, etc., the English name of the Epoxy resin plastic package material is Epoxy Molding Compound (EMC), the Epoxy resin is used as matrix resin, high-performance phenolic resin is used as curing agent, silicon powder and the like are added as fillers, and various additives are added to mix the powder plastic package material, the plastic package process is that EMC is extruded into a mold cavity by a transfer Molding method, the semiconductor chip and circuits in the semiconductor chip are embedded, and the semiconductor chip and the circuits are simultaneously cross-linked and cured to form a semiconductor device with certain structural appearance, the chip is directly contacted with the plastic package material, the expansion coefficient (about 26E-6/DEG C) of the plastic package material is larger than that the expansion coefficient of the chip is larger, when the injection Molding cooling or the temperature difference of the device use environment is larger, the chip warpage and even the chip is damaged, so that the problem that the EMC and the chip structure of the package body need to be protected by the chip needs to be solved.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems in the prior art, the utility model provides a packaging body structure and chip device.

In order to achieve the above object, the utility model discloses a packaging body structure that the application provided, including packaging body and chip, the pin department electric connection of chip has the circuit layer, packaging body encapsulates chip and circuit layer, a side surface protrusion of packaging body is provided with the pad for realize the inside and outside circuit connection of packaging body, the surface of chip is provided with the stress buffer layer, the stress buffer layer forms the surface package of chip.

Further, the expansion coefficient of the stress buffer layer is smaller than that of the packaging body so as to buffer the stress of the packaging body.

Furthermore, the stress buffer layer has a flat surface.

Furthermore, the surface of the stress buffer layer is wavy, and the contact area between the stress buffer layer and the packaging body is increased.

Furthermore, the stress buffer layer is made of insulating and heat dissipation materials and is formed in a spraying or injection molding mode, and the components of the stress buffer layer are the same.

A chip device comprises the packaging body structure.

The utility model discloses the application is through forming one deck plane shape or wavy stress buffer layer on the surface of chip in advance before the encapsulation, and stress buffer layer parcel chip surface just has certain thickness, both can guarantee to cushion the stress protection chip, and it is controllable to reduce the warpage cost again, can also guarantee mechanical strength simultaneously, maintains stable in structure, and the stress buffering effect strengthens.

Drawings

Fig. 1 is a cross-sectional view of a package structure and a chip device according to a first embodiment of the present invention;

fig. 2 is a cross-sectional view of a second embodiment of a package structure and a chip device according to the present invention;

fig. 3 is a process flow diagram of the present invention for a package structure and a chip device.

The symbols in the figure illustrate: package 1, chip 2, stress buffer layer 3, pad 4.

Detailed Description

In order to better understand the purpose, structure and function of the present invention, the following description will be made in detail with reference to fig. 1-3 for a package structure and a chip device according to the present invention.

In injection molding or in a chip device using environment, the influence of temperature change on the package is large, the temperature mainly influences the package through the difference of expansion coefficients, the expansion coefficient is a physical quantity representing the thermal expansion property of an object, namely, a physical quantity representing the increase degree of the length, the area and the volume of the object when the object is heated, the lower the expansion coefficient is, which shows that under the heated condition, the change of self volume expansion is small, the larger the thermal expansion coefficient is, the larger the thermal stress is, namely, the larger the force born on the unit area of the object is, and the unit of the thermal expansion coefficient is: 1/k or 1/DEG C, which represents the change of temperature per degree, the material volume is about 26E-6/DEG C, the expansion coefficient of the epoxy resin plastic packaging material with different proportions is about 26E-6/DEG C, which is read as minus 6 times 10, and represents the change of temperature per 1℃, the change of the object volume is equal to the minus 6 times 10 times the volume value at 0 ℃, the thermal expansion coefficient of the chip silicon is 2.5E-6/DEG C, which is read as minus 6 times 2.5 times 10, which represents the change of temperature per 1℃, the change of the object volume is equal to the minus 6 times 10 times the volume value at 0 ℃, the expansion coefficient of the epoxy resin plastic packaging material is greater than the expansion coefficient of the chip silicon, and the difference is large, the volume expansion change of the epoxy resin plastic packaging material is large due to the temperature difference when the injection molding is cooled or the device is used, the thermal stress is large, the chip is easy to be extruded, and the chip is damaged or the chip is easy to be damaged, and the chip is damaged or the chip is damaged.

Example 1

Please refer to fig. 1, fig. 1 is a product cross-sectional view of an embodiment one of the present invention, including the package body 1 and the chip 2, the pin of the chip 2 is electrically connected to the circuit layer, the package body 1 encapsulates the chip 2 and the circuit layer, a side surface of the package body 1 protrudes and is provided with the bonding pad 4 for realizing the circuit connection inside and outside the package body 1, the surface of the chip 2 is provided with the stress buffer layer 3, and the stress buffer layer 3 forms the surface package of the chip 2.

Referring to fig. 3, fig. 3 is a process flow diagram of a package structure and a chip device according to the present invention, which includes the following steps:

s1: after the chip 2 is pasted with a piece, a stress buffer layer 3 with a certain thickness is formed on the back surface of the chip 2 in a spraying or injection molding mode, and the stress buffer layer 3 forms a surface package of the chip 2;

s2: after the stress buffer layer 3 is solidified, the packaging body 1 is formed through plastic package;

s3: the packaging body 1 is exposed out of the chip pins, and then circuit connection is realized through a semiconductor layer-by-layer packaging process.

Referring to fig. 1 and S1, the mounting method of the chip 2 of the present invention includes but is not limited to flip-chip mounting, the structure of the package 1 of the present invention is suitable for multiple packaging types, and is also suitable for stacking or tiling packaging, the present invention uses flip-chip mounting as an example, and also uses only packaging of a single chip 2 as an example, and the process of flip-chip mounting is: the chip 2 after the ball is planted is inversely installed on a carrier plate, the ball planting is a common technical means in the field and is used for forming a chip pin, namely, the ball planting surface (active surface) of the chip 2 faces the carrier plate for installation, at the moment, the back surface and four side surfaces of the chip 2 are exposed, a layer of smooth stress buffer layer 3 is sprayed on the surface of the chip 2, the thickness of the stress buffer layer is 0.05-0.3 time of the thickness of the chip 2, the stress buffer layer 3 is taken as an example of 0.175 time of the thickness of the chip 2, the stress buffer layer 3 forms surface wrapping of the chip 2, the mechanical strength of the whole structure can be guaranteed through the thickness control, the cost is also controlled, the surface of the chip 2 is wrapped to buffer the stress in multiple directions, the stress buffer layer 3 wraps the chip 2 except at least one surface of the ball planting surface, the chip 2 is taken as an example of wrapping five surfaces of the chip 2 (the five surfaces are other five surfaces of the chip 2 except the ball planting surface, and a cross-sectional view only shows three surfaces).

The material of the stress buffer layer 3 includes but is not limited to organic silica gel, the basic structural unit of the organic silica gel product is composed of silicon-oxygen chain links, the side chain is connected with other various organic groups through silicon atoms, and compared with other high polymer materials, the most outstanding performance of the organic silica gel product is as follows: 1. the temperature resistance characteristic is high and low temperature resistance, the composite material can be used in a wide temperature range, and the change of chemical properties or physical and mechanical properties with the temperature is small; 2. the organic silicon has better thermal stability, irradiation resistance and weather resistance than other high polymer materials; 3. the electric insulation performance is excellent, and the organic silicon has excellent heat resistance and excellent water repellency, which guarantees high reliability of electric equipment in a wet condition; 4. physiologically inert, silicone based compounds are one of the most inactive compounds known; according to the application, the adopted organic silica gel has different expansion coefficients according to different raw material proportioning components, for example, the organic silica gel formed by adding a heat conducting agent, a coupling agent and the like is controlled to have the thermal expansion coefficient of about 5.0-8.0E-6/DEG C according to experiments, which is far smaller than that of an epoxy resin plastic package material, so that the thermal stability is good, and during the injection molding process, the stress buffer layer 3 can preferentially deform the chip silicon, absorb the deformation stress of the plastic package material and prevent the chip 2 from warping or extruding due to the deformation of the plastic package material; when the chip 2 device works, the temperature of the surface of the chip 2 rises, the stress buffer layer 3 deforms in preference to the plastic package material, the package body 1 is prevented from deforming and the stress of the structure is prevented from being absorbed, and meanwhile, the chip 2 device can also be used as a heat dissipation layer to play a role in heat dissipation of the structure of the package body 1.

Chip 2 means the wafer packaging body of integrated transistor back encapsulation, and chip 2 pin need set up quantity according to actual production's chip 2, and this application sets up eight, and the sectional view only sees four, and other four are sheltered from, and the one end of chip 2 pin is passed through tin melting and is handled, plates one deck tin on chip 2 pin of copper material promptly, and the flip-chip paster is accomplished through the solder paste welding to the back.

Referring to fig. 1 and S2, the organic silicon gel can be cured rapidly in a high temperature environment, and the stress buffer layer 3 is cured and then the whole is molded and encapsulated, the molding compound adopted in the present application is an epoxy resin molding compound, which has low cost and good curing performance, and the encapsulation body 1 is formed after baking and curing.

Referring to fig. 1 and S3, after the carrier is peeled off, the pins of the flip chip 2 are exposed outside the package 1 and flush with the bottom surface of the package 1, and then the package molding of the semiconductor chip device is realized through a common layer-by-layer packaging process in the semi-field, that is, the pins are electrically connected to the redistribution layer, the redistribution layer is electrically connected to the upper conductive posts, and then the conductive posts are packaged again and ground to expose the conductive posts, and the pads 4 of the upper package 1 are electroplated at the conductive posts for connection of the internal and external circuits of the package 1.

All steps that use electroplating process of this application, all be earlier through the photoetching technique of exposure, development at the surface formation electroplating protection, later rethread sputtering or the mode of heavy copper is waiting to electroplate regional formation metal seed layer, what the metal seed layer adopted of this application is the copper product matter, and the metal seed layer is for guaranteeing the cohesion between the metal of follow-up electroplating and the plastic envelope material, provides the adnexed surface of conducting ion for electroplating simultaneously, guarantees to electroplate the effect.

This application adopts and forms one deck stress buffer layer 3 through the surface at chip 2 in advance before the encapsulation, and stress buffer layer 3 wraps up 2 surfaces of chip, and has certain thickness, both can guarantee buffering stress protection chip 2, can reduce again that the warpage cost is controllable, can also guarantee mechanical strength simultaneously, maintains stable in structure.

A chip device comprises the packaging body structure.

Example 2

The process steps are the same, and the only difference is that after the chip 2 is inversely installed, the back surface and four side surfaces of the chip 2 are exposed, a wavy stress buffer layer 3 (shown in figure 2) is formed on the surface of the chip by injection molding, the formation of waves is ensured by adjusting the spraying angle and speed, the contact area between the stress buffer layer 3 and the packaging body 1 is increased, and the stress buffer effect is enhanced.

It is to be understood that the present invention has been described with respect to certain embodiments and that various changes, modifications, and equivalents may be made to the features and embodiments without departing from the spirit and scope of the present invention as defined by the appended claims. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, the present application is not intended to be limited to the particular embodiments disclosed herein, and all embodiments that fall within the scope of the claims are intended to be encompassed by the present application.

Claims

1. The utility model provides a packaging body structure, includes packaging body and chip, the pin department electric connection of chip has the circuit layer, packaging body encapsulates chip and circuit layer, one side surface protrusion of packaging body is provided with the pad for realize the inside and outside circuit connection of packaging body, its characterized in that, the surface of chip is provided with the stress buffer layer, the stress buffer layer forms the surface parcel of chip.

2. The package structure of claim 1, wherein the stress buffer layer has a coefficient of expansion less than a coefficient of expansion of the package to buffer stress of the package.

3. The package structure of claim 2, wherein the stress buffer layer has a flat surface.

4. The package structure of claim 2, wherein the stress buffer layer has a wavy surface, and the contact area between the stress buffer layer and the package is increased.

5. The package structure of claim 1, wherein the stress buffer layer is made of insulating and heat dissipating material and has the same composition, and the stress buffer layer is formed by spraying or injection molding.

6. A chip device comprising the package structure of any one of claims 1 to 5.