CN110707045A - 一种制作半导体元件的方法 - Google Patents
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Abstract
本发明公开一种制作半导体元件的方法。首先形成一凹槽于一基底内,然后形成一第一氧化层于该凹槽内,接着形成一硅层于该第一氧化层上,进行一氧化制作工艺将该硅层转换为一第二氧化层,再平坦化第二氧化层以及第一氧化层以形成一浅沟隔离。
Description
技术领域
本发明涉及一种制作半导体元件的方法,尤其是涉及一种制作动态随机存取存储器(Dynamic Random Access Memory,DRAM)元件的方法。
背景技术
随着各种电子产品朝小型化发展的趋势,动态随机存取存储器(DRAM)单元的设计也必须符合高集成度及高密度的要求。对于一具备凹入式栅极结构的DRAM单元而言,由于其可以在相同的半导体基底内获得更长的载流子通道长度,以减少电容结构的漏电情形产生,因此在目前主流发展趋势下,其已逐渐取代仅具备平面栅极结构的DRAM单元。
一般来说,具备凹入式栅极结构的DRAM单元会包含一晶体管元件与一电荷贮存装置,以接收来自于位线及字符线的电压信号。然而,受限于制作工艺技术之故,现有具备凹入式栅极结构的DRAM单元仍存在有许多缺陷,还待进一步改良并有效提升相关存储器元件的效能及可靠度。
发明内容
本发明揭露一种制作半导体元件的方法。首先形成一凹槽于一基底内,然后形成一第一氧化层于该凹槽内,接着形成一硅层于第一氧化层上,进行一氧化制作工艺将硅层转换为一第二氧化层,再平坦化第二氧化层以及第一氧化层以形成一浅沟隔离。
依据本发明一实施例,另包含形成硅层于第一氧化层上但不完全填满该凹槽。
依据本发明一实施例,另包含将该硅层转换为该第二氧化层并完全填满该凹槽。
依据本发明一实施例,另包含进行一原子沉积制作工艺以形成该第一氧化层。
依据本发明一实施例,其中该氧化制作工艺包含一现场蒸气成长(in-situ steamgeneration,ISSG)制作工艺。
依据本发明一实施例,其中该硅层的厚度低于该第一氧化层的厚度。
依据本发明一实施例,其中该第二氧化层的厚度高于该硅层的厚度。
依据本发明一实施例,其中该硅层包含一非晶硅层。
依据本发明一实施例,其中该第一氧化层以及该第二氧化层包含氧化硅。
附图说明
图1为本发明一实施例的动态随机存取存储器元件的俯视图;
图2至图6为图1中沿着切线AA’方向制作动态随机存取存储器元件的方法示意图。
主要元件符号说明
10 动态随机存取存储器元件 12 位线
14 字符线 16 基底
18 主动区(有源区) 20 存储器区
22 栅极 24 浅沟隔离
26 凹槽 28 凹槽
30 第一氧化层 32 硅层
34 氧化制作工艺 36 第二氧化层
40 第一凹槽 42 第二凹槽
44 氧化硅层 46 阻障层
48 导电层 50 第一栅极结构
52 第二栅极结构 54 硬掩模
具体实施方式
请参照图1至图5,图1至图5为本发明优选实施例制作一动态随机存取存储器元件的方法示意图,其中图1为俯视图,图2至图5显示图1中沿着切线AA’方向制作动态随机存取存储器元件的浅沟隔离的方法示意图。本实施例是提供一存储器元件,例如是具备凹入式栅极的动态随机存取存储器元件10,其包含有至少一晶体管元件(图未示)以及至少一电容结构(图未示),以作为DRAM阵列中的最小组成单元并接收来自于位线12及字符线14的电压信号。
如图1所示,动态随机存取存储器元件10包含一基底16,例如一由硅所构成的半导体基底,然后于基底16内形成有至少一浅沟隔离24,以于基底16上定义出多个主动区(active area,AA)18。此外,基底16上还定义有一存储器区20以及一周边区(图未示)。其中,动态随机存取存储器元件10的多个字符线(word line,WL)14与多个位线(bit line,BL)12较佳形成于存储器区20的基底16上而其他的主动元件等(未绘示)则可形成在周边区。需注意的是,为简化说明,本发明的图1仅绘示出位于存储器区20的元件上视图并省略了位于周边区的元件。
在本实施例中,存储器区20的各主动区18例如是相互平行地朝向一第一方向延伸,而字符线14或多条栅极22是形成在基底16内并穿越各主动区18及浅沟隔离24。具体来说,各栅极22是沿着不同于第一方向的一第二方向,例如Y方向延伸,且第二方向与第一方向相交并小于90度。
另一方面,位线12是相互平行地形成在基底16上沿着一第三方向,例如X方向延伸,并同样横跨各主动区18及浅沟隔离24。其中,第三方向同样是不同于第一方向,并且较佳是与第二方向垂直。也就是说,第一方向、第二方向及第三方向彼此都不同,且第一方向与第二方向及第三方向都不垂直。此外,字符线14两侧的主动区18内较佳设有接触插塞,例如包括位线接触插塞(bit line contact,BLC)(图未示)来电连接至各晶体管元件的源极/漏极区域(图未示)以及存储节点(storage node)接触插塞(图未示)来电连接一电容。
以下针对字符线14(或又称埋藏式字符线)之前浅沟隔离或隔离结构的制作进行说明。首先如图2所示,先形成至少一凹槽,例如凹槽26以及凹槽28于存储器区20的基底16内,然后进行一原子层沉积(atomic layer deposition,ALD)制作工艺或化学气相沉积(chemical vapor deposition,CVD)制作工艺以形成第一氧化层30于基底16表面及凹槽26、28内但不完全填满凹槽26、28。在本实施例中,第一氧化层30较佳由氧化硅所构成的且第一氧化层30的厚度较佳约介于50埃至90埃或更佳约70埃。
如图3所示,接着形成一硅层32于第一氧化层30上,其中硅层32较佳覆盖于第一氧化层30表面且同样不填满各凹槽26、28。在本实施例中,硅层32较佳包含一非晶硅层且硅层32的厚度较佳略低于第一氧化层30的厚度,其中硅层32的厚度较佳约介于20埃至40埃或更佳约30埃。
随后如图4所示,进行一氧化制作工艺34将硅层32转换为一第二氧化层36。在本实施例中,氧化制作工艺34较佳包含一现场蒸气成长(in-situ steam generation,ISSG)制作工艺,其中本阶段通过ISSG制作工艺通入氧气将硅层32转换为第二氧化层36的步骤较佳将所有的硅层32与氧气反应并转换为第二氧化层36。换句话说,经由ISSG制作工艺后已无任何硅层32留下且所形成的第二氧化层36较佳完全填满凹槽26、28并覆盖于第一氧化层30表面。在本实施例中,第二氧化层36与前述的第一氧化层30较佳包含相同材料,例如均由氧化硅所构成。然后进行一平坦化制作工艺,例如以化学机械研磨(chemical mechanicalpolishing,CMP)以及/或蚀刻制作工艺去除部分第二氧化层36以及部分第一氧化层30以形成浅沟隔离24于各凹槽内,其中此阶段的浅沟隔离24较佳约略切齐基底16表面。
之后可依据制作工艺需求进行后续字符线14(或又称埋藏式字符线)的制作。例如图5所示,可先利用蚀刻制作工艺同时去除部分浅沟隔离24以及浅沟隔离24旁的部分基底16形成第一凹槽40与第二凹槽42,其中第一凹槽40底部设有浅沟隔离24且浅沟隔离24上表面较佳略低于第二凹槽42底部或下表面。接着再利用一ALD制作工艺、CVD制作工艺或ISSG制作工艺形成一氧化硅层44于第一凹槽40与第二凹槽42内。
然后如图6所示,依序形成一阻障层46以及一导电层48于第一凹槽40与第二凹槽42内并填满各凹槽,再进行一回蚀刻制作工艺去除部分导电层48、部分阻障层46以及部分氧化硅层44,使剩余的导电层48、阻障层46以及氧化硅层44略低于基底16上表面以形成第一栅极结构50于第一凹槽40内以及第二栅极结构52于第二凹槽42内,其中第一栅极结构50以及第二栅极结构52即构成图1的位线12。之后再形成一硬掩模54于第一栅极结构50与第二栅极结构52上方,并使硬掩模54上表面切齐基底12上表面。
在本实施例中,阻障层46可依据制作工艺或产品需求选用N型功函数金属层或P型功函数金属层,其中N型功函数金属层可选用功函数为3.9电子伏特(eV)~4.3eV的金属材料,如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等,但不以此为限。另外P型功函数金属层可选用功函数为4.8eV~5.2eV的金属材料,如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等,但不以此为限。导电层48可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide,CoWP)等低电阻材料或其组合。硬掩模54则较佳由例如氮化硅等介电材料所构成。
之后可依据制作工艺需求进行一离子注入制作工艺,以于第一栅极结构50或第二栅极结构52两侧的基底16内形成一掺杂区(图未示),例如一轻掺杂漏极或源极/漏极区域。最后进行接触插塞制作工艺,例如可分别于第二栅极结构42两侧形成位线接触插塞电连接源极/漏极区域与后续所制作的位线,以及形成存储节点接触插塞同时电连接源极/漏极区域与后续所制作的电容。
综上所述,本发明主要在制备动态随机存取存储器元件的字符线之前先形成凹槽于基底内并形成第一氧化硅层于凹槽内,然后形成一硅层或更具体而言一非晶硅层于第一氧化硅层表面,利用ISSG制作工艺将所有非晶硅层转换为一第二氧化硅层,最后再平坦化部分第二氧化硅层与部分第一氧化硅层以形成浅沟隔离。依据本发明的优选实施例此制作工艺方法除了可降低由氧化硅所构成的浅沟隔离中产生缝隙的机率,又可避免进行ISSG制作工艺时消耗过多由硅所构成的基底。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (9)
1.一种制作半导体元件的方法,包含:
形成凹槽于基底内;
形成第一氧化层于该凹槽内;
形成硅层于该第一氧化层上;
进行氧化制作工艺将该硅层转换为第二氧化层;以及
平坦化该第二氧化层以及该第一氧化层以形成浅沟隔离。
2.如权利要求1所述的方法,另包含形成该硅层于该第一氧化层上但不完全填满该凹槽。
3.如权利要求1所述的方法,另包含将该硅层转换为该第二氧化层并完全填满该凹槽。
4.如权利要求1所述的方法,另包含进行原子层沉积制作工艺以形成该第一氧化层。
5.如权利要求1所述的方法,其中该氧化制作工艺包含现场蒸气成长(in-situ steamgeneration,ISSG)制作工艺。
6.如权利要求1所述的方法,其中该硅层的厚度低于该第一氧化层的厚度。
7.如权利要求1所述的方法,其中该第二氧化层的厚度高于该硅层的厚度。
8.如权利要求1所述的方法,其中该硅层包含非晶硅层。
9.如权利要求1所述的方法,其中该第一氧化层以及该第二氧化层包含氧化硅。
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