CN110673016A - Wafer test card and wafer test method - Google Patents
Wafer test card and wafer test method Download PDFInfo
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- CN110673016A CN110673016A CN201910973753.3A CN201910973753A CN110673016A CN 110673016 A CN110673016 A CN 110673016A CN 201910973753 A CN201910973753 A CN 201910973753A CN 110673016 A CN110673016 A CN 110673016A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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Abstract
A wafer test card and a wafer test method are provided, wherein the wafer test card is used for detecting a wafer to be tested, and a pixel device is arranged in the wafer to be tested, and the wafer test card comprises: a substrate including a first region and a second region, the second region surrounding the first region, the second region including a logic region; a plurality of probes positioned on the surface of the first region; and the logic device is positioned in the logic area and is used for forming signal transmission with the pixel device. The wafer test card is adopted to carry out wafer test, so that the detection efficiency can be improved, and the damage can be reduced.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a wafer test card and a wafer test method.
Background
The manufacturing process of integrated circuits can be generally divided into wafer processing, wafer testing, packaging and final testing. Before the chip is packaged, an electrical performance test is usually performed on the integrated circuit on the wafer to determine whether the integrated circuit is good, and another electrical performance test is performed on the integrated circuit after the packaging process is completed to screen out a defective product caused by the poor packaging process, so as to further improve the yield of the final finished product. In the prior art, a wafer test card having a plurality of probes is generally used, the probes of the wafer test card are contacted with the integrated circuits of the wafer, and test signals are applied to the integrated circuits to determine whether the electrical performance of the integrated circuits is good.
In the field of semiconductor technology, a stacked image sensor is formed by bonding a logic wafer and a pixel wafer after they are separately manufactured, and since the logic wafer and the pixel wafer are separately manufactured, the manufacturing process is flexible and low in cost, and the stacked image sensor has the advantages of large available area of the wafers and integration of multifunctional wafers, and is favored.
However, the dark field and bright field yield detection of the stacked image sensor is required after the whole stacking process is completed, so that the conventional wafer test card cannot perform the dark field yield detection of the pixel wafer alone.
Disclosure of Invention
The invention provides a wafer test card and a wafer test method, aiming at improving the detection efficiency and reducing the loss.
In order to solve the above technical problem, a technical solution of the present invention provides a wafer test card for testing a wafer to be tested, where the wafer to be tested has a pixel device therein, the wafer test card including: a substrate including a first region and a second region, the second region surrounding the first region, the second region including a logic region; a plurality of probes positioned on the surface of the first region; and the logic device is positioned in the logic area and is used for forming signal transmission with the pixel device.
Optionally, the probe is electrically connected to the logic device.
Optionally, the second zone further comprises a detection zone having a detection device therein.
Optionally, the probe and the detection device are electrically connected.
Optionally, the number of the first areas is more than one, and the number of the logic areas is more than one; when the number of the first areas is more than two, and the number of the logic areas is more than two, the plurality of probes on the surface of one first area are electrically connected with the corresponding logic device in one logic area.
Optionally, the number range of the first areas is 1 to 100, and the number range of the logic areas is 1 to 100.
Optionally, the size range of the first region is 1 mm to 10 mm.
Optionally, the size range of the logic area is 1 mm to 10 mm.
Correspondingly, the technical scheme of the invention also provides a wafer testing method, which comprises the following steps: providing a wafer to be tested, wherein the wafer to be tested is provided with a pixel device; providing the wafer test card of any one of the above items; and contacting the probe with the wafer to be detected, so that the pixel device and the logic device are connected to form signal transmission.
Optionally, the wafer to be tested further includes: and a plurality of contact pads, one of which is electrically connected with a corresponding one of the probes.
Optionally, the wafer to be tested includes a pixel area and a peripheral area located around the pixel area; the pixel device is located in a pixel region, the contact pads are located in the peripheral region, and the contact pads surround the pixel region.
Optionally, the wafer to be tested includes a plurality of chip areas, and each chip area includes one pixel area and a peripheral area surrounding the pixel area; the wafer test card comprises a plurality of first areas and a plurality of logic areas, a plurality of probes on the surface of each first area are electrically connected with a plurality of contact pads in a corresponding peripheral area, and a logic device in each logic area is electrically connected with a pixel device in a corresponding pixel area.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the wafer test card provided by the technical scheme of the invention, the wafer test card is used for detecting a wafer to be tested, and a pixel device is arranged in the wafer to be tested. Since the second area of the wafer test card comprises: and the logic area is provided with logic devices. When the wafer test card is used for carrying out dark field yield measurement on a wafer to be tested, the logic device can be electrically connected with the pixel device to form signal transmission, so that the wafer test card can be used for detecting the wafer to be tested only with the pixel device, the detection efficiency is improved, and the cost is saved.
Furthermore, the wafer test card can be provided with a plurality of first areas and a plurality of logic areas, and the plurality of probes on the surface of one first area are electrically connected with the corresponding logic device in one logic area, so that the wafer test card can simultaneously carry out yield detection on a plurality of chip areas in the wafer to be detected at one time, thereby further improving the detection efficiency, saving the detection time and saving the cost.
In the wafer testing method provided by the technical scheme of the invention, as the pixel device is arranged in the wafer to be tested and the logic device is arranged in the wafer testing card, the pixel device is electrically connected with the logic device by contacting the probe with the wafer to be tested, so that signal transmission is formed between the pixel device and the logic device. And the signal can further pass through a detection device in the wafer test card to form a detection circuit, and the yield test of the wafer to be tested is realized by combining a detection program. The method is simple, and can improve the detection efficiency, save the detection time and save the cost.
Drawings
FIG. 1 is a schematic diagram of a wafer test card;
FIG. 2 is a schematic diagram illustrating a structure of a wafer to be tested according to an embodiment of the present invention;
FIGS. 3 and 4 are schematic structural diagrams of a wafer test card according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a wafer test card according to another embodiment of the present invention;
FIG. 6 is a flowchart illustrating a wafer testing method according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram illustrating a wafer test card testing a wafer to be tested according to an embodiment of the present invention.
Detailed Description
As described in the background, the conventional wafer test card has poor test efficiency.
The reason why the wafer test card has poor test efficiency will be described in detail with reference to the accompanying drawings, and fig. 1 is a schematic structural diagram of the wafer test card.
Referring to fig. 1, a wafer test card includes: a substrate 100, the substrate 100 including a first region a and a second region B, and the second region B surrounding the first region a; the surface of the first area A is provided with a plurality of probes 101; the second region B has a detection device (not shown in the figure) therein.
In the structure, the surface of the first area a is provided with a probe 101 for guiding the signal of the wafer to be tested to the second area B in the wafer test card. The second area B is internally provided with a detection device, and when the detection device detects a signal transmitted by the probe 101, the second area B is combined with a test program to read and judge the acquired signal, so that the dark field yield of the wafer to be tested is tested.
When the wafer to be tested is a stacked image sensor, the stacked image sensor is required to be a device formed after a stacking process, and the stacked image sensor is formed by bonding a pixel wafer and a logic wafer. Because the logic wafer and the pixel wafer are used together to form the complete image sensor, when the logic wafer and the pixel wafer are not subjected to the bonding process to form a wafer to be tested, the conventional wafer test card cannot perform yield test on the pixel wafer or the logic wafer independently.
However, the pixel wafer and the logic wafer need to be processed separately in different processes. When the process procedure of the pixel wafer is in a problem, after the process procedure of the logic wafer is required to be completed, the formed pixel wafer and the logic wafer are bonded to form a complete image sensor serving as a wafer to be tested, and the wafer test card is adopted to carry out a total test, so that the pixel wafer can be detected to have a problem, the dark field test efficiency is poor, and the detection time and the detection cost are correspondingly increased.
In order to solve the technical problem, an embodiment of the present invention provides a wafer test card for detecting a wafer to be tested, where the wafer to be tested has a pixel device therein, and the wafer test card includes: a substrate including a first region and a second region, the second region surrounding the first region, the second region including a logic region; a plurality of probes positioned on the surface of the first region; and the logic device is positioned in the logic area and is used for forming signal transmission with the pixel device. The wafer test card is adopted to carry out wafer test, so that the detection efficiency can be improved, and the loss is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 is a schematic structural diagram of a wafer to be tested according to an embodiment of the invention.
Referring to fig. 2, a wafer 300 to be tested, the wafer 300 to be tested has pixel devices (not shown in the figure).
In this embodiment, the pixel device may include a photodiode (not shown in the figure) and a pixel circuit, wherein the pixel circuit may include devices forming various appropriate transistors such as a selection transistor, a reset transistor, and a source follower transistor, and may include a transfer gate and a floating diffusion region, for example. Note that, in the present embodiment, the composition of a specific pixel circuit is not limited.
In this embodiment, the wafer 300 to be tested further includes: a plurality of contact pads 320.
The material of the contact pad 320 includes: one or more combinations of titanium, nickel, copper, tungsten, aluminum, titanium, silver, and tantalum.
The wafer 300 to be tested comprises a pixel area 301 and a peripheral area 302 positioned around the pixel area 301; the pixel device is located in the pixel region 301, the contact pads 320 are located in the peripheral region 302, and the contact pads 320 surround the pixel region 301.
In this embodiment, the wafer 300 to be tested includes a plurality of chip areas C, and each of the chip areas C includes one pixel area 301 and a peripheral area 302 surrounding the pixel area 301.
Fig. 3 and 4 are schematic structural diagrams of a wafer test card according to an embodiment of the invention.
Referring to fig. 3 and 4, fig. 4 is a schematic cross-sectional view of fig. 3 along a tangential direction of M-N, a wafer test card 200 for testing a wafer 300 to be tested, wherein the wafer 300 to be tested has pixel devices therein, and the wafer comprises: the substrate 210, the substrate 210 includes a first region I and a second region II, the second region II surrounds the first region I, and the second region II includes a logic region a; a plurality of probes 220 positioned on the surface of the first zone I; and the logic device 230 is positioned in the logic area A, and the logic device 230 is used for forming signal transmission with the pixel device.
In this embodiment, the substrate 210 is made of silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; in other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the probes 220 are electrically connected to a logic device 230.
Because the probes 220 are electrically connected with the logic devices 230, when the pixel devices in the wafer 300 to be tested are electrically connected with the probes 220, the pixel devices can be electrically connected with the logic devices 230, so that signal transmission is formed.
With continued reference to fig. 3 and 4, the second region II further includes a detection region B, and the detection region B has a detection device (not shown).
In this embodiment, the probe 220 and the sensing device are electrically connected.
Because the detection device is electrically connected with the probe 220, when the pixel device in the wafer 300 to be tested is contacted with the probe 220, a detection circuit is formed between the detection device and the pixel device, and by combining a test program, signals formed by the pixel device in the wafer 300 to be tested and the logic device 230 can be read and distinguished, so that an electrical test process is completed.
The number of the first areas I is more than one, and the number of the logic areas A is more than one; when the number of the first areas I is more than two, and the number of the logic areas a is more than two, the plurality of probes 220 on the surface of one first area I are electrically connected with the corresponding logic device in one logic area a.
The number range of the first areas is 1-100, and the number range of the logic areas is 1-100.
In this embodiment, the number of the first areas I is one, the number of the logic areas a is one, and the plurality of probes 220 on the surface of one first area I are electrically connected to the corresponding logic device 230 in one logic area a.
In other embodiments, the number of the logic areas is more than two, and the number of the logic areas is more than two.
The wafer test card 200 is used for detecting a wafer 300 to be tested, and the wafer 300 to be tested has a pixel device therein. Since the second region II of the wafer test card 200 includes: a logic area a, and logic devices 230 are provided in the logic area a. When the wafer test card 200 is used for performing dark field yield measurement on the wafer 300 to be tested, the logic device 230 can be electrically connected with the pixel device to form signal transmission, so that the wafer test card 200 can detect the wafer 300 to be tested only with the pixel device, thereby improving the detection efficiency and saving the cost.
The size range of the first zone is 1 mm to 10 mm.
The size range of the logic area is 1 mm-10 mm.
FIG. 5 is a schematic structural diagram of a wafer test card according to another embodiment of the present invention.
Referring to fig. 5, a wafer test card 400 is used for testing a wafer 300 to be tested, where the wafer 300 to be tested has pixel devices therein, and the wafer test card includes: a substrate (not shown), wherein the substrate comprises a first area I and a second area II, the second area II surrounds the first area I, and the second area II comprises a logic area A; a plurality of probes 420 positioned on the surface of the first zone I; and the logic device (not marked in the figure) is positioned in the logic area A and is used for forming signal transmission with the pixel device.
In this embodiment, the number of the first areas I is five, the number of the logic areas a is five, and the plurality of probes 420 on the surface of one of the first areas I are electrically connected to the corresponding logic device in one of the logic areas a.
Because the wafer test card 400 has a plurality of first areas I and a plurality of logic areas a, and the plurality of probes 420 on the surface of one first area I are electrically connected to the corresponding logic device in one logic area a, the wafer test card 400 can simultaneously perform yield detection on a plurality of chip areas 301 in the wafer 300 to be detected at one time, thereby further improving the detection efficiency, saving the detection time and saving the cost.
Fig. 6 is a flowchart illustrating a wafer testing method according to an embodiment of the invention.
Referring to fig. 6, a wafer testing method includes:
s1: providing a wafer to be tested, wherein the wafer to be tested is provided with a pixel device;
s2: providing the wafer test card;
s3; and contacting the probe with the wafer to be detected, so that the pixel device and the logic device are connected to form a signal.
The wafer testing method is described in detail below with reference to the accompanying drawings.
With continued reference to fig. 2, a wafer 300 to be tested is provided, wherein the wafer 300 to be tested has pixel devices therein.
The wafer 300 to be tested further includes: a plurality of contact pads 320.
The contact pads 320 are used for being electrically connected with the probes in the wafer test card in a subsequent step, so that the wafer test card is electrically connected with the contact pads 320 through the probes, and the wafer to be tested can be subjected to yield test.
With continued reference to fig. 3 and 4, the wafer test card 200 is provided.
The wafer test card 200 includes: the substrate 210, the substrate 210 includes a first region I and a second region II, the second region II surrounds the first region I, and the second region II includes a logic region a; a plurality of probes 220 positioned on the surface of the first zone I; and the logic device 230 is positioned in the logic area A and is used for forming signal transmission with the pixel device.
The probes 220 are electrically connected with the logic device, so that when the pixel devices in the wafer 300 to be tested are electrically connected with the probes 220, the pixel devices can be electrically connected with the logic device 230, and signal transmission is formed.
The second zone II also includes a detection zone B having a detection device therein.
The probe 220 is electrically connected to the detection device.
Specifically, since the detection device is electrically connected to the probe 220, when the pixel device in the wafer 300 to be tested is electrically connected to the probe 220, a detection circuit is formed between the detection device and the pixel device, and by combining with a test program, signals formed by the pixel device in the wafer 300 to be tested and the logic device 230 can be read and distinguished, thereby completing an electrical test process.
A first I surface has a plurality of probes 220, and one probe 220 is electrically connected to a corresponding contact pad 320.
In this embodiment, the wafer test card 200 includes a first area I and a corresponding logic area a.
In other embodiments, the wafer test card comprises: the plurality of probes on the surface of each first area are electrically connected with the plurality of contact pads in the corresponding peripheral area, and the logic device in each logic area is electrically connected with the pixel device in the corresponding pixel area.
FIG. 7 is a schematic structural diagram illustrating a wafer test card testing a wafer to be tested according to an embodiment of the present invention.
Referring to fig. 7, the probes 220 are contacted with the wafer 300 to be tested, so that the pixel devices and the logic device 230 are connected to form signals.
It should be noted that the distribution of the contact pads 320 in the peripheral area 302 matches the distribution of the probes 220 on the surface of the first area I, so that the contact pads 320 can be electrically connected to the probes 220, which is beneficial for the wafer test card 200 to accurately perform the yield test on the wafer 300 to be tested.
It should be noted that the size of each chip area 301 is matched with the size of the corresponding first area I, which is beneficial for the wafer test card 200 to accurately perform the yield test on the pixel devices in each chip area 301.
Specifically, the contact pads 320 contact the probes 220, so that the wafer 300 to be tested contacts the probes 220, and the probes 220 are electrically connected to the wafer 300 to be tested.
Since the wafer 300 to be tested has the pixel devices therein, and the wafer test card 200 has the logic devices 230 therein, the contact pads 320 are in contact with the probes 220, and the contact pads 320 are electrically connected with the probes 220, so that the pixel devices are electrically connected with the logic devices 230, and signals are formed between the pixel devices and the logic devices 230. Moreover, the probe 220 is electrically connected to the logic device 230, the probe 220 is electrically connected to the detection device, and the signal can further pass through the detection device in the wafer test card 200 to form a detection circuit, and the yield test of the wafer to be tested is realized by combining with the detection program.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A wafer test card is used for detecting a wafer to be tested, wherein a pixel device is arranged in the wafer to be tested, and the wafer to be tested is characterized by comprising:
a substrate including a first region and a second region, the second region surrounding the first region, the second region including a logic region;
a plurality of probes positioned on the surface of the first region;
and the logic device is positioned in the logic area and is used for forming signal transmission with the pixel device.
2. The wafer test card of claim 1, wherein the probes are electrically connected to a logic device.
3. The wafer test card of claim 1, wherein the second zone further comprises a detection zone having a detection device therein.
4. The wafer test card of claim 3, wherein the probes and the test devices are electrically connected.
5. The wafer test card of claim 1, wherein the number of the first areas is more than one, and the number of the logic areas is more than one; when the number of the first areas is more than two, and the number of the logic areas is more than two, the plurality of probes on the surface of one first area are electrically connected with the corresponding logic device in one logic area.
6. The wafer test card according to claim 5, wherein the number of the first areas ranges from 1 to 100, and the number of the logic areas ranges from 1 to 100.
7. The wafer test card of claim 1, wherein the first area has a size ranging from 1 mm to 10 mm.
8. The wafer test card of claim 1, wherein the size of the logic area ranges from 1 mm to 10 mm.
9. A wafer testing method, comprising:
providing a wafer to be tested, wherein the wafer to be tested is provided with a pixel device;
providing a wafer test card according to any one of claims 1 to 8;
and contacting the probe with the wafer to be detected, so that the pixel device and the logic device are connected to form a signal.
10. The wafer testing method as claimed in claim 9, wherein the wafer to be tested further comprises: and a plurality of contact pads, one of which is electrically connected with a corresponding one of the probes.
11. The wafer testing method as claimed in claim 9, wherein the wafer to be tested includes a pixel area and a peripheral area around the pixel area; the pixel device is located in a pixel region, the contact pads are located in the peripheral region, and the contact pads surround the pixel region.
12. The wafer test method as claimed in claim 11, wherein the wafer to be tested includes a plurality of chip areas, each of the chip areas includes one of the pixel areas and a peripheral area surrounding the pixel area; the wafer test card comprises a plurality of first areas and a plurality of logic areas, a plurality of probes on the surface of each first area are electrically connected with a plurality of contact pads in a corresponding peripheral area, and a logic device in each logic area is electrically connected with a pixel device in a corresponding pixel area.
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| CN201910973753.3A CN110673016A (en) | 2019-10-14 | 2019-10-14 | Wafer test card and wafer test method |
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