CN110673016A - Wafer test card and wafer test method - Google Patents

Abstract

A wafer test card and a wafer test method, wherein the wafer test card is used to detect a wafer to be tested, and the wafer to be tested has a pixel device, comprising: a substrate, the substrate includes a first area and a second area Two areas, and the second area surrounds the first area, the second area includes a logic area; a number of probes located on the surface of the first area; logic devices located in the logic area, the logic The device is used to form signal transmission with the pixel device. Using the wafer test card for wafer testing can improve detection efficiency and reduce damage.

Description

Wafer test card and wafer test method

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a wafer test card and a wafer test method.

Background technique

The manufacturing process of integrated circuits can usually be divided into wafer process, wafer testing, packaging and final testing. Before chip packaging, it is usually necessary to conduct electrical performance tests on the integrated circuits on the wafer to determine whether the integrated circuits are in good condition. After the packaging process is completed, the integrated circuits must undergo another electrical performance test to screen out the defects caused by the packaging process. The defective products caused by the poor products further improve the yield of the final product. In the prior art, a wafer test card with several probes is usually used, the probes of the wafer test card are contacted with the integrated circuits of the wafer, and a test signal is applied to the integrated circuit to determine its Whether the electrical performance is good.

In the field of semiconductor technology, stacked image sensors are formed by separate manufacturing of logic wafers and pixel wafers and then bonding. Since the logic wafers and pixel wafers are manufactured separately, the manufacturing process is flexible and low-cost, and there is a usable wafer area. The advantages of large and multi-functional wafers that can be integrated together are favored.

However, at present, it is necessary to perform dark field and bright field yield testing on the stacked image sensor after the entire stacking process is completed, so that the existing wafer test card cannot perform dark field yield testing for pixel wafers alone.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a wafer test card and a wafer test method, so as to improve the detection efficiency and reduce the loss.

In order to solve the above technical problems, the technical solution of the present invention provides a wafer test card for testing a wafer to be tested, the wafer to be tested has pixel devices in it, and includes: a substrate, and the substrate includes a first area and a second area. Two areas, and the second area surrounds the first area, the second area includes a logic area; a number of probes located on the surface of the first area; logic devices located in the logic area, the logic The device is used to form signal transmission with the pixel device.

Optionally, the probe is electrically connected to the logic device.

Optionally, the second area further includes a detection area, and the detection area has a detection device.

Optionally, the probe and the detection device are electrically connected.

Optionally, the number of the first area is one or more, and the number of the logic area is more than one; when the number of the first area is two or more, the number of the logic area is two. When there are more than one, a plurality of probes on the surface of one of the first regions are electrically connected to logic devices in a corresponding one of the logic regions.

Optionally, the number of the first areas ranges from 1 to 100, and the number of the logical areas ranges from 1 to 100.

Optionally, the size of the first region ranges from 1 mm to 10 mm.

Optionally, the size of the logic area ranges from 1 mm to 10 mm.

Correspondingly, the technical solution of the present invention also provides a wafer testing method, including: providing a wafer to be tested, the wafer to be tested has pixel devices; providing the wafer test card described in any one of the above; The probe is in contact with the wafer to be tested, so that the pixel device and the logic device are connected to form signal transmission.

Optionally, the wafer to be tested further includes: a plurality of contact pads, one of which is electrically connected to a corresponding one of the probes.

Optionally, the wafer to be tested includes a pixel area and a peripheral area located around the pixel area; the pixel device is located in the pixel area, the contact pads are located in the peripheral area, and the contact pads surround the pixel area. the pixel area.

Optionally, the wafer to be tested includes several chip areas, and each of the chip areas includes one of the pixel areas and a peripheral area surrounding the pixel area; the wafer test card includes several first areas and several In the logic area, a plurality of probes on the surface of each first area are electrically connected with a plurality of contact pads in a corresponding peripheral area, and a logic device in each logic area is electrically connected with a pixel device in a corresponding pixel area.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

In the wafer test card provided by the technical solution of the present invention, the wafer test card is used to detect the wafer to be tested, and the wafer to be tested has pixel devices therein. Because the second area of the wafer test card includes: a logic area, and the logic area has logic devices. When the wafer test card is used for dark field yield measurement of the wafer to be tested, the logic device can be electrically connected with the pixel device to form signal transmission, so that the wafer test card can be used to test the wafer to be tested with only pixel devices. Wafers are inspected to improve inspection efficiency and save costs.

Further, since the wafer test card may have multiple first areas and multiple logic areas, and several probes on the surface of one of the first areas are electrically connected to the logic devices in the corresponding one of the logic areas, so that The wafer test card can simultaneously perform yield detection on multiple chip regions in the wafer to be tested at one time, so as to further improve the detection efficiency, save the detection time and save the cost.

In the wafer testing method provided by the technical solution of the present invention, since the wafer to be tested has pixel devices, and the wafer test card has logic devices, the probes are in contact with the wafer to be tested, The pixel device and the logic device are electrically connected, so that signal transmission is formed between the pixel device and the logic device. In addition, the signal can further pass through the detection device in the wafer test card to form a detection circuit, and combined with the detection procedure, realize the yield test of the wafer to be tested. The method is simple, can improve detection efficiency, save detection time and cost.

Description of drawings

1 is a schematic structural diagram of a wafer test card;

2 is a schematic structural diagram of a wafer to be tested in an embodiment of the present invention;

3 and 4 are schematic structural diagrams of a wafer test card in an embodiment of the present invention;

5 is a schematic structural diagram of a wafer test card in another embodiment of the present invention;

6 is a schematic flowchart of a wafer testing method according to an embodiment of the present invention;

7 is a schematic structural diagram of a wafer test card for testing a wafer to be tested in an embodiment of the present invention.

Detailed ways

As mentioned in the background art, the test efficiency of the existing wafer test card is poor.

The reasons for the poor test efficiency of the wafer test card will be described in detail below with reference to the accompanying drawings. FIG. 1 is a schematic structural diagram of a wafer test card.

Referring to FIG. 1, a wafer test card includes: a substrate 100, the substrate 100 includes a first area A and a second area B, and the second area B surrounds the first area A; the first area The surface of a region A has several probes 101; the second region B has detection devices (not shown in the figure).

In the above structure, the surface of the first area A has probes 101 for guiding the signals of the wafer to be tested to the second area B in the wafer test card. There is a detection device in the second area B. When the detection device detects the signal conducted by the probe 101, the second area B will combine the test program to read and discriminate the acquired signal, so as to achieve Test the darkfield yield of the wafer to be tested.

When the wafer to be tested is a stacked image sensor, the stacked image sensor is required to be a device formed by a stacking process. A stacked image sensor is a pixel wafer and a logic wafer through a bonding process. Forming. Since both the logic wafer and the pixel wafer are jointly used to form a complete image sensor, when the logic wafer and the pixel wafer are not subjected to the bonding process to form the wafer to be tested, the existing wafer test card cannot Yield testing is performed on pixel wafers or logic wafers individually.

However, since the pixel wafer and the logic wafer need to be processed in different processes respectively. When there is a problem with the process of the pixel wafer, it is required that after the process of the logic wafer is completed, the formed pixel wafer and the logic wafer are bonded to form a complete image sensor as the wafer to be tested. Circle, the wafer test card is used for the total test, and then the pixel wafer can be detected to have problems, resulting in poor dark field test efficiency and corresponding increase in detection time and detection cost.

In order to solve the technical problem, an embodiment of the present invention provides a wafer test card for testing a wafer to be tested, the wafer to be tested has pixel devices in it, and includes: a substrate, the substrate includes a first area and a a second area, and the second area surrounds the first area, the second area includes a logic area; a number of probes located on the surface of the first area; logic devices located in the logic area, the The logic device is used to form signal transmission with the pixel device. Using the wafer test card for wafer testing can improve detection efficiency and reduce losses.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 is a schematic structural diagram of a wafer to be tested in an embodiment of the present invention.

Please refer to FIG. 2 , a wafer 300 to be tested has pixel devices (not shown in the figure) in the wafer 300 to be tested.

In this embodiment, the pixel device may include a photodiode (not shown in the figure) and a pixel circuit, wherein the pixel circuit may include various appropriate transistors such as a selection transistor, a reset transistor, and a source follower transistor. The device, for example, may include a transfer gate and a floating diffusion region. It should be noted that, in this embodiment, the specific composition of the pixel circuit is not limited.

In this embodiment, the wafer to be tested 300 further includes: a plurality of contact pads 320 .

The material of the contact pad 320 includes one or more combinations of titanium, nickel, copper, tungsten, aluminum, titanium, silver and tantalum.

The wafer to be tested 300 includes a pixel area 301 and a peripheral area 302 located around the pixel area 301; the pixel device is located in the pixel area 301, the contact pads 320 are located in the peripheral area 302, and a number of Contact pads 320 surround the pixel region 301 .

In this embodiment, the wafer to be tested 300 includes a plurality of chip regions C, and each of the chip regions C includes one of the pixel regions 301 and a peripheral region 302 surrounding the pixel regions 301 .

3 and 4 are schematic structural diagrams of a wafer test card according to an embodiment of the present invention.

Please refer to FIG. 3 and FIG. 4 . FIG. 4 is a schematic cross-sectional structure diagram of FIG. 3 along the M-N tangent direction. A wafer test card 200 is used to detect a wafer to be tested 300 , and the wafer to be tested 300 has pixels in it. The device includes: a substrate 210, the substrate 210 includes a first region I and a second region II, and the second region II surrounds the first region I, and the second region II includes a logic region A; Several probes 220 on the surface of the first region I; logic devices 230 located in the logic region A, and the logic devices 230 are used for signal transmission with the pixel devices.

In this embodiment, the material of the substrate 210 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the probes 220 and the logic device 230 are electrically connected.

Because the probes 220 and the logic device 230 are electrically connected, when the pixel device in the wafer under test 300 is electrically connected to the probes 220, it can be electrically connected to the logic device 230 to form signal transmission.

Please continue to refer to FIG. 3 and FIG. 4 , the second area II further includes a detection area B, and the detection area B has a detection device (not shown in the figures).

In this embodiment, the probe 220 is electrically connected to the detection device.

Since the detection device is electrically connected to the probe 220, when the pixel device in the wafer to be tested 300 is in contact with the probe 220, a detection circuit is formed between the detection device and the pixel device. The signals formed by the pixel device and the logic device 230 in the wafer to be tested 300 are read and discriminated to complete the electrical testing process.

The number of the first area I is more than one, and the number of the logic area A is more than one; when the number of the first area I is more than two, the number of the logic area A is two. When there are more than one, the probes 220 on the surface of one of the first regions I are electrically connected to the logic devices in the corresponding one of the logic regions A.

The number of the first areas ranges from 1 to 100, and the number of the logical areas ranges from 1 to 100.

In this embodiment, the number of the first area I is one, the number of the logic area A is one, and a plurality of probes 220 on the surface of the first area I and a corresponding one of the logic The logic devices 230 in region A are electrically connected.

In other embodiments, the number of the logical areas is two or more, and the number of the logical areas is two or more.

The wafer test card 200 is used for testing the wafer 300 to be tested, and the wafer to be tested 300 has pixel devices therein. Because the second area II of the wafer test card 200 includes: the logic area A, and the logic area A has the logic device 230 therein. When using the wafer test card 200 to perform dark field yield measurement on the wafer 300 to be tested, the logic device 230 can be electrically connected with the pixel device to form signal transmission, so that the wafer test card 200 The wafer to be tested 300 of the device is inspected, so as to improve the inspection efficiency and save the cost.

The size of the first region ranges from 1 mm to 10 mm.

The size of the logic area ranges from 1 mm to 10 mm.

FIG. 5 is a schematic structural diagram of a wafer test card in another embodiment of the present invention.

Referring to FIG. 5, a wafer test card 400 is used for testing a wafer 300 to be tested. The wafer to be tested 300 has pixel devices in it, including: a substrate (not shown in the figure), the substrate includes a first A region I and a second region II, and the second region II surrounds the first region I, the second region II includes a logic region A; a number of probes 420 located on the surface of the first region I; The logic device (not shown in the figure) in the logic area A is used to form signal transmission with the pixel device.

In this embodiment, the number of the first area I is five, the number of the logic area A is five, and a plurality of probes 420 on the surface of the first area I and a corresponding one The logic devices in the logic region A are electrically connected.

Since the wafer test card 400 has a plurality of first areas I and a plurality of logic areas A, and a plurality of probes 420 on the surface of the first area I and a corresponding logic device in the logic area A are electrically The connection enables the wafer test card 400 to simultaneously perform yield detection on multiple chip regions 301 in the wafer to be tested 300 at one time, so as to further improve the detection efficiency, save the detection time and save the cost.

FIG. 6 is a schematic flowchart of a wafer testing method according to an embodiment of the present invention.

Referring to FIG. 6, a wafer testing method includes:

S1: provide a wafer to be tested, and the wafer to be tested has pixel devices;

S2: Provide the above wafer test card;

S3: Contact the probe with the wafer to be tested, so that the pixel device and the logic device are connected to form a signal.

The wafer testing method will be described in detail below with reference to the accompanying drawings.

Please continue to refer to FIG. 2 , a wafer 300 under test is provided, and the wafer under test 300 has pixel devices therein.

The wafer under test 300 further includes a plurality of contact pads 320 .

The contact pads 320 are used for subsequent electrical connection with the probes in the wafer test card, so that the wafer test card forms an electrical connection between the probes and the contact pads 320 , so that the wafer to be tested can be tested for yield.

Please continue to refer to FIG. 3 and FIG. 4 , the above-mentioned wafer test card 200 is provided.

The wafer test card 200 includes: a substrate 210, the substrate 210 includes a first area I and a second area II, the second area II surrounds the first area I, and the second area II includes logic Area A; a plurality of probes 220 located on the surface of the first area I; logic devices 230 located in the logic area A, the logic devices are used for signal transmission with pixel devices.

The probes 220 are electrically connected to the logic devices, so that when the pixel devices in the wafer under test 300 are electrically connected to the probes 220, they can be electrically connected to the logic devices 230 to form signal transmission.

The second area II further includes a detection area B, and the detection area B has a detection device therein.

The probe 220 is electrically connected to the detection device.

Specifically, since the detection device is electrically connected to the probe 220, when the pixel device in the wafer to be tested 300 is electrically connected to the probe 220, a detection circuit is formed between the detection device and the pixel device, and through the combined test The program can read and discriminate the signals formed by the pixel device and the logic device 230 in the wafer to be tested 300 to complete the electrical testing process.

A surface of the first region I has several probes 220 , and one probe 220 is electrically connected to a corresponding contact pad 320 .

In this embodiment, the wafer test card 200 includes a first area I and a corresponding logic area A.

In other embodiments, the wafer test card includes: a number of first areas and a number of logic areas, a number of probes on the surface of each first area are electrically connected to a number of contact pads in a corresponding peripheral area, each logic area The logic device within the region is electrically connected to the pixel device within a corresponding pixel region.

7 is a schematic structural diagram of a wafer test card for testing a wafer to be tested in an embodiment of the present invention.

Referring to FIG. 7 , the probes 220 are brought into contact with the wafer 300 to be tested, so that the pixel device and the logic device 230 are connected to form signals.

It should be noted that the distribution of the contact pads 320 in one peripheral area 302 matches the distribution of the probes 220 on the surface of the first area I, so that the contact pads 320 can be better electrically connected to the probes 220. This facilitates the accurate yield test of the wafer to be tested 300 on the wafer test card 200 .

It should be noted that the size of each chip area 301 matches the size of the corresponding first area I, which is beneficial for the wafer test card 200 to accurately perform a yield test on the pixel devices in each chip area 301.

Specifically, the contact pads 320 are in contact with the probes 220 , so that the wafer under test 300 is in contact with the probes 220 , so that the probes 220 are electrically connected to the wafer under test 300 .

Since the wafer under test 300 has pixel devices, and the wafer test card 200 has logic devices 230, the plurality of contact pads 320 are in contact with the plurality of probes 220, and the plurality of contact pads 320 and the plurality of probes 220 The electrical connection is formed so that the pixel device and the logic device 230 are electrically connected, so that a signal is formed between the pixel device and the logic device 230 . In addition, the probe 220 is electrically connected to the logic device 230, the probe 220 is electrically connected to the detection device, and the signal can further pass through the detection device in the wafer test card 200 to form a detection circuit, and combined with the detection program, Realize the yield test of the wafer to be tested.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (12)

1. A wafer test card is used for detecting a wafer to be tested, wherein a pixel device is arranged in the wafer to be tested, and the wafer to be tested is characterized by comprising:

a substrate including a first region and a second region, the second region surrounding the first region, the second region including a logic region;

a plurality of probes positioned on the surface of the first region;

and the logic device is positioned in the logic area and is used for forming signal transmission with the pixel device.

2. The wafer test card of claim 1, wherein the probes are electrically connected to a logic device.

3. The wafer test card of claim 1, wherein the second zone further comprises a detection zone having a detection device therein.

4. The wafer test card of claim 3, wherein the probes and the test devices are electrically connected.

5. The wafer test card of claim 1, wherein the number of the first areas is more than one, and the number of the logic areas is more than one; when the number of the first areas is more than two, and the number of the logic areas is more than two, the plurality of probes on the surface of one first area are electrically connected with the corresponding logic device in one logic area.

6. The wafer test card according to claim 5, wherein the number of the first areas ranges from 1 to 100, and the number of the logic areas ranges from 1 to 100.

7. The wafer test card of claim 1, wherein the first area has a size ranging from 1 mm to 10 mm.

8. The wafer test card of claim 1, wherein the size of the logic area ranges from 1 mm to 10 mm.

9. A wafer testing method, comprising:

providing a wafer to be tested, wherein the wafer to be tested is provided with a pixel device;

providing a wafer test card according to any one of claims 1 to 8;

and contacting the probe with the wafer to be detected, so that the pixel device and the logic device are connected to form a signal.

10. The wafer testing method as claimed in claim 9, wherein the wafer to be tested further comprises: and a plurality of contact pads, one of which is electrically connected with a corresponding one of the probes.

11. The wafer testing method as claimed in claim 9, wherein the wafer to be tested includes a pixel area and a peripheral area around the pixel area; the pixel device is located in a pixel region, the contact pads are located in the peripheral region, and the contact pads surround the pixel region.

12. The wafer test method as claimed in claim 11, wherein the wafer to be tested includes a plurality of chip areas, each of the chip areas includes one of the pixel areas and a peripheral area surrounding the pixel area; the wafer test card comprises a plurality of first areas and a plurality of logic areas, a plurality of probes on the surface of each first area are electrically connected with a plurality of contact pads in a corresponding peripheral area, and a logic device in each logic area is electrically connected with a pixel device in a corresponding pixel area.

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