CN113921514A

CN113921514A - Test wafer, chip forming method and chip testing method

Info

Publication number: CN113921514A
Application number: CN202111145686.XA
Authority: CN
Inventors: 王贻源
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2021-09-28
Filing date: 2021-09-28
Publication date: 2022-01-11

Abstract

The application discloses test wafer, chip forming method and chip testing method, wherein the test wafer comprises: the memory device comprises a plurality of memory dies, a plurality of testing areas and a plurality of control modules, wherein each memory die is provided with a plurality of testing areas, and each testing area comprises a control logic area and a pad area which are electrically connected; the control logic area is electrically connected with the corresponding memory bare chip and is integrated with the control logic of the logic bare chip; the pad area is used for wafer probe CP testing.

Description

Test wafer, chip forming method and chip testing method

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a test wafer, a chip forming method, and a chip testing method.

Background

The manufacturing process of integrated circuits can be generally divided into wafer processing, wafer testing, packaging and final testing. Before the chip is packaged, an electrical performance test is usually performed on the integrated circuit on the wafer to determine whether the integrated circuit is good, and another electrical performance test is performed on the integrated circuit after the packaging process is completed to screen out a defective product caused by the poor packaging process, so as to further improve the yield of the final finished product. In the related art, a wafer tester having a plurality of probes is usually used, the probes of the wafer tester are contacted with the integrated circuits of the wafer, and test signals are applied to the integrated circuits to determine whether the electrical performance of the integrated circuits is good.

However, such probe probing can only be performed on the wafers that have already been bonded, and once a defect exists in the memory wafer of the bonded wafers, the logic wafer bonded with the defect is also scrapped.

Disclosure of Invention

Embodiments of the present application are intended to provide a test wafer, a chip forming method, and a chip testing method.

The technical scheme of the application is realized as follows:

a first aspect of an embodiment of the present application provides a test wafer, where the test wafer includes:

the memory device comprises a plurality of memory dies, a plurality of testing areas and a plurality of control modules, wherein each memory die is provided with a plurality of testing areas, and each testing area comprises a control logic area and a pad area which are electrically connected;

the control logic area is electrically connected with the corresponding memory bare chip and is integrated with the control logic of the logic bare chip;

the pad area is used for wafer probe CP testing.

Optionally, the control logic comprises: memory cell repair logic and memory cell control logic.

Optionally, the control logic is configured to control at least one of the following test operations to be performed: the method comprises the steps of testing short circuit of a storage unit, testing open circuit of the storage unit, testing short circuit between adjacent storage units, testing short circuit of an address, testing open circuit of the address and testing interference of the storage unit.

Optionally, the memory die is a DRAM memory die, or an SRAM memory die, or an MRAM memory die.

Optionally, the test region is located at an edge region of the memory die.

Optionally, the pad region is located at the highest metal layer.

Optionally, the pad area is smaller in area than the logic integration area.

Optionally, the pad region is disposed above the logic integration region.

Optionally, a total area of the plurality of test regions is less than 0.5% of an area of the memory die.

A second aspect of the embodiments of the present application provides a chip forming method, including:

providing a test wafer according to the first aspect;

dicing the test wafer to obtain a plurality of memory dies;

bonding the memory die with the logic die on a logic wafer to form a memory chip.

A third aspect of the embodiments of the present application provides a chip testing method, including:

providing a test wafer according to the first aspect;

the pad area is contacted by a test probe to perform a wafer probe CP test on the test die based on the control logic of the logic die integrated by the control logic area.

The application discloses a test wafer, a chip forming method and a chip testing method, wherein the test wafer comprises: the memory device comprises a plurality of memory dies, a plurality of testing areas and a plurality of control modules, wherein each memory die is provided with a plurality of testing areas, and each testing area comprises a control logic area and a pad area which are electrically connected; the control logic area is electrically connected with the corresponding memory bare chip and is integrated with the control logic of the logic bare chip; the pad area is used for wafer probe CP testing. According to the method and the device, the control logic area is arranged on the storage bare chip, the control logic on the logic bare chip is transferred to the control logic area of the storage bare chip, and the pad area is arranged to perform probe test, so that the storage bare chip can be tested independently before the storage bare chip is bonded with the logic wafer, the rejection rate of the logic wafer is effectively reduced, and the encapsulation test cost is saved.

Drawings

Fig. 1 is a schematic structural diagram of a three-dimensional memory chip according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a test wafer according to an embodiment of the present disclosure;

fig. 3 is a flowchart illustrating a method for forming a memory chip according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the steps. For example, some steps may be decomposed, and some steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

It will be appreciated that spatial relationship terms, such as "under … …," "under … …," "under … …," "over … …," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The memory chip is a specific application of the concept of an embedded system chip in the memory industry. Therefore, both system chips and memory chips are implemented with multiple functions and high performance, and support for multiple protocols, multiple hardware and different applications by embedding software in a single chip. Depending on the characteristics, the Memory devices corresponding to the Memory chips can be classified into Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), FLASH Memory (FLASH), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), etc., which are widely used in various electronic devices and occupy important positions in the circuits.

The logic chip may be a CMOS chip. The logic chip is generally used to complete bonding with the memory chip, and provide control logic, repair logic, etc. for the memory chip, so that the memory cells in the memory chip perform corresponding functions.

Currently, the bonding method is more commonly used to cut a memory wafer into a plurality of memory dies, then bond the plurality of memory dies and a logic wafer, then perform wafer cutting to form memory dies, and package the memory dies to form memory chips.

In an example, referring to fig. 1, fig. 1 is a schematic structural diagram of a three-dimensional memory chip according to an embodiment of the present disclosure, where a top layer is a memory die 100(memory die), an intermediate layer is a Logic die 101(Logic die), a dashed line represents a bonding surface between the memory die 100 and the Logic die 101, and a bottom layer is a package substrate and a motherboard. The memory die may be, for example, a DRAM memory die, or an SRAM memory die, or an MRAM memory die). Specifically, the Chip Substrate 110(Chip Substrate), the memory device Layer 120(memory device Layer), the Metal Layer 130(Metal Layer), the Hybrid bonding Layer 140(Hybrid Bond Layer), the Metal Layer (not labeled in the figure), the Logic device Layer 150(Logic device Layer), the Chip Substrate (not labeled in the figure), the flip Chip bonding micro-Bumps 160 (flip Chip Bumps), the Package Substrate 170 (Silicon Substrate), the Package bonding micro-Bumps 180(Package Bumps), and the motherboard 190 are arranged in sequence from top to bottom, wherein Through Silicon Vias (TSVs) are further present in the Logic device Layer and the Chip Substrate thereof to complete interlayer interconnection. The bonding packaging of the memory die and the logic die can be realized through processes such as bonding and packaging.

Here, the through silicon via technology is a high-density packaging technology, and vertical electrical interconnection of through silicon vias is realized by filling conductive substances such as copper, tungsten, polysilicon, and the like. Through vertical electrical interconnection, the interconnection length is reduced, so that the signal delay is reduced, the capacitance/inductance is reduced, low power consumption and high-speed communication among chips are realized, the broadband is increased, and the miniaturization of device integration is realized.

In this example, the memory die and the logic die are bonded by a hybrid bonding technique. Hybrid bonding technology is a relatively common wafer bonding method, including insulator-insulator bonding, semiconductor-semiconductor bonding, and metal-metal bonding, for example, and can ensure stability and reliability of wafer bonding.

Generally, for the specific case of wafer bonding, it can be obtained by performing wafer probe CP test on the wafer. Wafer prober CP testing typically requires the use of a prober, or prober card. The probe test board can be used for fixing a bonded wafer to be tested, the probe test card comprises a probe head which is used for contacting with the bonded wafer and establishing signal connection, and the probe test machine is provided with a corresponding test system which can control a test flow based on an application test program of the test system. After receiving the control instruction, the test system sends out a special electronic signal, the electronic signal is transmitted to the bonded wafer through a probe head on the probe test card, the bonded wafer sends out a feedback signal after receiving the electronic signal, and the feedback signal returns to the test system through the probe test card. Therefore, the test system can judge the specific condition of the bonded wafer based on the feedback signal, for example, the feedback signal is accurate, and the bonded wafer is represented to be good if the feedback time is within the expected time; on the contrary, the bonded wafer has defects. Further, the defect type of the chip can be analyzed according to the error type of the feedback signal. It should be noted that the above-mentioned bonded wafer is a wafer that has completed the bonding step.

However, the wafer probe CP test described above can only be performed on a wafer that has completed a bonding step. Before bonding, it is difficult to perform a wafer probe CP test on a memory die on a memory wafer alone, and since a DRAM die, an SRAM die, or an MRAM die, which is a memory die, is supplied with a control signal through a logic die, the number of metal layers of the memory die is small, the thickness of the metal layers is thin, and CP pricking cannot be performed. If the needle is pricked, the metal layer and the device below the metal layer are damaged, and the corresponding logic function test is difficult to perform due to the lack of the corresponding logic function on the memory bare chip, so that the memory bare chip cannot be tested independently. If the memory die is not tested before bonding, the logic die or the logic wafer bonded with the memory die will be rejected once the memory die has defects or other performance problems, and for heterogeneous integrated chips, the process of the logic die or the logic wafer is generally advanced, for example, 7nm/14nm/16nm, and the rejection of the logic die or the logic wafer causes a large cost loss, in addition to the bonding cost and even the loss of the packaging cost.

In an embodiment, please refer to fig. 2, fig. 2 is a partial structural diagram of a test wafer according to an embodiment of the present disclosure. The test wafer includes:

a plurality of memory dies 210, each memory die 210 having a plurality of test areas thereon, each test area including a control logic area 220 and a pad area 230 electrically connected thereto;

the control logic area 220 is electrically connected with the corresponding memory die 210, and the control logic area 220 is integrated with the control logic of the logic die;

the pad area 230 is used for wafer probe CP testing.

In the present embodiment, one memory die 210 in a test wafer is taken as an example for illustration, and here, the memory die 210 may be a DRAM memory die, an SRAM memory die, or an MRAM memory die, and of course, may also be other types of memory dies, which is not exhaustive here.

The memory die 210 is provided with a plurality of test regions, in one example, the test regions are located at edge regions of the memory die, specifically, the test regions are located at four corner regions of the memory die 210, and the test regions may be rectangular, circular, or irregular, which is not limited herein. The area of the test region may be the smallest area that can implement the control logic integration, so that the area loss of the memory die 210 can be guaranteed to be the smallest after the test operation is performed, where the number of the test regions is not limited to 4, but may also be 3, 5, and the like, without limitation.

The test area includes an electrically connected control logic area 220 and a pad area 230, wherein the control logic area 220 is used for integrating a part of control logic on the logic die, and the pad area 230 is used for contacting with the CP wafer probe, which cooperate with each other to realize logic function test on the memory die based on the control logic before bonding.

In one embodiment, the control logic comprises: memory cell repair logic and memory cell control logic.

Here, the control logic may include a portion of the control logic on the logic die.

Wherein the memory cell repair logic may provide universal redundancy repair for the memory stack. In view of the subsequent stacking and packaging processes, defective memory cells may occur on the memory dies after manufacturing, and therefore, the defective memory cells need to be repaired by the repair logic, and different types of memory dies in the memory can be repaired by the repair logic of the memory cells, or the failure of the memory cells is avoided, for example, the content addressable memory CAM replaces the failure addresses on the memory dies, or the memory addresses are directly changed to avoid the defective parts of the memory cells.

The memory cell control logic may be configured to store information such as a pre-written control command to control the memory die to perform a corresponding test operation or access operation.

In one embodiment, the control logic is to control performance of at least one of the following test operations: the method comprises the steps of testing short circuit of a storage unit, testing open circuit of the storage unit, testing short circuit between adjacent storage units, testing short circuit of an address, testing open circuit of the address and testing interference of the storage unit.

The memory cell short circuit test comprises a short circuit test between a memory cell and a power supply or ground, the memory cell open circuit test comprises a state test of the memory cell during writing, the short circuit test between adjacent memory cells comprises a test of data written in the adjacent memory cells during production, the address short circuit or address open circuit test comprises that one memory cell corresponds to a plurality of addresses or a plurality of addresses correspond to a corresponding test of output of one memory cell, and the memory cell interference comprises a state test of the adjacent memory cells during writing or reading.

Once a memory die contains any type of error, it may affect the function of the bonded memory chip and even cause the bonded memory chip to be rejected, and therefore, the above test operation needs to be performed under the control of the control logic integrated in the control logic area on the memory die to discriminate the memory die with defects.

In one embodiment, the pad region is located at the top metal (top metal).

Here, the highest metal layer (top metal) is located above the memory die, which can enable electrical tapping of the memory die. On the other hand, the electrical connection exists between the highest metal layer and the memory unit in the memory die, so that the probe of the CP wafer can contact with the pad area, the electrical test of the memory die is directly completed, and the damage of the probe to the memory die is avoided.

In one embodiment, a pad region is disposed above the logic integration region, and an area of the pad region is smaller than an area of the logic integration region.

In this embodiment, the logic integration region and the pad region are stacked, and the logic integration region and the pad region are sequentially disposed from bottom to top, and the area of the pad region is smaller than that of the logic integration region, so that only the area of the stacked logic integration region needs to be provided on the memory die, and no additional pad region needs to be provided, thereby reducing the area loss of the memory die.

In this embodiment, the total area of the plurality of test regions is less than 0.5% of the area of the memory die.

The test areas in fig. 2 are only schematic representations, and the actual size of the test areas may be smaller on an actual memory die. In particular toFor an area of 130mm²Only approximately 0.5% of the area of the memory die is required to be provided as a test area for setting the logic integration area and the pad area. When the area of the memory die is larger, the area of the test area will occupy less area on the memory die and the area loss for the memory die will be smaller.

According to the embodiment of the application, the control logic area is arranged on the storage bare chip, part of control logic on the logic bare chip is transferred to the control logic area of the storage bare chip, the pad area is arranged to perform probe test, and the logic function test of the storage bare chip is completed, so that the logic function of the storage bare chip can be tested before bonding, the rejection rate of the logic bare chip or the logic wafer is effectively reduced, the subsequent bonding cost and the packaging cost can be saved, and the yield of products is improved to a great extent.

In one embodiment, the present application provides a chip forming method, including:

providing the test wafer;

cutting the test wafer to obtain a plurality of memory dies;

the memory die is bonded with the logic die on the logic wafer to form a memory chip.

Here, the test wafer includes: the device comprises a plurality of memory dies, a plurality of testing areas and a plurality of control modules, wherein each memory die is provided with a plurality of testing areas, and each testing area comprises a control logic area and a pad area which are electrically connected; the control logic area is electrically connected with the corresponding memory bare chip and is integrated with the control logic of the logic bare chip; the pad area is used for CP wafer probe testing.

In one embodiment, as shown in fig. 3, the chip forming method includes the steps of:

step 310, providing a test wafer;

step 320, performing a wafer probe CP test on the test wafer;

step 330, judging whether the test wafer has defects;

in the present embodiment, if the test wafer has no defect, step 340 is performed.

Step 340, cutting the test wafer into a plurality of memory dies, and bonding the memory dies with the logic wafer;

step 350, carrying out wafer probe CP test on the bonded wafer;

step 360, judging whether the bonded wafer has defects;

in this embodiment, if there is no defect in the bonded wafer, step 370 is performed.

Step 370, the bonded wafer is diced and sealed.

Before step 340, step 341: a logic wafer is provided. In the present embodiment, if the test wafer has no defect, step 341 is performed. The test wafer is the test wafer provided with the control logic area and the pad area mentioned in the above embodiment, each memory die in the test wafer is tested based on the wafer probe CP, whether the test wafer has a defective memory die or not is judged, the test wafer is cut, and if the memory die having the defect exists, the test wafer is rejected; and if the memory chips do not exist, bonding the plurality of memory bare chips obtained by cutting with the plurality of logic bare chips on the logic wafer, performing wafer probe CP test on the bonded wafer after the bonding operation is completed, and if the bonded wafer does not have defects, performing cutting and sealing test on the bonded wafer to form a perfect memory chip.

Wherein the memory cell repair logic may provide universal redundancy repair for the memory stack. In view of the subsequent stacking and packaging processes, defective memory cells may occur on the memory dies after manufacturing, and therefore, the defective memory cells need to be repaired by the repair logic, and different types of memory dies in the memory can be repaired by the repair logic of the memory cells, or the failure of the memory cells is avoided, for example, the content addressable memory CAM replaces the failure addresses on the memory dies, or the memory addresses are directly changed to avoid the defective parts of the memory cells. The memory cell control logic may be configured to store information such as a pre-written control command to control the memory die to perform a corresponding test operation or a memory operation.

In one embodiment, the control logic is to control performance of at least one of the following test operations: a memory cell short circuit test, a memory cell open circuit test, a short circuit test between adjacent memory cells, an address short circuit test, or an address open circuit test and a memory cell disturb test.

Once a memory die contains any type of error, it may affect the function of the bonded memory chip and even cause the bonded memory chip to be rejected, and therefore, the control logic is required to perform the test operation to discriminate the memory die with defects.

After the CP wafer probe is used for testing the test wafer, and the memory dies with defects are removed, a plurality of intact memory dies can be obtained, and the memory dies and the logic dies can be bonded through a hybrid bonding technology, so that a memory chip with good performance is formed.

According to the embodiment of the application, the control logic area is arranged on the storage bare chip, part of control logic on the logic bare chip is transferred to the control logic area of the storage bare chip, the pad area is arranged to perform probe test, and the logic function test on the storage bare chip is completed, so that the logic function of the storage bare chip can be tested before bonding, further, the waste of the logic bare chip caused by the defect of the storage bare chip is avoided, the raw material cost is effectively reduced, the subsequent bonding cost and the packaging cost can be saved, and the yield of products is improved to a great extent.

In one embodiment, an embodiment of the present application provides a chip testing method, including:

providing the test wafer;

the pad area is contacted by the test probe to perform a wafer probe CP test on the test die based on the control logic of the logic die integrated with the control logic area.

Here, the test wafer includes: the device comprises a plurality of memory dies, a plurality of testing areas and a plurality of control modules, wherein each memory die is provided with a plurality of testing areas, and each testing area comprises a control logic area and a pad area which are electrically connected; the control logic area is electrically connected with the corresponding memory bare chip and is integrated with the control logic of the logic bare chip; the pad area is used for wafer probe CP testing. Specific examples are described in the above examples of the test wafer, and are not described in detail herein.

The memory cell repair logic may provide, among other things, universal redundancy repair for the memory stack, and may specifically repair different types of memory dies in the memory or circumvent failure of the memory cells. The memory cell control logic may be configured to store information such as a control command written in advance, so as to control the memory die to perform a corresponding test operation or a corresponding memory operation, such as a memory cell short circuit test, a memory cell open circuit test, a short circuit test between adjacent memory cells, an address short circuit or address open circuit test, a memory cell disturb test, and the like. Specific examples are described in the above examples of the test wafer, and are not described in detail herein.

According to the embodiment of the application, the CP wafer probe is contacted with the pad area on the storage bare chip, and the function test of the storage bare chip is completed based on the control logic area integrated with the control logic on the storage bare chip, so that the logic function test of the storage bare chip is realized based on the control logic before bonding, the rejection rate of the logic bare chip or the logic wafer is effectively reduced, the subsequent bonding cost and the packaging cost can be saved, and the yield of products is improved to a great extent.

The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.

Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.

The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the modules is only one logical functional division, and other division manners may be implemented in practice, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or modules may be electrical, mechanical or other forms.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network modules; some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, all functional modules in the embodiments of the present application may be integrated into one processing module, or each module may be separately used as one module, or two or more modules may be integrated into one module; the integrated module can be realized in a hardware form, and can also be realized in a form of hardware and a software functional module.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A test wafer, comprising:

the pad area is used for wafer probe CP testing.

2. The test wafer of claim 1, the control logic comprising: memory cell repair logic and memory cell control logic.

3. The test wafer of claim 1, wherein the control logic is configured to control at least one of the following test operations to be performed: the method comprises the steps of testing short circuit of a storage unit, testing open circuit of the storage unit, testing short circuit between adjacent storage units, testing short circuit of an address, testing open circuit of the address and testing interference of the storage unit.

4. The test wafer of claim 1, wherein the memory die is a DRAM memory die, or an SRAM memory die, or an MRAM memory die.

5. The test wafer of claim 1, wherein the test area is located at an edge region of the memory die.

6. The test wafer of claim 1, wherein the pad region is located at a highest metal layer.

7. The test wafer of claim 1, wherein an area of the pad region is smaller than an area of the logic integration region.

8. The test wafer of claim 1, wherein the pad region is disposed above the logic integration region.

9. The test wafer of claim 1, wherein a total area of the plurality of test regions is less than 0.5% of an area of the memory die.

10. A method of forming a memory chip, the method comprising:

providing a test wafer according to any one of claims 1 to 9;

dicing the test wafer to obtain a plurality of memory dies;

11. A method for testing a chip, comprising:

providing a test wafer according to any one of claims 1 to 9;

12. The chip testing method of claim 11, wherein the control logic comprises: memory cell repair logic and memory cell control logic.